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1 #ifndef __ASM_ARM_CPUTYPE_H
2 #define __ASM_ARM_CPUTYPE_H
3 
4 #include <linux/stringify.h>
5 
6 #define CPUID_ID	0
7 #define CPUID_CACHETYPE	1
8 #define CPUID_TCM	2
9 #define CPUID_TLBTYPE	3
10 
11 #ifdef CONFIG_CPU_CP15
12 #define read_cpuid(reg)							\
13 	({								\
14 		unsigned int __val;					\
15 		asm("mrc	p15, 0, %0, c0, c0, " __stringify(reg)	\
16 		    : "=r" (__val)					\
17 		    :							\
18 		    : "cc");						\
19 		__val;							\
20 	})
21 #else
22 extern unsigned int processor_id;
23 #define read_cpuid(reg) (processor_id)
24 #endif
25 
26 /*
27  * The CPU ID never changes at run time, so we might as well tell the
28  * compiler that it's constant.  Use this function to read the CPU ID
29  * rather than directly reading processor_id or read_cpuid() directly.
30  */
read_cpuid_id(void)31 static inline unsigned int __attribute_const__ read_cpuid_id(void)
32 {
33 	return read_cpuid(CPUID_ID);
34 }
35 
read_cpuid_cachetype(void)36 static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
37 {
38 	return read_cpuid(CPUID_CACHETYPE);
39 }
40 
41 /*
42  * Intel's XScale3 core supports some v6 features (supersections, L2)
43  * but advertises itself as v5 as it does not support the v6 ISA.  For
44  * this reason, we need a way to explicitly test for this type of CPU.
45  */
46 #ifndef CONFIG_CPU_XSC3
47 #define cpu_is_xsc3()	0
48 #else
cpu_is_xsc3(void)49 static inline int cpu_is_xsc3(void)
50 {
51 	if ((read_cpuid_id() & 0xffffe000) == 0x69056000)
52 		return 1;
53 
54 	return 0;
55 }
56 #endif
57 
58 #if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3)
59 #define	cpu_is_xscale()	0
60 #else
61 #define	cpu_is_xscale()	1
62 #endif
63 
64 #endif
65