1 /* 2 * cx18 ADEC header 3 * 4 * Derived from cx25840-core.h 5 * 6 * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl> 7 * Copyright (C) 2008 Andy Walls <awalls@radix.net> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 2 12 * of the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 22 * 02110-1301, USA. 23 */ 24 25 #ifndef _CX18_AV_CORE_H_ 26 #define _CX18_AV_CORE_H_ 27 28 struct cx18; 29 30 enum cx18_av_video_input { 31 /* Composite video inputs In1-In8 */ 32 CX18_AV_COMPOSITE1 = 1, 33 CX18_AV_COMPOSITE2, 34 CX18_AV_COMPOSITE3, 35 CX18_AV_COMPOSITE4, 36 CX18_AV_COMPOSITE5, 37 CX18_AV_COMPOSITE6, 38 CX18_AV_COMPOSITE7, 39 CX18_AV_COMPOSITE8, 40 41 /* S-Video inputs consist of one luma input (In1-In8) ORed with one 42 chroma input (In5-In8) */ 43 CX18_AV_SVIDEO_LUMA1 = 0x10, 44 CX18_AV_SVIDEO_LUMA2 = 0x20, 45 CX18_AV_SVIDEO_LUMA3 = 0x30, 46 CX18_AV_SVIDEO_LUMA4 = 0x40, 47 CX18_AV_SVIDEO_LUMA5 = 0x50, 48 CX18_AV_SVIDEO_LUMA6 = 0x60, 49 CX18_AV_SVIDEO_LUMA7 = 0x70, 50 CX18_AV_SVIDEO_LUMA8 = 0x80, 51 CX18_AV_SVIDEO_CHROMA4 = 0x400, 52 CX18_AV_SVIDEO_CHROMA5 = 0x500, 53 CX18_AV_SVIDEO_CHROMA6 = 0x600, 54 CX18_AV_SVIDEO_CHROMA7 = 0x700, 55 CX18_AV_SVIDEO_CHROMA8 = 0x800, 56 57 /* S-Video aliases for common luma/chroma combinations */ 58 CX18_AV_SVIDEO1 = 0x510, 59 CX18_AV_SVIDEO2 = 0x620, 60 CX18_AV_SVIDEO3 = 0x730, 61 CX18_AV_SVIDEO4 = 0x840, 62 }; 63 64 enum cx18_av_audio_input { 65 /* Audio inputs: serial or In4-In8 */ 66 CX18_AV_AUDIO_SERIAL1, 67 CX18_AV_AUDIO_SERIAL2, 68 CX18_AV_AUDIO4 = 4, 69 CX18_AV_AUDIO5, 70 CX18_AV_AUDIO6, 71 CX18_AV_AUDIO7, 72 CX18_AV_AUDIO8, 73 }; 74 75 struct cx18_av_state { 76 int radio; 77 v4l2_std_id std; 78 enum cx18_av_video_input vid_input; 79 enum cx18_av_audio_input aud_input; 80 u32 audclk_freq; 81 int audmode; 82 int vbi_line_offset; 83 int default_volume; 84 u32 id; 85 u32 rev; 86 int is_initialized; 87 }; 88 89 90 /* Registers */ 91 #define CXADEC_CHIP_TYPE_TIGER 0x837 92 #define CXADEC_CHIP_TYPE_MAKO 0x843 93 94 #define CXADEC_HOST_REG1 0x000 95 #define CXADEC_HOST_REG2 0x001 96 97 #define CXADEC_CHIP_CTRL 0x100 98 #define CXADEC_AFE_CTRL 0x104 99 #define CXADEC_PLL_CTRL1 0x108 100 #define CXADEC_VID_PLL_FRAC 0x10C 101 #define CXADEC_AUX_PLL_FRAC 0x110 102 #define CXADEC_PIN_CTRL1 0x114 103 #define CXADEC_PIN_CTRL2 0x118 104 #define CXADEC_PIN_CFG1 0x11C 105 #define CXADEC_PIN_CFG2 0x120 106 107 #define CXADEC_PIN_CFG3 0x124 108 #define CXADEC_I2S_MCLK 0x127 109 110 #define CXADEC_AUD_LOCK1 0x128 111 #define CXADEC_AUD_LOCK2 0x12C 112 #define CXADEC_POWER_CTRL 0x130 113 #define CXADEC_AFE_DIAG_CTRL1 0x134 114 #define CXADEC_AFE_DIAG_CTRL2 0x138 115 #define CXADEC_AFE_DIAG_CTRL3 0x13C 116 #define CXADEC_PLL_DIAG_CTRL 0x140 117 #define CXADEC_TEST_CTRL1 0x144 118 #define CXADEC_TEST_CTRL2 0x148 119 #define CXADEC_BIST_STAT 0x14C 120 #define CXADEC_DLL1_DIAG_CTRL 0x158 121 #define CXADEC_DLL2_DIAG_CTRL 0x15C 122 123 /* IR registers */ 124 #define CXADEC_IR_CTRL_REG 0x200 125 #define CXADEC_IR_TXCLK_REG 0x204 126 #define CXADEC_IR_RXCLK_REG 0x208 127 #define CXADEC_IR_CDUTY_REG 0x20C 128 #define CXADEC_IR_STAT_REG 0x210 129 #define CXADEC_IR_IRQEN_REG 0x214 130 #define CXADEC_IR_FILTER_REG 0x218 131 #define CXADEC_IR_FIFO_REG 0x21C 132 133 /* Video Registers */ 134 #define CXADEC_MODE_CTRL 0x400 135 #define CXADEC_OUT_CTRL1 0x404 136 #define CXADEC_OUT_CTRL2 0x408 137 #define CXADEC_GEN_STAT 0x40C 138 #define CXADEC_INT_STAT_MASK 0x410 139 #define CXADEC_LUMA_CTRL 0x414 140 141 #define CXADEC_BRIGHTNESS_CTRL_BYTE 0x414 142 #define CXADEC_CONTRAST_CTRL_BYTE 0x415 143 #define CXADEC_LUMA_CTRL_BYTE_3 0x416 144 145 #define CXADEC_HSCALE_CTRL 0x418 146 #define CXADEC_VSCALE_CTRL 0x41C 147 148 #define CXADEC_CHROMA_CTRL 0x420 149 150 #define CXADEC_USAT_CTRL_BYTE 0x420 151 #define CXADEC_VSAT_CTRL_BYTE 0x421 152 #define CXADEC_HUE_CTRL_BYTE 0x422 153 154 #define CXADEC_VBI_LINE_CTRL1 0x424 155 #define CXADEC_VBI_LINE_CTRL2 0x428 156 #define CXADEC_VBI_LINE_CTRL3 0x42C 157 #define CXADEC_VBI_LINE_CTRL4 0x430 158 #define CXADEC_VBI_LINE_CTRL5 0x434 159 #define CXADEC_VBI_FC_CFG 0x438 160 #define CXADEC_VBI_MISC_CFG1 0x43C 161 #define CXADEC_VBI_MISC_CFG2 0x440 162 #define CXADEC_VBI_PAY1 0x444 163 #define CXADEC_VBI_PAY2 0x448 164 #define CXADEC_VBI_CUST1_CFG1 0x44C 165 #define CXADEC_VBI_CUST1_CFG2 0x450 166 #define CXADEC_VBI_CUST1_CFG3 0x454 167 #define CXADEC_VBI_CUST2_CFG1 0x458 168 #define CXADEC_VBI_CUST2_CFG2 0x45C 169 #define CXADEC_VBI_CUST2_CFG3 0x460 170 #define CXADEC_VBI_CUST3_CFG1 0x464 171 #define CXADEC_VBI_CUST3_CFG2 0x468 172 #define CXADEC_VBI_CUST3_CFG3 0x46C 173 #define CXADEC_HORIZ_TIM_CTRL 0x470 174 #define CXADEC_VERT_TIM_CTRL 0x474 175 #define CXADEC_SRC_COMB_CFG 0x478 176 #define CXADEC_CHROMA_VBIOFF_CFG 0x47C 177 #define CXADEC_FIELD_COUNT 0x480 178 #define CXADEC_MISC_TIM_CTRL 0x484 179 #define CXADEC_DFE_CTRL1 0x488 180 #define CXADEC_DFE_CTRL2 0x48C 181 #define CXADEC_DFE_CTRL3 0x490 182 #define CXADEC_PLL_CTRL2 0x494 183 #define CXADEC_HTL_CTRL 0x498 184 #define CXADEC_COMB_CTRL 0x49C 185 #define CXADEC_CRUSH_CTRL 0x4A0 186 #define CXADEC_SOFT_RST_CTRL 0x4A4 187 #define CXADEC_MV_DT_CTRL2 0x4A8 188 #define CXADEC_MV_DT_CTRL3 0x4AC 189 #define CXADEC_MISC_DIAG_CTRL 0x4B8 190 191 #define CXADEC_DL_CTL 0x800 192 #define CXADEC_DL_CTL_ADDRESS_LOW 0x800 /* Byte 1 in DL_CTL */ 193 #define CXADEC_DL_CTL_ADDRESS_HIGH 0x801 /* Byte 2 in DL_CTL */ 194 #define CXADEC_DL_CTL_DATA 0x802 /* Byte 3 in DL_CTL */ 195 #define CXADEC_DL_CTL_CONTROL 0x803 /* Byte 4 in DL_CTL */ 196 197 #define CXADEC_STD_DET_STATUS 0x804 198 199 #define CXADEC_STD_DET_CTL 0x808 200 #define CXADEC_STD_DET_CTL_AUD_CTL 0x808 /* Byte 1 in STD_DET_CTL */ 201 #define CXADEC_STD_DET_CTL_PREF_MODE 0x809 /* Byte 2 in STD_DET_CTL */ 202 203 #define CXADEC_DW8051_INT 0x80C 204 #define CXADEC_GENERAL_CTL 0x810 205 #define CXADEC_AAGC_CTL 0x814 206 #define CXADEC_IF_SRC_CTL 0x818 207 #define CXADEC_ANLOG_DEMOD_CTL 0x81C 208 #define CXADEC_ROT_FREQ_CTL 0x820 209 #define CXADEC_FM1_CTL 0x824 210 #define CXADEC_PDF_CTL 0x828 211 #define CXADEC_DFT1_CTL1 0x82C 212 #define CXADEC_DFT1_CTL2 0x830 213 #define CXADEC_DFT_STATUS 0x834 214 #define CXADEC_DFT2_CTL1 0x838 215 #define CXADEC_DFT2_CTL2 0x83C 216 #define CXADEC_DFT2_STATUS 0x840 217 #define CXADEC_DFT3_CTL1 0x844 218 #define CXADEC_DFT3_CTL2 0x848 219 #define CXADEC_DFT3_STATUS 0x84C 220 #define CXADEC_DFT4_CTL1 0x850 221 #define CXADEC_DFT4_CTL2 0x854 222 #define CXADEC_DFT4_STATUS 0x858 223 #define CXADEC_AM_MTS_DET 0x85C 224 #define CXADEC_ANALOG_MUX_CTL 0x860 225 #define CXADEC_DIG_PLL_CTL1 0x864 226 #define CXADEC_DIG_PLL_CTL2 0x868 227 #define CXADEC_DIG_PLL_CTL3 0x86C 228 #define CXADEC_DIG_PLL_CTL4 0x870 229 #define CXADEC_DIG_PLL_CTL5 0x874 230 #define CXADEC_DEEMPH_GAIN_CTL 0x878 231 #define CXADEC_DEEMPH_COEF1 0x87C 232 #define CXADEC_DEEMPH_COEF2 0x880 233 #define CXADEC_DBX1_CTL1 0x884 234 #define CXADEC_DBX1_CTL2 0x888 235 #define CXADEC_DBX1_STATUS 0x88C 236 #define CXADEC_DBX2_CTL1 0x890 237 #define CXADEC_DBX2_CTL2 0x894 238 #define CXADEC_DBX2_STATUS 0x898 239 #define CXADEC_AM_FM_DIFF 0x89C 240 241 /* NICAM registers go here */ 242 #define CXADEC_NICAM_STATUS 0x8C8 243 #define CXADEC_DEMATRIX_CTL 0x8CC 244 245 #define CXADEC_PATH1_CTL1 0x8D0 246 #define CXADEC_PATH1_VOL_CTL 0x8D4 247 #define CXADEC_PATH1_EQ_CTL 0x8D8 248 #define CXADEC_PATH1_SC_CTL 0x8DC 249 250 #define CXADEC_PATH2_CTL1 0x8E0 251 #define CXADEC_PATH2_VOL_CTL 0x8E4 252 #define CXADEC_PATH2_EQ_CTL 0x8E8 253 #define CXADEC_PATH2_SC_CTL 0x8EC 254 255 #define CXADEC_SRC_CTL 0x8F0 256 #define CXADEC_SRC_LF_COEF 0x8F4 257 #define CXADEC_SRC1_CTL 0x8F8 258 #define CXADEC_SRC2_CTL 0x8FC 259 #define CXADEC_SRC3_CTL 0x900 260 #define CXADEC_SRC4_CTL 0x904 261 #define CXADEC_SRC5_CTL 0x908 262 #define CXADEC_SRC6_CTL 0x90C 263 264 #define CXADEC_BASEBAND_OUT_SEL 0x910 265 #define CXADEC_I2S_IN_CTL 0x914 266 #define CXADEC_I2S_OUT_CTL 0x918 267 #define CXADEC_AC97_CTL 0x91C 268 #define CXADEC_QAM_PDF 0x920 269 #define CXADEC_QAM_CONST_DEC 0x924 270 #define CXADEC_QAM_ROTATOR_FREQ 0x948 271 272 /* Bit defintions / settings used in Mako Audio */ 273 #define CXADEC_PREF_MODE_MONO_LANGA 0 274 #define CXADEC_PREF_MODE_MONO_LANGB 1 275 #define CXADEC_PREF_MODE_MONO_LANGC 2 276 #define CXADEC_PREF_MODE_FALLBACK 3 277 #define CXADEC_PREF_MODE_STEREO 4 278 #define CXADEC_PREF_MODE_DUAL_LANG_AC 5 279 #define CXADEC_PREF_MODE_DUAL_LANG_BC 6 280 #define CXADEC_PREF_MODE_DUAL_LANG_AB 7 281 282 283 #define CXADEC_DETECT_STEREO 1 284 #define CXADEC_DETECT_DUAL 2 285 #define CXADEC_DETECT_TRI 4 286 #define CXADEC_DETECT_SAP 0x10 287 #define CXADEC_DETECT_NO_SIGNAL 0xFF 288 289 #define CXADEC_SELECT_AUDIO_STANDARD_BG 0xF0 /* NICAM BG and A2 BG */ 290 #define CXADEC_SELECT_AUDIO_STANDARD_DK1 0xF1 /* NICAM DK and A2 DK */ 291 #define CXADEC_SELECT_AUDIO_STANDARD_DK2 0xF2 292 #define CXADEC_SELECT_AUDIO_STANDARD_DK3 0xF3 293 #define CXADEC_SELECT_AUDIO_STANDARD_I 0xF4 /* NICAM I and A1 */ 294 #define CXADEC_SELECT_AUDIO_STANDARD_L 0xF5 /* NICAM L and System L AM */ 295 #define CXADEC_SELECT_AUDIO_STANDARD_BTSC 0xF6 296 #define CXADEC_SELECT_AUDIO_STANDARD_EIAJ 0xF7 297 #define CXADEC_SELECT_AUDIO_STANDARD_A2_M 0xF8 /* A2 M */ 298 #define CXADEC_SELECT_AUDIO_STANDARD_FM 0xF9 /* FM radio */ 299 #define CXADEC_SELECT_AUDIO_STANDARD_AUTO 0xFF /* Auto detect */ 300 301 /* ----------------------------------------------------------------------- */ 302 /* cx18_av-core.c */ 303 int cx18_av_write(struct cx18 *cx, u16 addr, u8 value); 304 int cx18_av_write4(struct cx18 *cx, u16 addr, u32 value); 305 int cx18_av_write4_noretry(struct cx18 *cx, u16 addr, u32 value); 306 int cx18_av_write_expect(struct cx18 *cx, u16 addr, u8 value, u8 eval, u8 mask); 307 int cx18_av_write4_expect(struct cx18 *cx, u16 addr, u32 value, u32 eval, 308 u32 mask); 309 u8 cx18_av_read(struct cx18 *cx, u16 addr); 310 u32 cx18_av_read4(struct cx18 *cx, u16 addr); 311 int cx18_av_and_or(struct cx18 *cx, u16 addr, unsigned mask, u8 value); 312 int cx18_av_and_or4(struct cx18 *cx, u16 addr, u32 mask, u32 value); 313 int cx18_av_cmd(struct cx18 *cx, unsigned int cmd, void *arg); 314 void cx18_av_std_setup(struct cx18 *cx); 315 316 /* ----------------------------------------------------------------------- */ 317 /* cx18_av-firmware.c */ 318 int cx18_av_loadfw(struct cx18 *cx); 319 320 /* ----------------------------------------------------------------------- */ 321 /* cx18_av-audio.c */ 322 int cx18_av_audio(struct cx18 *cx, unsigned int cmd, void *arg); 323 void cx18_av_audio_set_path(struct cx18 *cx); 324 325 /* ----------------------------------------------------------------------- */ 326 /* cx18_av-vbi.c */ 327 int cx18_av_vbi(struct cx18 *cx, unsigned int cmd, void *arg); 328 329 #endif 330