1 /* 2 * Tehuti Networks(R) Network Driver 3 * Copyright (C) 2007 Tehuti Networks Ltd. All rights reserved 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 */ 10 11 #ifndef _TEHUTI_H 12 #define _TEHUTI_H 13 14 #include <linux/module.h> 15 #include <linux/kernel.h> 16 #include <linux/netdevice.h> 17 #include <linux/etherdevice.h> 18 #include <linux/pci.h> 19 #include <linux/delay.h> 20 #include <linux/ethtool.h> 21 #include <linux/mii.h> 22 #include <linux/crc32.h> 23 #include <linux/uaccess.h> 24 #include <linux/in.h> 25 #include <linux/ip.h> 26 #include <linux/tcp.h> 27 #include <linux/sched.h> 28 #include <linux/tty.h> 29 #include <linux/if_vlan.h> 30 #include <linux/interrupt.h> 31 #include <linux/vmalloc.h> 32 #include <asm/byteorder.h> 33 34 /* Compile Time Switches */ 35 /* start */ 36 #define BDX_TSO 37 #define BDX_LLTX 38 #define BDX_DELAY_WPTR 39 /* #define BDX_MSI */ 40 /* end */ 41 42 #if !defined CONFIG_PCI_MSI 43 # undef BDX_MSI 44 #endif 45 46 #define BDX_DEF_MSG_ENABLE (NETIF_MSG_DRV | \ 47 NETIF_MSG_PROBE | \ 48 NETIF_MSG_LINK) 49 50 /* ioctl ops */ 51 #define BDX_OP_READ 1 52 #define BDX_OP_WRITE 2 53 54 /* RX copy break size */ 55 #define BDX_COPYBREAK 257 56 57 #define DRIVER_AUTHOR "Tehuti Networks(R)" 58 #define BDX_DRV_DESC "Tehuti Networks(R) Network Driver" 59 #define BDX_DRV_NAME "tehuti" 60 #define BDX_NIC_NAME "Tehuti 10 Giga TOE SmartNIC" 61 #define BDX_NIC2PORT_NAME "Tehuti 2-Port 10 Giga TOE SmartNIC" 62 #define BDX_DRV_VERSION "7.29.3" 63 64 #ifdef BDX_MSI 65 # define BDX_MSI_STRING "msi " 66 #else 67 # define BDX_MSI_STRING "" 68 #endif 69 70 /* netdev tx queue len for Luxor. default value is, btw, 1000 71 * ifcontig eth1 txqueuelen 3000 - to change it at runtime */ 72 #define BDX_NDEV_TXQ_LEN 3000 73 74 #define FIFO_SIZE 4096 75 #define FIFO_EXTRA_SPACE 1024 76 77 #define MIN(x, y) ((x) < (y) ? (x) : (y)) 78 79 #if BITS_PER_LONG == 64 80 # define H32_64(x) (u32) ((u64)(x) >> 32) 81 # define L32_64(x) (u32) ((u64)(x) & 0xffffffff) 82 #elif BITS_PER_LONG == 32 83 # define H32_64(x) 0 84 # define L32_64(x) ((u32) (x)) 85 #else /* BITS_PER_LONG == ?? */ 86 # error BITS_PER_LONG is undefined. Must be 64 or 32 87 #endif /* BITS_PER_LONG */ 88 89 #ifdef __BIG_ENDIAN 90 # define CPU_CHIP_SWAP32(x) swab32(x) 91 # define CPU_CHIP_SWAP16(x) swab16(x) 92 #else 93 # define CPU_CHIP_SWAP32(x) (x) 94 # define CPU_CHIP_SWAP16(x) (x) 95 #endif 96 97 #define READ_REG(pp, reg) readl(pp->pBdxRegs + reg) 98 #define WRITE_REG(pp, reg, val) writel(val, pp->pBdxRegs + reg) 99 100 #ifndef DMA_64BIT_MASK 101 # define DMA_64BIT_MASK 0xffffffffffffffffULL 102 #endif 103 104 #ifndef DMA_32BIT_MASK 105 # define DMA_32BIT_MASK 0x00000000ffffffffULL 106 #endif 107 108 #ifndef NET_IP_ALIGN 109 # define NET_IP_ALIGN 2 110 #endif 111 112 #ifndef NETDEV_TX_OK 113 # define NETDEV_TX_OK 0 114 #endif 115 116 #define LUXOR_MAX_PORT 2 117 #define BDX_MAX_RX_DONE 150 118 #define BDX_TXF_DESC_SZ 16 119 #define BDX_MAX_TX_LEVEL (priv->txd_fifo0.m.memsz - 16) 120 #define BDX_MIN_TX_LEVEL 256 121 #define BDX_NO_UPD_PACKETS 40 122 123 struct pci_nic { 124 int port_num; 125 void __iomem *regs; 126 int irq_type; 127 struct bdx_priv *priv[LUXOR_MAX_PORT]; 128 }; 129 130 enum { IRQ_INTX, IRQ_MSI, IRQ_MSIX }; 131 132 #define PCK_TH_MULT 128 133 #define INT_COAL_MULT 2 134 135 #define BITS_MASK(nbits) ((1<<nbits)-1) 136 #define GET_BITS_SHIFT(x, nbits, nshift) (((x)>>nshift)&BITS_MASK(nbits)) 137 #define BITS_SHIFT_MASK(nbits, nshift) (BITS_MASK(nbits)<<nshift) 138 #define BITS_SHIFT_VAL(x, nbits, nshift) (((x)&BITS_MASK(nbits))<<nshift) 139 #define BITS_SHIFT_CLEAR(x, nbits, nshift) \ 140 ((x)&(~BITS_SHIFT_MASK(nbits, nshift))) 141 142 #define GET_INT_COAL(x) GET_BITS_SHIFT(x, 15, 0) 143 #define GET_INT_COAL_RC(x) GET_BITS_SHIFT(x, 1, 15) 144 #define GET_RXF_TH(x) GET_BITS_SHIFT(x, 4, 16) 145 #define GET_PCK_TH(x) GET_BITS_SHIFT(x, 4, 20) 146 147 #define INT_REG_VAL(coal, coal_rc, rxf_th, pck_th) \ 148 ((coal)|((coal_rc)<<15)|((rxf_th)<<16)|((pck_th)<<20)) 149 150 struct fifo { 151 dma_addr_t da; /* physical address of fifo (used by HW) */ 152 char *va; /* virtual address of fifo (used by SW) */ 153 u32 rptr, wptr; /* cached values of RPTR and WPTR registers, 154 they're 32 bits on both 32 and 64 archs */ 155 u16 reg_CFG0, reg_CFG1; 156 u16 reg_RPTR, reg_WPTR; 157 u16 memsz; /* memory size allocated for fifo */ 158 u16 size_mask; 159 u16 pktsz; /* skb packet size to allocate */ 160 u16 rcvno; /* number of buffers that come from this RXF */ 161 }; 162 163 struct txf_fifo { 164 struct fifo m; /* minimal set of variables used by all fifos */ 165 }; 166 167 struct txd_fifo { 168 struct fifo m; /* minimal set of variables used by all fifos */ 169 }; 170 171 struct rxf_fifo { 172 struct fifo m; /* minimal set of variables used by all fifos */ 173 }; 174 175 struct rxd_fifo { 176 struct fifo m; /* minimal set of variables used by all fifos */ 177 }; 178 179 struct rx_map { 180 u64 dma; 181 struct sk_buff *skb; 182 }; 183 184 struct rxdb { 185 int *stack; 186 struct rx_map *elems; 187 int nelem; 188 int top; 189 }; 190 191 union bdx_dma_addr { 192 dma_addr_t dma; 193 struct sk_buff *skb; 194 }; 195 196 /* Entry in the db. 197 * if len == 0 addr is dma 198 * if len != 0 addr is skb */ 199 struct tx_map { 200 union bdx_dma_addr addr; 201 int len; 202 }; 203 204 /* tx database - implemented as circular fifo buffer*/ 205 struct txdb { 206 struct tx_map *start; /* points to the first element */ 207 struct tx_map *end; /* points just AFTER the last element */ 208 struct tx_map *rptr; /* points to the next element to read */ 209 struct tx_map *wptr; /* points to the next element to write */ 210 int size; /* number of elements in the db */ 211 }; 212 213 /*Internal stats structure*/ 214 struct bdx_stats { 215 u64 InUCast; /* 0x7200 */ 216 u64 InMCast; /* 0x7210 */ 217 u64 InBCast; /* 0x7220 */ 218 u64 InPkts; /* 0x7230 */ 219 u64 InErrors; /* 0x7240 */ 220 u64 InDropped; /* 0x7250 */ 221 u64 FrameTooLong; /* 0x7260 */ 222 u64 FrameSequenceErrors; /* 0x7270 */ 223 u64 InVLAN; /* 0x7280 */ 224 u64 InDroppedDFE; /* 0x7290 */ 225 u64 InDroppedIntFull; /* 0x72A0 */ 226 u64 InFrameAlignErrors; /* 0x72B0 */ 227 228 /* 0x72C0-0x72E0 RSRV */ 229 230 u64 OutUCast; /* 0x72F0 */ 231 u64 OutMCast; /* 0x7300 */ 232 u64 OutBCast; /* 0x7310 */ 233 u64 OutPkts; /* 0x7320 */ 234 235 /* 0x7330-0x7360 RSRV */ 236 237 u64 OutVLAN; /* 0x7370 */ 238 u64 InUCastOctects; /* 0x7380 */ 239 u64 OutUCastOctects; /* 0x7390 */ 240 241 /* 0x73A0-0x73B0 RSRV */ 242 243 u64 InBCastOctects; /* 0x73C0 */ 244 u64 OutBCastOctects; /* 0x73D0 */ 245 u64 InOctects; /* 0x73E0 */ 246 u64 OutOctects; /* 0x73F0 */ 247 }; 248 249 struct bdx_priv { 250 void __iomem *pBdxRegs; 251 struct net_device *ndev; 252 253 struct napi_struct napi; 254 255 /* RX FIFOs: 1 for data (full) descs, and 2 for free descs */ 256 struct rxd_fifo rxd_fifo0; 257 struct rxf_fifo rxf_fifo0; 258 struct rxdb *rxdb; /* rx dbs to store skb pointers */ 259 int napi_stop; 260 struct vlan_group *vlgrp; 261 262 /* Tx FIFOs: 1 for data desc, 1 for empty (acks) desc */ 263 struct txd_fifo txd_fifo0; 264 struct txf_fifo txf_fifo0; 265 266 struct txdb txdb; 267 int tx_level; 268 #ifdef BDX_DELAY_WPTR 269 int tx_update_mark; 270 int tx_noupd; 271 #endif 272 spinlock_t tx_lock; /* NETIF_F_LLTX mode */ 273 274 /* rarely used */ 275 u8 port; 276 u32 msg_enable; 277 int stats_flag; 278 struct bdx_stats hw_stats; 279 struct net_device_stats net_stats; 280 struct pci_dev *pdev; 281 282 struct pci_nic *nic; 283 284 u8 txd_size; 285 u8 txf_size; 286 u8 rxd_size; 287 u8 rxf_size; 288 u32 rdintcm; 289 u32 tdintcm; 290 }; 291 292 /* RX FREE descriptor - 64bit*/ 293 struct rxf_desc { 294 u32 info; /* Buffer Count + Info - described below */ 295 u32 va_lo; /* VAdr[31:0] */ 296 u32 va_hi; /* VAdr[63:32] */ 297 u32 pa_lo; /* PAdr[31:0] */ 298 u32 pa_hi; /* PAdr[63:32] */ 299 u32 len; /* Buffer Length */ 300 }; 301 302 #define GET_RXD_BC(x) GET_BITS_SHIFT((x), 5, 0) 303 #define GET_RXD_RXFQ(x) GET_BITS_SHIFT((x), 2, 8) 304 #define GET_RXD_TO(x) GET_BITS_SHIFT((x), 1, 15) 305 #define GET_RXD_TYPE(x) GET_BITS_SHIFT((x), 4, 16) 306 #define GET_RXD_ERR(x) GET_BITS_SHIFT((x), 6, 21) 307 #define GET_RXD_RXP(x) GET_BITS_SHIFT((x), 1, 27) 308 #define GET_RXD_PKT_ID(x) GET_BITS_SHIFT((x), 3, 28) 309 #define GET_RXD_VTAG(x) GET_BITS_SHIFT((x), 1, 31) 310 #define GET_RXD_VLAN_ID(x) GET_BITS_SHIFT((x), 12, 0) 311 #define GET_RXD_VLAN_TCI(x) GET_BITS_SHIFT((x), 16, 0) 312 #define GET_RXD_CFI(x) GET_BITS_SHIFT((x), 1, 12) 313 #define GET_RXD_PRIO(x) GET_BITS_SHIFT((x), 3, 13) 314 315 struct rxd_desc { 316 u32 rxd_val1; 317 u16 len; 318 u16 rxd_vlan; 319 u32 va_lo; 320 u32 va_hi; 321 }; 322 323 /* PBL describes each virtual buffer to be */ 324 /* transmitted from the host.*/ 325 struct pbl { 326 u32 pa_lo; 327 u32 pa_hi; 328 u32 len; 329 }; 330 331 /* First word for TXD descriptor. It means: type = 3 for regular Tx packet, 332 * hw_csum = 7 for ip+udp+tcp hw checksums */ 333 #define TXD_W1_VAL(bc, checksum, vtag, lgsnd, vlan_id) \ 334 ((bc) | ((checksum)<<5) | ((vtag)<<8) | \ 335 ((lgsnd)<<9) | (0x30000) | ((vlan_id)<<20)) 336 337 struct txd_desc { 338 u32 txd_val1; 339 u16 mss; 340 u16 length; 341 u32 va_lo; 342 u32 va_hi; 343 struct pbl pbl[0]; /* Fragments */ 344 } __attribute__ ((packed)); 345 346 /* Register region size */ 347 #define BDX_REGS_SIZE 0x1000 348 349 /* Registers from 0x0000-0x00fc were remapped to 0x4000-0x40fc */ 350 #define regTXD_CFG1_0 0x4000 351 #define regRXF_CFG1_0 0x4010 352 #define regRXD_CFG1_0 0x4020 353 #define regTXF_CFG1_0 0x4030 354 #define regTXD_CFG0_0 0x4040 355 #define regRXF_CFG0_0 0x4050 356 #define regRXD_CFG0_0 0x4060 357 #define regTXF_CFG0_0 0x4070 358 #define regTXD_WPTR_0 0x4080 359 #define regRXF_WPTR_0 0x4090 360 #define regRXD_WPTR_0 0x40A0 361 #define regTXF_WPTR_0 0x40B0 362 #define regTXD_RPTR_0 0x40C0 363 #define regRXF_RPTR_0 0x40D0 364 #define regRXD_RPTR_0 0x40E0 365 #define regTXF_RPTR_0 0x40F0 366 #define regTXF_RPTR_3 0x40FC 367 368 /* hardware versioning */ 369 #define FW_VER 0x5010 370 #define SROM_VER 0x5020 371 #define FPGA_VER 0x5030 372 #define FPGA_SEED 0x5040 373 374 /* Registers from 0x0100-0x0150 were remapped to 0x5100-0x5150 */ 375 #define regISR regISR0 376 #define regISR0 0x5100 377 378 #define regIMR regIMR0 379 #define regIMR0 0x5110 380 381 #define regRDINTCM0 0x5120 382 #define regRDINTCM2 0x5128 383 384 #define regTDINTCM0 0x5130 385 386 #define regISR_MSK0 0x5140 387 388 #define regINIT_SEMAPHORE 0x5170 389 #define regINIT_STATUS 0x5180 390 391 #define regMAC_LNK_STAT 0x0200 392 #define MAC_LINK_STAT 0x4 /* Link state */ 393 394 #define regGMAC_RXF_A 0x1240 395 396 #define regUNC_MAC0_A 0x1250 397 #define regUNC_MAC1_A 0x1260 398 #define regUNC_MAC2_A 0x1270 399 400 #define regVLAN_0 0x1800 401 402 #define regMAX_FRAME_A 0x12C0 403 404 #define regRX_MAC_MCST0 0x1A80 405 #define regRX_MAC_MCST1 0x1A84 406 #define MAC_MCST_NUM 15 407 #define regRX_MCST_HASH0 0x1A00 408 #define MAC_MCST_HASH_NUM 8 409 410 #define regVPC 0x2300 411 #define regVIC 0x2320 412 #define regVGLB 0x2340 413 414 #define regCLKPLL 0x5000 415 416 /*for 10G only*/ 417 #define regREVISION 0x6000 418 #define regSCRATCH 0x6004 419 #define regCTRLST 0x6008 420 #define regMAC_ADDR_0 0x600C 421 #define regMAC_ADDR_1 0x6010 422 #define regFRM_LENGTH 0x6014 423 #define regPAUSE_QUANT 0x6018 424 #define regRX_FIFO_SECTION 0x601C 425 #define regTX_FIFO_SECTION 0x6020 426 #define regRX_FULLNESS 0x6024 427 #define regTX_FULLNESS 0x6028 428 #define regHASHTABLE 0x602C 429 #define regMDIO_ST 0x6030 430 #define regMDIO_CTL 0x6034 431 #define regMDIO_DATA 0x6038 432 #define regMDIO_ADDR 0x603C 433 434 #define regRST_PORT 0x7000 435 #define regDIS_PORT 0x7010 436 #define regRST_QU 0x7020 437 #define regDIS_QU 0x7030 438 439 #define regCTRLST_TX_ENA 0x0001 440 #define regCTRLST_RX_ENA 0x0002 441 #define regCTRLST_PRM_ENA 0x0010 442 #define regCTRLST_PAD_ENA 0x0020 443 444 #define regCTRLST_BASE (regCTRLST_PAD_ENA|regCTRLST_PRM_ENA) 445 446 #define regRX_FLT 0x1400 447 448 /* TXD TXF RXF RXD CONFIG 0x0000 --- 0x007c*/ 449 #define TX_RX_CFG1_BASE 0xffffffff /*0-31 */ 450 #define TX_RX_CFG0_BASE 0xfffff000 /*31:12 */ 451 #define TX_RX_CFG0_RSVD 0x0ffc /*11:2 */ 452 #define TX_RX_CFG0_SIZE 0x0003 /*1:0 */ 453 454 /* TXD TXF RXF RXD WRITE 0x0080 --- 0x00BC */ 455 #define TXF_WPTR_WR_PTR 0x7ff8 /*14:3 */ 456 457 /* TXD TXF RXF RXD READ 0x00CO --- 0x00FC */ 458 #define TXF_RPTR_RD_PTR 0x7ff8 /*14:3 */ 459 460 #define TXF_WPTR_MASK 0x7ff0 /* last 4 bits are dropped 461 * size is rounded to 16 */ 462 463 /* regISR 0x0100 */ 464 /* regIMR 0x0110 */ 465 #define IMR_INPROG 0x80000000 /*31 */ 466 #define IR_LNKCHG1 0x10000000 /*28 */ 467 #define IR_LNKCHG0 0x08000000 /*27 */ 468 #define IR_GPIO 0x04000000 /*26 */ 469 #define IR_RFRSH 0x02000000 /*25 */ 470 #define IR_RSVD 0x01000000 /*24 */ 471 #define IR_SWI 0x00800000 /*23 */ 472 #define IR_RX_FREE_3 0x00400000 /*22 */ 473 #define IR_RX_FREE_2 0x00200000 /*21 */ 474 #define IR_RX_FREE_1 0x00100000 /*20 */ 475 #define IR_RX_FREE_0 0x00080000 /*19 */ 476 #define IR_TX_FREE_3 0x00040000 /*18 */ 477 #define IR_TX_FREE_2 0x00020000 /*17 */ 478 #define IR_TX_FREE_1 0x00010000 /*16 */ 479 #define IR_TX_FREE_0 0x00008000 /*15 */ 480 #define IR_RX_DESC_3 0x00004000 /*14 */ 481 #define IR_RX_DESC_2 0x00002000 /*13 */ 482 #define IR_RX_DESC_1 0x00001000 /*12 */ 483 #define IR_RX_DESC_0 0x00000800 /*11 */ 484 #define IR_PSE 0x00000400 /*10 */ 485 #define IR_TMR3 0x00000200 /*9 */ 486 #define IR_TMR2 0x00000100 /*8 */ 487 #define IR_TMR1 0x00000080 /*7 */ 488 #define IR_TMR0 0x00000040 /*6 */ 489 #define IR_VNT 0x00000020 /*5 */ 490 #define IR_RxFL 0x00000010 /*4 */ 491 #define IR_SDPERR 0x00000008 /*3 */ 492 #define IR_TR 0x00000004 /*2 */ 493 #define IR_PCIE_LINK 0x00000002 /*1 */ 494 #define IR_PCIE_TOUT 0x00000001 /*0 */ 495 496 #define IR_EXTRA (IR_RX_FREE_0 | IR_LNKCHG0 | IR_PSE | \ 497 IR_TMR0 | IR_PCIE_LINK | IR_PCIE_TOUT) 498 #define IR_RUN (IR_EXTRA | IR_RX_DESC_0 | IR_TX_FREE_0) 499 #define IR_ALL 0xfdfffff7 500 501 #define IR_LNKCHG0_ofst 27 502 503 #define GMAC_RX_FILTER_OSEN 0x1000 /* shared OS enable */ 504 #define GMAC_RX_FILTER_TXFC 0x0400 /* Tx flow control */ 505 #define GMAC_RX_FILTER_RSV0 0x0200 /* reserved */ 506 #define GMAC_RX_FILTER_FDA 0x0100 /* filter out direct address */ 507 #define GMAC_RX_FILTER_AOF 0x0080 /* accept over run */ 508 #define GMAC_RX_FILTER_ACF 0x0040 /* accept control frames */ 509 #define GMAC_RX_FILTER_ARUNT 0x0020 /* accept under run */ 510 #define GMAC_RX_FILTER_ACRC 0x0010 /* accept crc error */ 511 #define GMAC_RX_FILTER_AM 0x0008 /* accept multicast */ 512 #define GMAC_RX_FILTER_AB 0x0004 /* accept broadcast */ 513 #define GMAC_RX_FILTER_PRM 0x0001 /* [0:1] promiscous mode */ 514 515 #define MAX_FRAME_AB_VAL 0x3fff /* 13:0 */ 516 517 #define CLKPLL_PLLLKD 0x0200 /*9 */ 518 #define CLKPLL_RSTEND 0x0100 /*8 */ 519 #define CLKPLL_SFTRST 0x0001 /*0 */ 520 521 #define CLKPLL_LKD (CLKPLL_PLLLKD|CLKPLL_RSTEND) 522 523 /* 524 * PCI-E Device Control Register (Offset 0x88) 525 * Source: Luxor Data Sheet, 7.1.3.3.3 526 */ 527 #define PCI_DEV_CTRL_REG 0x88 528 #define GET_DEV_CTRL_MAXPL(x) GET_BITS_SHIFT(x, 3, 5) 529 #define GET_DEV_CTRL_MRRS(x) GET_BITS_SHIFT(x, 3, 12) 530 531 /* 532 * PCI-E Link Status Register (Offset 0x92) 533 * Source: Luxor Data Sheet, 7.1.3.3.7 534 */ 535 #define PCI_LINK_STATUS_REG 0x92 536 #define GET_LINK_STATUS_LANES(x) GET_BITS_SHIFT(x, 6, 4) 537 538 /* Debugging Macros */ 539 540 #define ERR(fmt, args...) printk(KERN_ERR fmt, ## args) 541 #define DBG2(fmt, args...) \ 542 printk(KERN_ERR "%s:%-5d: " fmt, __func__, __LINE__, ## args) 543 544 #define BDX_ASSERT(x) BUG_ON(x) 545 546 #ifdef DEBUG 547 548 #define ENTER do { \ 549 printk(KERN_ERR "%s:%-5d: ENTER\n", __func__, __LINE__); \ 550 } while (0) 551 552 #define RET(args...) do { \ 553 printk(KERN_ERR "%s:%-5d: RETURN\n", __func__, __LINE__); \ 554 return args; } while (0) 555 556 #define DBG(fmt, args...) \ 557 printk(KERN_ERR "%s:%-5d: " fmt, __func__, __LINE__, ## args) 558 #else 559 #define ENTER do { } while (0) 560 #define RET(args...) return args 561 #define DBG(fmt, args...) do { } while (0) 562 #endif 563 564 #endif /* _BDX__H */ 565