1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2005-2008 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11 /* Common definitions for all Efx net driver code */
12
13 #ifndef EFX_NET_DRIVER_H
14 #define EFX_NET_DRIVER_H
15
16 #include <linux/version.h>
17 #include <linux/netdevice.h>
18 #include <linux/etherdevice.h>
19 #include <linux/ethtool.h>
20 #include <linux/if_vlan.h>
21 #include <linux/timer.h>
22 #include <linux/mii.h>
23 #include <linux/list.h>
24 #include <linux/pci.h>
25 #include <linux/device.h>
26 #include <linux/highmem.h>
27 #include <linux/workqueue.h>
28 #include <linux/inet_lro.h>
29 #include <linux/i2c.h>
30
31 #include "enum.h"
32 #include "bitfield.h"
33
34 #define EFX_MAX_LRO_DESCRIPTORS 8
35 #define EFX_MAX_LRO_AGGR MAX_SKB_FRAGS
36
37 /**************************************************************************
38 *
39 * Build definitions
40 *
41 **************************************************************************/
42 #ifndef EFX_DRIVER_NAME
43 #define EFX_DRIVER_NAME "sfc"
44 #endif
45 #define EFX_DRIVER_VERSION "2.3"
46
47 #ifdef EFX_ENABLE_DEBUG
48 #define EFX_BUG_ON_PARANOID(x) BUG_ON(x)
49 #define EFX_WARN_ON_PARANOID(x) WARN_ON(x)
50 #else
51 #define EFX_BUG_ON_PARANOID(x) do {} while (0)
52 #define EFX_WARN_ON_PARANOID(x) do {} while (0)
53 #endif
54
55 /* Un-rate-limited logging */
56 #define EFX_ERR(efx, fmt, args...) \
57 dev_err(&((efx)->pci_dev->dev), "ERR: %s " fmt, efx_dev_name(efx), ##args)
58
59 #define EFX_INFO(efx, fmt, args...) \
60 dev_info(&((efx)->pci_dev->dev), "INFO: %s " fmt, efx_dev_name(efx), ##args)
61
62 #ifdef EFX_ENABLE_DEBUG
63 #define EFX_LOG(efx, fmt, args...) \
64 dev_info(&((efx)->pci_dev->dev), "DBG: %s " fmt, efx_dev_name(efx), ##args)
65 #else
66 #define EFX_LOG(efx, fmt, args...) \
67 dev_dbg(&((efx)->pci_dev->dev), "DBG: %s " fmt, efx_dev_name(efx), ##args)
68 #endif
69
70 #define EFX_TRACE(efx, fmt, args...) do {} while (0)
71
72 #define EFX_REGDUMP(efx, fmt, args...) do {} while (0)
73
74 /* Rate-limited logging */
75 #define EFX_ERR_RL(efx, fmt, args...) \
76 do {if (net_ratelimit()) EFX_ERR(efx, fmt, ##args); } while (0)
77
78 #define EFX_INFO_RL(efx, fmt, args...) \
79 do {if (net_ratelimit()) EFX_INFO(efx, fmt, ##args); } while (0)
80
81 #define EFX_LOG_RL(efx, fmt, args...) \
82 do {if (net_ratelimit()) EFX_LOG(efx, fmt, ##args); } while (0)
83
84 /**************************************************************************
85 *
86 * Efx data structures
87 *
88 **************************************************************************/
89
90 #define EFX_MAX_CHANNELS 32
91 #define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS
92
93 #define EFX_TX_QUEUE_OFFLOAD_CSUM 0
94 #define EFX_TX_QUEUE_NO_CSUM 1
95 #define EFX_TX_QUEUE_COUNT 2
96
97 /**
98 * struct efx_special_buffer - An Efx special buffer
99 * @addr: CPU base address of the buffer
100 * @dma_addr: DMA base address of the buffer
101 * @len: Buffer length, in bytes
102 * @index: Buffer index within controller;s buffer table
103 * @entries: Number of buffer table entries
104 *
105 * Special buffers are used for the event queues and the TX and RX
106 * descriptor queues for each channel. They are *not* used for the
107 * actual transmit and receive buffers.
108 *
109 * Note that for Falcon, TX and RX descriptor queues live in host memory.
110 * Allocation and freeing procedures must take this into account.
111 */
112 struct efx_special_buffer {
113 void *addr;
114 dma_addr_t dma_addr;
115 unsigned int len;
116 int index;
117 int entries;
118 };
119
120 /**
121 * struct efx_tx_buffer - An Efx TX buffer
122 * @skb: The associated socket buffer.
123 * Set only on the final fragment of a packet; %NULL for all other
124 * fragments. When this fragment completes, then we can free this
125 * skb.
126 * @tsoh: The associated TSO header structure, or %NULL if this
127 * buffer is not a TSO header.
128 * @dma_addr: DMA address of the fragment.
129 * @len: Length of this fragment.
130 * This field is zero when the queue slot is empty.
131 * @continuation: True if this fragment is not the end of a packet.
132 * @unmap_single: True if pci_unmap_single should be used.
133 * @unmap_len: Length of this fragment to unmap
134 */
135 struct efx_tx_buffer {
136 const struct sk_buff *skb;
137 struct efx_tso_header *tsoh;
138 dma_addr_t dma_addr;
139 unsigned short len;
140 bool continuation;
141 bool unmap_single;
142 unsigned short unmap_len;
143 };
144
145 /**
146 * struct efx_tx_queue - An Efx TX queue
147 *
148 * This is a ring buffer of TX fragments.
149 * Since the TX completion path always executes on the same
150 * CPU and the xmit path can operate on different CPUs,
151 * performance is increased by ensuring that the completion
152 * path and the xmit path operate on different cache lines.
153 * This is particularly important if the xmit path is always
154 * executing on one CPU which is different from the completion
155 * path. There is also a cache line for members which are
156 * read but not written on the fast path.
157 *
158 * @efx: The associated Efx NIC
159 * @queue: DMA queue number
160 * @channel: The associated channel
161 * @buffer: The software buffer ring
162 * @txd: The hardware descriptor ring
163 * @flushed: Used when handling queue flushing
164 * @read_count: Current read pointer.
165 * This is the number of buffers that have been removed from both rings.
166 * @stopped: Stopped count.
167 * Set if this TX queue is currently stopping its port.
168 * @insert_count: Current insert pointer
169 * This is the number of buffers that have been added to the
170 * software ring.
171 * @write_count: Current write pointer
172 * This is the number of buffers that have been added to the
173 * hardware ring.
174 * @old_read_count: The value of read_count when last checked.
175 * This is here for performance reasons. The xmit path will
176 * only get the up-to-date value of read_count if this
177 * variable indicates that the queue is full. This is to
178 * avoid cache-line ping-pong between the xmit path and the
179 * completion path.
180 * @tso_headers_free: A list of TSO headers allocated for this TX queue
181 * that are not in use, and so available for new TSO sends. The list
182 * is protected by the TX queue lock.
183 * @tso_bursts: Number of times TSO xmit invoked by kernel
184 * @tso_long_headers: Number of packets with headers too long for standard
185 * blocks
186 * @tso_packets: Number of packets via the TSO xmit path
187 */
188 struct efx_tx_queue {
189 /* Members which don't change on the fast path */
190 struct efx_nic *efx ____cacheline_aligned_in_smp;
191 int queue;
192 struct efx_channel *channel;
193 struct efx_nic *nic;
194 struct efx_tx_buffer *buffer;
195 struct efx_special_buffer txd;
196 bool flushed;
197
198 /* Members used mainly on the completion path */
199 unsigned int read_count ____cacheline_aligned_in_smp;
200 int stopped;
201
202 /* Members used only on the xmit path */
203 unsigned int insert_count ____cacheline_aligned_in_smp;
204 unsigned int write_count;
205 unsigned int old_read_count;
206 struct efx_tso_header *tso_headers_free;
207 unsigned int tso_bursts;
208 unsigned int tso_long_headers;
209 unsigned int tso_packets;
210 };
211
212 /**
213 * struct efx_rx_buffer - An Efx RX data buffer
214 * @dma_addr: DMA base address of the buffer
215 * @skb: The associated socket buffer, if any.
216 * If both this and page are %NULL, the buffer slot is currently free.
217 * @page: The associated page buffer, if any.
218 * If both this and skb are %NULL, the buffer slot is currently free.
219 * @data: Pointer to ethernet header
220 * @len: Buffer length, in bytes.
221 * @unmap_addr: DMA address to unmap
222 */
223 struct efx_rx_buffer {
224 dma_addr_t dma_addr;
225 struct sk_buff *skb;
226 struct page *page;
227 char *data;
228 unsigned int len;
229 dma_addr_t unmap_addr;
230 };
231
232 /**
233 * struct efx_rx_queue - An Efx RX queue
234 * @efx: The associated Efx NIC
235 * @queue: DMA queue number
236 * @channel: The associated channel
237 * @buffer: The software buffer ring
238 * @rxd: The hardware descriptor ring
239 * @added_count: Number of buffers added to the receive queue.
240 * @notified_count: Number of buffers given to NIC (<= @added_count).
241 * @removed_count: Number of buffers removed from the receive queue.
242 * @add_lock: Receive queue descriptor add spin lock.
243 * This lock must be held in order to add buffers to the RX
244 * descriptor ring (rxd and buffer) and to update added_count (but
245 * not removed_count).
246 * @max_fill: RX descriptor maximum fill level (<= ring size)
247 * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill
248 * (<= @max_fill)
249 * @fast_fill_limit: The level to which a fast fill will fill
250 * (@fast_fill_trigger <= @fast_fill_limit <= @max_fill)
251 * @min_fill: RX descriptor minimum non-zero fill level.
252 * This records the minimum fill level observed when a ring
253 * refill was triggered.
254 * @min_overfill: RX descriptor minimum overflow fill level.
255 * This records the minimum fill level at which RX queue
256 * overflow was observed. It should never be set.
257 * @alloc_page_count: RX allocation strategy counter.
258 * @alloc_skb_count: RX allocation strategy counter.
259 * @work: Descriptor push work thread
260 * @buf_page: Page for next RX buffer.
261 * We can use a single page for multiple RX buffers. This tracks
262 * the remaining space in the allocation.
263 * @buf_dma_addr: Page's DMA address.
264 * @buf_data: Page's host address.
265 * @flushed: Use when handling queue flushing
266 */
267 struct efx_rx_queue {
268 struct efx_nic *efx;
269 int queue;
270 struct efx_channel *channel;
271 struct efx_rx_buffer *buffer;
272 struct efx_special_buffer rxd;
273
274 int added_count;
275 int notified_count;
276 int removed_count;
277 spinlock_t add_lock;
278 unsigned int max_fill;
279 unsigned int fast_fill_trigger;
280 unsigned int fast_fill_limit;
281 unsigned int min_fill;
282 unsigned int min_overfill;
283 unsigned int alloc_page_count;
284 unsigned int alloc_skb_count;
285 struct delayed_work work;
286 unsigned int slow_fill_count;
287
288 struct page *buf_page;
289 dma_addr_t buf_dma_addr;
290 char *buf_data;
291 bool flushed;
292 };
293
294 /**
295 * struct efx_buffer - An Efx general-purpose buffer
296 * @addr: host base address of the buffer
297 * @dma_addr: DMA base address of the buffer
298 * @len: Buffer length, in bytes
299 *
300 * Falcon uses these buffers for its interrupt status registers and
301 * MAC stats dumps.
302 */
303 struct efx_buffer {
304 void *addr;
305 dma_addr_t dma_addr;
306 unsigned int len;
307 };
308
309
310 /* Flags for channel->used_flags */
311 #define EFX_USED_BY_RX 1
312 #define EFX_USED_BY_TX 2
313 #define EFX_USED_BY_RX_TX (EFX_USED_BY_RX | EFX_USED_BY_TX)
314
315 enum efx_rx_alloc_method {
316 RX_ALLOC_METHOD_AUTO = 0,
317 RX_ALLOC_METHOD_SKB = 1,
318 RX_ALLOC_METHOD_PAGE = 2,
319 };
320
321 /**
322 * struct efx_channel - An Efx channel
323 *
324 * A channel comprises an event queue, at least one TX queue, at least
325 * one RX queue, and an associated tasklet for processing the event
326 * queue.
327 *
328 * @efx: Associated Efx NIC
329 * @channel: Channel instance number
330 * @name: Name for channel and IRQ
331 * @used_flags: Channel is used by net driver
332 * @enabled: Channel enabled indicator
333 * @irq: IRQ number (MSI and MSI-X only)
334 * @irq_moderation: IRQ moderation value (in us)
335 * @napi_dev: Net device used with NAPI
336 * @napi_str: NAPI control structure
337 * @reset_work: Scheduled reset work thread
338 * @work_pending: Is work pending via NAPI?
339 * @eventq: Event queue buffer
340 * @eventq_read_ptr: Event queue read pointer
341 * @last_eventq_read_ptr: Last event queue read pointer value.
342 * @eventq_magic: Event queue magic value for driver-generated test events
343 * @lro_mgr: LRO state
344 * @rx_alloc_level: Watermark based heuristic counter for pushing descriptors
345 * and diagnostic counters
346 * @rx_alloc_push_pages: RX allocation method currently in use for pushing
347 * descriptors
348 * @rx_alloc_pop_pages: RX allocation method currently in use for popping
349 * descriptors
350 * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors
351 * @n_rx_ip_frag_err: Count of RX IP fragment errors
352 * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors
353 * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors
354 * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors
355 * @n_rx_overlength: Count of RX_OVERLENGTH errors
356 * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun
357 */
358 struct efx_channel {
359 struct efx_nic *efx;
360 int channel;
361 char name[IFNAMSIZ + 6];
362 int used_flags;
363 bool enabled;
364 int irq;
365 unsigned int irq_moderation;
366 struct net_device *napi_dev;
367 struct napi_struct napi_str;
368 bool work_pending;
369 struct efx_special_buffer eventq;
370 unsigned int eventq_read_ptr;
371 unsigned int last_eventq_read_ptr;
372 unsigned int eventq_magic;
373
374 struct net_lro_mgr lro_mgr;
375 int rx_alloc_level;
376 int rx_alloc_push_pages;
377 int rx_alloc_pop_pages;
378
379 unsigned n_rx_tobe_disc;
380 unsigned n_rx_ip_frag_err;
381 unsigned n_rx_ip_hdr_chksum_err;
382 unsigned n_rx_tcp_udp_chksum_err;
383 unsigned n_rx_frm_trunc;
384 unsigned n_rx_overlength;
385 unsigned n_skbuff_leaks;
386
387 /* Used to pipeline received packets in order to optimise memory
388 * access with prefetches.
389 */
390 struct efx_rx_buffer *rx_pkt;
391 bool rx_pkt_csummed;
392
393 };
394
395 /**
396 * struct efx_blinker - S/W LED blinking context
397 * @led_num: LED ID (board-specific meaning)
398 * @state: Current state - on or off
399 * @resubmit: Timer resubmission flag
400 * @timer: Control timer for blinking
401 */
402 struct efx_blinker {
403 int led_num;
404 bool state;
405 bool resubmit;
406 struct timer_list timer;
407 };
408
409
410 /**
411 * struct efx_board - board information
412 * @type: Board model type
413 * @major: Major rev. ('A', 'B' ...)
414 * @minor: Minor rev. (0, 1, ...)
415 * @init: Initialisation function
416 * @init_leds: Sets up board LEDs
417 * @set_fault_led: Turns the fault LED on or off
418 * @blink: Starts/stops blinking
419 * @monitor: Board-specific health check function
420 * @fini: Cleanup function
421 * @blinker: used to blink LEDs in software
422 * @hwmon_client: I2C client for hardware monitor
423 * @ioexp_client: I2C client for power/port control
424 */
425 struct efx_board {
426 int type;
427 int major;
428 int minor;
429 int (*init) (struct efx_nic *nic);
430 /* As the LEDs are typically attached to the PHY, LEDs
431 * have a separate init callback that happens later than
432 * board init. */
433 int (*init_leds)(struct efx_nic *efx);
434 int (*monitor) (struct efx_nic *nic);
435 void (*set_fault_led) (struct efx_nic *efx, bool state);
436 void (*blink) (struct efx_nic *efx, bool start);
437 void (*fini) (struct efx_nic *nic);
438 struct efx_blinker blinker;
439 struct i2c_client *hwmon_client, *ioexp_client;
440 };
441
442 #define STRING_TABLE_LOOKUP(val, member) \
443 member ## _names[val]
444
445 enum efx_int_mode {
446 /* Be careful if altering to correct macro below */
447 EFX_INT_MODE_MSIX = 0,
448 EFX_INT_MODE_MSI = 1,
449 EFX_INT_MODE_LEGACY = 2,
450 EFX_INT_MODE_MAX /* Insert any new items before this */
451 };
452 #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI)
453
454 enum phy_type {
455 PHY_TYPE_NONE = 0,
456 PHY_TYPE_TXC43128 = 1,
457 PHY_TYPE_88E1111 = 2,
458 PHY_TYPE_SFX7101 = 3,
459 PHY_TYPE_QT2022C2 = 4,
460 PHY_TYPE_PM8358 = 6,
461 PHY_TYPE_SFT9001A = 8,
462 PHY_TYPE_SFT9001B = 10,
463 PHY_TYPE_MAX /* Insert any new items before this */
464 };
465
466 #define PHY_ADDR_INVALID 0xff
467
468 #define EFX_IS10G(efx) ((efx)->link_speed == 10000)
469
470 enum nic_state {
471 STATE_INIT = 0,
472 STATE_RUNNING = 1,
473 STATE_FINI = 2,
474 STATE_DISABLED = 3,
475 STATE_MAX,
476 };
477
478 /*
479 * Alignment of page-allocated RX buffers
480 *
481 * Controls the number of bytes inserted at the start of an RX buffer.
482 * This is the equivalent of NET_IP_ALIGN [which controls the alignment
483 * of the skb->head for hardware DMA].
484 */
485 #ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
486 #define EFX_PAGE_IP_ALIGN 0
487 #else
488 #define EFX_PAGE_IP_ALIGN NET_IP_ALIGN
489 #endif
490
491 /*
492 * Alignment of the skb->head which wraps a page-allocated RX buffer
493 *
494 * The skb allocated to wrap an rx_buffer can have this alignment. Since
495 * the data is memcpy'd from the rx_buf, it does not need to be equal to
496 * EFX_PAGE_IP_ALIGN.
497 */
498 #define EFX_PAGE_SKB_ALIGN 2
499
500 /* Forward declaration */
501 struct efx_nic;
502
503 /* Pseudo bit-mask flow control field */
504 enum efx_fc_type {
505 EFX_FC_RX = 1,
506 EFX_FC_TX = 2,
507 EFX_FC_AUTO = 4,
508 };
509
510 /* Supported MAC bit-mask */
511 enum efx_mac_type {
512 EFX_GMAC = 1,
513 EFX_XMAC = 2,
514 };
515
efx_fc_advertise(enum efx_fc_type wanted_fc)516 static inline unsigned int efx_fc_advertise(enum efx_fc_type wanted_fc)
517 {
518 unsigned int adv = 0;
519 if (wanted_fc & EFX_FC_RX)
520 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
521 if (wanted_fc & EFX_FC_TX)
522 adv ^= ADVERTISE_PAUSE_ASYM;
523 return adv;
524 }
525
efx_fc_resolve(enum efx_fc_type wanted_fc,unsigned int lpa)526 static inline enum efx_fc_type efx_fc_resolve(enum efx_fc_type wanted_fc,
527 unsigned int lpa)
528 {
529 unsigned int adv = efx_fc_advertise(wanted_fc);
530
531 if (!(wanted_fc & EFX_FC_AUTO))
532 return wanted_fc;
533
534 if (adv & lpa & ADVERTISE_PAUSE_CAP)
535 return EFX_FC_RX | EFX_FC_TX;
536 if (adv & lpa & ADVERTISE_PAUSE_ASYM) {
537 if (adv & ADVERTISE_PAUSE_CAP)
538 return EFX_FC_RX;
539 if (lpa & ADVERTISE_PAUSE_CAP)
540 return EFX_FC_TX;
541 }
542 return 0;
543 }
544
545 /**
546 * struct efx_mac_operations - Efx MAC operations table
547 * @reconfigure: Reconfigure MAC. Serialised by the mac_lock
548 * @update_stats: Update statistics
549 * @irq: Hardware MAC event callback. Serialised by the mac_lock
550 * @poll: Poll for hardware state. Serialised by the mac_lock
551 */
552 struct efx_mac_operations {
553 void (*reconfigure) (struct efx_nic *efx);
554 void (*update_stats) (struct efx_nic *efx);
555 void (*irq) (struct efx_nic *efx);
556 void (*poll) (struct efx_nic *efx);
557 };
558
559 /**
560 * struct efx_phy_operations - Efx PHY operations table
561 * @init: Initialise PHY
562 * @fini: Shut down PHY
563 * @reconfigure: Reconfigure PHY (e.g. for new link parameters)
564 * @clear_interrupt: Clear down interrupt
565 * @blink: Blink LEDs
566 * @poll: Poll for hardware state. Serialised by the mac_lock.
567 * @get_settings: Get ethtool settings. Serialised by the mac_lock.
568 * @set_settings: Set ethtool settings. Serialised by the mac_lock.
569 * @set_npage_adv: Set abilities advertised in (Extended) Next Page
570 * (only needed where AN bit is set in mmds)
571 * @num_tests: Number of PHY-specific tests/results
572 * @test_names: Names of the tests/results
573 * @run_tests: Run tests and record results as appropriate.
574 * Flags are the ethtool tests flags.
575 * @mmds: MMD presence mask
576 * @loopbacks: Supported loopback modes mask
577 */
578 struct efx_phy_operations {
579 enum efx_mac_type macs;
580 int (*init) (struct efx_nic *efx);
581 void (*fini) (struct efx_nic *efx);
582 void (*reconfigure) (struct efx_nic *efx);
583 void (*clear_interrupt) (struct efx_nic *efx);
584 void (*poll) (struct efx_nic *efx);
585 void (*get_settings) (struct efx_nic *efx,
586 struct ethtool_cmd *ecmd);
587 int (*set_settings) (struct efx_nic *efx,
588 struct ethtool_cmd *ecmd);
589 void (*set_npage_adv) (struct efx_nic *efx, u32);
590 u32 num_tests;
591 const char *const *test_names;
592 int (*run_tests) (struct efx_nic *efx, int *results, unsigned flags);
593 int mmds;
594 unsigned loopbacks;
595 };
596
597 /**
598 * @enum efx_phy_mode - PHY operating mode flags
599 * @PHY_MODE_NORMAL: on and should pass traffic
600 * @PHY_MODE_TX_DISABLED: on with TX disabled
601 * @PHY_MODE_LOW_POWER: set to low power through MDIO
602 * @PHY_MODE_OFF: switched off through external control
603 * @PHY_MODE_SPECIAL: on but will not pass traffic
604 */
605 enum efx_phy_mode {
606 PHY_MODE_NORMAL = 0,
607 PHY_MODE_TX_DISABLED = 1,
608 PHY_MODE_LOW_POWER = 2,
609 PHY_MODE_OFF = 4,
610 PHY_MODE_SPECIAL = 8,
611 };
612
efx_phy_mode_disabled(enum efx_phy_mode mode)613 static inline bool efx_phy_mode_disabled(enum efx_phy_mode mode)
614 {
615 return !!(mode & ~PHY_MODE_TX_DISABLED);
616 }
617
618 /*
619 * Efx extended statistics
620 *
621 * Not all statistics are provided by all supported MACs. The purpose
622 * is this structure is to contain the raw statistics provided by each
623 * MAC.
624 */
625 struct efx_mac_stats {
626 u64 tx_bytes;
627 u64 tx_good_bytes;
628 u64 tx_bad_bytes;
629 unsigned long tx_packets;
630 unsigned long tx_bad;
631 unsigned long tx_pause;
632 unsigned long tx_control;
633 unsigned long tx_unicast;
634 unsigned long tx_multicast;
635 unsigned long tx_broadcast;
636 unsigned long tx_lt64;
637 unsigned long tx_64;
638 unsigned long tx_65_to_127;
639 unsigned long tx_128_to_255;
640 unsigned long tx_256_to_511;
641 unsigned long tx_512_to_1023;
642 unsigned long tx_1024_to_15xx;
643 unsigned long tx_15xx_to_jumbo;
644 unsigned long tx_gtjumbo;
645 unsigned long tx_collision;
646 unsigned long tx_single_collision;
647 unsigned long tx_multiple_collision;
648 unsigned long tx_excessive_collision;
649 unsigned long tx_deferred;
650 unsigned long tx_late_collision;
651 unsigned long tx_excessive_deferred;
652 unsigned long tx_non_tcpudp;
653 unsigned long tx_mac_src_error;
654 unsigned long tx_ip_src_error;
655 u64 rx_bytes;
656 u64 rx_good_bytes;
657 u64 rx_bad_bytes;
658 unsigned long rx_packets;
659 unsigned long rx_good;
660 unsigned long rx_bad;
661 unsigned long rx_pause;
662 unsigned long rx_control;
663 unsigned long rx_unicast;
664 unsigned long rx_multicast;
665 unsigned long rx_broadcast;
666 unsigned long rx_lt64;
667 unsigned long rx_64;
668 unsigned long rx_65_to_127;
669 unsigned long rx_128_to_255;
670 unsigned long rx_256_to_511;
671 unsigned long rx_512_to_1023;
672 unsigned long rx_1024_to_15xx;
673 unsigned long rx_15xx_to_jumbo;
674 unsigned long rx_gtjumbo;
675 unsigned long rx_bad_lt64;
676 unsigned long rx_bad_64_to_15xx;
677 unsigned long rx_bad_15xx_to_jumbo;
678 unsigned long rx_bad_gtjumbo;
679 unsigned long rx_overflow;
680 unsigned long rx_missed;
681 unsigned long rx_false_carrier;
682 unsigned long rx_symbol_error;
683 unsigned long rx_align_error;
684 unsigned long rx_length_error;
685 unsigned long rx_internal_error;
686 unsigned long rx_good_lt64;
687 };
688
689 /* Number of bits used in a multicast filter hash address */
690 #define EFX_MCAST_HASH_BITS 8
691
692 /* Number of (single-bit) entries in a multicast filter hash */
693 #define EFX_MCAST_HASH_ENTRIES (1 << EFX_MCAST_HASH_BITS)
694
695 /* An Efx multicast filter hash */
696 union efx_multicast_hash {
697 u8 byte[EFX_MCAST_HASH_ENTRIES / 8];
698 efx_oword_t oword[EFX_MCAST_HASH_ENTRIES / sizeof(efx_oword_t) / 8];
699 };
700
701 /**
702 * struct efx_nic - an Efx NIC
703 * @name: Device name (net device name or bus id before net device registered)
704 * @pci_dev: The PCI device
705 * @type: Controller type attributes
706 * @legacy_irq: IRQ number
707 * @workqueue: Workqueue for port reconfigures and the HW monitor.
708 * Work items do not hold and must not acquire RTNL.
709 * @workqueue_name: Name of workqueue
710 * @reset_work: Scheduled reset workitem
711 * @monitor_work: Hardware monitor workitem
712 * @membase_phys: Memory BAR value as physical address
713 * @membase: Memory BAR value
714 * @biu_lock: BIU (bus interface unit) lock
715 * @interrupt_mode: Interrupt mode
716 * @i2c_adap: I2C adapter
717 * @board_info: Board-level information
718 * @state: Device state flag. Serialised by the rtnl_lock.
719 * @reset_pending: Pending reset method (normally RESET_TYPE_NONE)
720 * @tx_queue: TX DMA queues
721 * @rx_queue: RX DMA queues
722 * @channel: Channels
723 * @n_rx_queues: Number of RX queues
724 * @n_channels: Number of channels in use
725 * @rx_buffer_len: RX buffer length
726 * @rx_buffer_order: Order (log2) of number of pages for each RX buffer
727 * @irq_status: Interrupt status buffer
728 * @last_irq_cpu: Last CPU to handle interrupt.
729 * This register is written with the SMP processor ID whenever an
730 * interrupt is handled. It is used by falcon_test_interrupt()
731 * to verify that an interrupt has occurred.
732 * @spi_flash: SPI flash device
733 * This field will be %NULL if no flash device is present.
734 * @spi_eeprom: SPI EEPROM device
735 * This field will be %NULL if no EEPROM device is present.
736 * @spi_lock: SPI bus lock
737 * @n_rx_nodesc_drop_cnt: RX no descriptor drop count
738 * @nic_data: Hardware dependant state
739 * @mac_lock: MAC access lock. Protects @port_enabled, @phy_mode,
740 * @port_inhibited, efx_monitor() and efx_reconfigure_port()
741 * @port_enabled: Port enabled indicator.
742 * Serialises efx_stop_all(), efx_start_all(), efx_monitor(),
743 * efx_phy_work(), and efx_mac_work() with kernel interfaces. Safe to read
744 * under any one of the rtnl_lock, mac_lock, or netif_tx_lock, but all
745 * three must be held to modify it.
746 * @port_inhibited: If set, the netif_carrier is always off. Hold the mac_lock
747 * @port_initialized: Port initialized?
748 * @net_dev: Operating system network device. Consider holding the rtnl lock
749 * @rx_checksum_enabled: RX checksumming enabled
750 * @netif_stop_count: Port stop count
751 * @netif_stop_lock: Port stop lock
752 * @mac_stats: MAC statistics. These include all statistics the MACs
753 * can provide. Generic code converts these into a standard
754 * &struct net_device_stats.
755 * @stats_buffer: DMA buffer for statistics
756 * @stats_lock: Statistics update lock. Serialises statistics fetches
757 * @stats_disable_count: Nest count for disabling statistics fetches
758 * @mac_op: MAC interface
759 * @mac_address: Permanent MAC address
760 * @phy_type: PHY type
761 * @phy_lock: PHY access lock
762 * @phy_op: PHY interface
763 * @phy_data: PHY private data (including PHY-specific stats)
764 * @mii: PHY interface
765 * @phy_mode: PHY operating mode. Serialised by @mac_lock.
766 * @mac_up: MAC link state
767 * @link_up: Link status
768 * @link_fd: Link is full duplex
769 * @link_fc: Actualy flow control flags
770 * @link_speed: Link speed (Mbps)
771 * @n_link_state_changes: Number of times the link has changed state
772 * @promiscuous: Promiscuous flag. Protected by netif_tx_lock.
773 * @multicast_hash: Multicast hash table
774 * @wanted_fc: Wanted flow control flags
775 * @phy_work: work item for dealing with PHY events
776 * @mac_work: work item for dealing with MAC events
777 * @loopback_mode: Loopback status
778 * @loopback_modes: Supported loopback mode bitmask
779 * @loopback_selftest: Offline self-test private state
780 *
781 * The @priv field of the corresponding &struct net_device points to
782 * this.
783 */
784 struct efx_nic {
785 char name[IFNAMSIZ];
786 struct pci_dev *pci_dev;
787 const struct efx_nic_type *type;
788 int legacy_irq;
789 struct workqueue_struct *workqueue;
790 char workqueue_name[16];
791 struct work_struct reset_work;
792 struct delayed_work monitor_work;
793 resource_size_t membase_phys;
794 void __iomem *membase;
795 spinlock_t biu_lock;
796 enum efx_int_mode interrupt_mode;
797
798 struct i2c_adapter i2c_adap;
799 struct efx_board board_info;
800
801 enum nic_state state;
802 enum reset_type reset_pending;
803
804 struct efx_tx_queue tx_queue[EFX_TX_QUEUE_COUNT];
805 struct efx_rx_queue rx_queue[EFX_MAX_RX_QUEUES];
806 struct efx_channel channel[EFX_MAX_CHANNELS];
807
808 int n_rx_queues;
809 int n_channels;
810 unsigned int rx_buffer_len;
811 unsigned int rx_buffer_order;
812
813 struct efx_buffer irq_status;
814 volatile signed int last_irq_cpu;
815
816 struct efx_spi_device *spi_flash;
817 struct efx_spi_device *spi_eeprom;
818 struct mutex spi_lock;
819
820 unsigned n_rx_nodesc_drop_cnt;
821
822 struct falcon_nic_data *nic_data;
823
824 struct mutex mac_lock;
825 struct work_struct mac_work;
826 bool port_enabled;
827 bool port_inhibited;
828
829 bool port_initialized;
830 struct net_device *net_dev;
831 bool rx_checksum_enabled;
832
833 atomic_t netif_stop_count;
834 spinlock_t netif_stop_lock;
835
836 struct efx_mac_stats mac_stats;
837 struct efx_buffer stats_buffer;
838 spinlock_t stats_lock;
839 unsigned int stats_disable_count;
840
841 struct efx_mac_operations *mac_op;
842 unsigned char mac_address[ETH_ALEN];
843
844 enum phy_type phy_type;
845 spinlock_t phy_lock;
846 struct work_struct phy_work;
847 struct efx_phy_operations *phy_op;
848 void *phy_data;
849 struct mii_if_info mii;
850 enum efx_phy_mode phy_mode;
851
852 bool mac_up;
853 bool link_up;
854 bool link_fd;
855 enum efx_fc_type link_fc;
856 unsigned int link_speed;
857 unsigned int n_link_state_changes;
858
859 bool promiscuous;
860 union efx_multicast_hash multicast_hash;
861 enum efx_fc_type wanted_fc;
862
863 atomic_t rx_reset;
864 enum efx_loopback_mode loopback_mode;
865 unsigned int loopback_modes;
866
867 void *loopback_selftest;
868 };
869
efx_dev_registered(struct efx_nic * efx)870 static inline int efx_dev_registered(struct efx_nic *efx)
871 {
872 return efx->net_dev->reg_state == NETREG_REGISTERED;
873 }
874
875 /* Net device name, for inclusion in log messages if it has been registered.
876 * Use efx->name not efx->net_dev->name so that races with (un)registration
877 * are harmless.
878 */
efx_dev_name(struct efx_nic * efx)879 static inline const char *efx_dev_name(struct efx_nic *efx)
880 {
881 return efx_dev_registered(efx) ? efx->name : "";
882 }
883
884 /**
885 * struct efx_nic_type - Efx device type definition
886 * @mem_bar: Memory BAR number
887 * @mem_map_size: Memory BAR mapped size
888 * @txd_ptr_tbl_base: TX descriptor ring base address
889 * @rxd_ptr_tbl_base: RX descriptor ring base address
890 * @buf_tbl_base: Buffer table base address
891 * @evq_ptr_tbl_base: Event queue pointer table base address
892 * @evq_rptr_tbl_base: Event queue read-pointer table base address
893 * @txd_ring_mask: TX descriptor ring size - 1 (must be a power of two - 1)
894 * @rxd_ring_mask: RX descriptor ring size - 1 (must be a power of two - 1)
895 * @evq_size: Event queue size (must be a power of two)
896 * @max_dma_mask: Maximum possible DMA mask
897 * @tx_dma_mask: TX DMA mask
898 * @bug5391_mask: Address mask for bug 5391 workaround
899 * @rx_xoff_thresh: RX FIFO XOFF watermark (bytes)
900 * @rx_xon_thresh: RX FIFO XON watermark (bytes)
901 * @rx_buffer_padding: Padding added to each RX buffer
902 * @max_interrupt_mode: Highest capability interrupt mode supported
903 * from &enum efx_init_mode.
904 * @phys_addr_channels: Number of channels with physically addressed
905 * descriptors
906 */
907 struct efx_nic_type {
908 unsigned int mem_bar;
909 unsigned int mem_map_size;
910 unsigned int txd_ptr_tbl_base;
911 unsigned int rxd_ptr_tbl_base;
912 unsigned int buf_tbl_base;
913 unsigned int evq_ptr_tbl_base;
914 unsigned int evq_rptr_tbl_base;
915
916 unsigned int txd_ring_mask;
917 unsigned int rxd_ring_mask;
918 unsigned int evq_size;
919 u64 max_dma_mask;
920 unsigned int tx_dma_mask;
921 unsigned bug5391_mask;
922
923 int rx_xoff_thresh;
924 int rx_xon_thresh;
925 unsigned int rx_buffer_padding;
926 unsigned int max_interrupt_mode;
927 unsigned int phys_addr_channels;
928 };
929
930 /**************************************************************************
931 *
932 * Prototypes and inline functions
933 *
934 *************************************************************************/
935
936 /* Iterate over all used channels */
937 #define efx_for_each_channel(_channel, _efx) \
938 for (_channel = &_efx->channel[0]; \
939 _channel < &_efx->channel[EFX_MAX_CHANNELS]; \
940 _channel++) \
941 if (!_channel->used_flags) \
942 continue; \
943 else
944
945 /* Iterate over all used TX queues */
946 #define efx_for_each_tx_queue(_tx_queue, _efx) \
947 for (_tx_queue = &_efx->tx_queue[0]; \
948 _tx_queue < &_efx->tx_queue[EFX_TX_QUEUE_COUNT]; \
949 _tx_queue++)
950
951 /* Iterate over all TX queues belonging to a channel */
952 #define efx_for_each_channel_tx_queue(_tx_queue, _channel) \
953 for (_tx_queue = &_channel->efx->tx_queue[0]; \
954 _tx_queue < &_channel->efx->tx_queue[EFX_TX_QUEUE_COUNT]; \
955 _tx_queue++) \
956 if (_tx_queue->channel != _channel) \
957 continue; \
958 else
959
960 /* Iterate over all used RX queues */
961 #define efx_for_each_rx_queue(_rx_queue, _efx) \
962 for (_rx_queue = &_efx->rx_queue[0]; \
963 _rx_queue < &_efx->rx_queue[_efx->n_rx_queues]; \
964 _rx_queue++)
965
966 /* Iterate over all RX queues belonging to a channel */
967 #define efx_for_each_channel_rx_queue(_rx_queue, _channel) \
968 for (_rx_queue = &_channel->efx->rx_queue[_channel->channel]; \
969 _rx_queue; \
970 _rx_queue = NULL) \
971 if (_rx_queue->channel != _channel) \
972 continue; \
973 else
974
975 /* Returns a pointer to the specified receive buffer in the RX
976 * descriptor queue.
977 */
efx_rx_buffer(struct efx_rx_queue * rx_queue,unsigned int index)978 static inline struct efx_rx_buffer *efx_rx_buffer(struct efx_rx_queue *rx_queue,
979 unsigned int index)
980 {
981 return (&rx_queue->buffer[index]);
982 }
983
984 /* Set bit in a little-endian bitfield */
set_bit_le(unsigned nr,unsigned char * addr)985 static inline void set_bit_le(unsigned nr, unsigned char *addr)
986 {
987 addr[nr / 8] |= (1 << (nr % 8));
988 }
989
990 /* Clear bit in a little-endian bitfield */
clear_bit_le(unsigned nr,unsigned char * addr)991 static inline void clear_bit_le(unsigned nr, unsigned char *addr)
992 {
993 addr[nr / 8] &= ~(1 << (nr % 8));
994 }
995
996
997 /**
998 * EFX_MAX_FRAME_LEN - calculate maximum frame length
999 *
1000 * This calculates the maximum frame length that will be used for a
1001 * given MTU. The frame length will be equal to the MTU plus a
1002 * constant amount of header space and padding. This is the quantity
1003 * that the net driver will program into the MAC as the maximum frame
1004 * length.
1005 *
1006 * The 10G MAC used in Falcon requires 8-byte alignment on the frame
1007 * length, so we round up to the nearest 8.
1008 */
1009 #define EFX_MAX_FRAME_LEN(mtu) \
1010 ((((mtu) + ETH_HLEN + VLAN_HLEN + 4/* FCS */) + 7) & ~7)
1011
1012
1013 #endif /* EFX_NET_DRIVER_H */
1014