1 /******************************************************************************* 2 3 Intel PRO/1000 Linux driver 4 Copyright(c) 1999 - 2008 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 29 #ifndef _E1000_DEFINES_H_ 30 #define _E1000_DEFINES_H_ 31 32 #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 33 #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 34 #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ 35 #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 36 #define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 37 #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ 38 #define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ 39 #define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ 40 #define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 41 #define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ 42 #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 43 #define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ 44 #define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ 45 #define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ 46 #define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ 47 #define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ 48 #define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ 49 #define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ 50 51 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 52 #define REQ_TX_DESCRIPTOR_MULTIPLE 8 53 #define REQ_RX_DESCRIPTOR_MULTIPLE 8 54 55 /* Definitions for power management and wakeup registers */ 56 /* Wake Up Control */ 57 #define E1000_WUC_APME 0x00000001 /* APM Enable */ 58 #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ 59 60 /* Wake Up Filter Control */ 61 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ 62 #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ 63 #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ 64 #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ 65 #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 66 #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ 67 68 /* Extended Device Control */ 69 #define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Definable Pin 7 */ 70 #define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ 71 #define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ 72 #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 73 #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 74 #define E1000_CTRL_EXT_EIAME 0x01000000 75 #define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ 76 #define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */ 77 #define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */ 78 #define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */ 79 80 /* Receive Descriptor bit definitions */ 81 #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ 82 #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ 83 #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ 84 #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 85 #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ 86 #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ 87 #define E1000_RXD_ERR_CE 0x01 /* CRC Error */ 88 #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ 89 #define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ 90 #define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */ 91 #define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */ 92 #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ 93 #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ 94 95 #define E1000_RXDEXT_STATERR_CE 0x01000000 96 #define E1000_RXDEXT_STATERR_SE 0x02000000 97 #define E1000_RXDEXT_STATERR_SEQ 0x04000000 98 #define E1000_RXDEXT_STATERR_CXE 0x10000000 99 #define E1000_RXDEXT_STATERR_RXE 0x80000000 100 101 /* mask to determine if packets should be dropped due to frame errors */ 102 #define E1000_RXD_ERR_FRAME_ERR_MASK ( \ 103 E1000_RXD_ERR_CE | \ 104 E1000_RXD_ERR_SE | \ 105 E1000_RXD_ERR_SEQ | \ 106 E1000_RXD_ERR_CXE | \ 107 E1000_RXD_ERR_RXE) 108 109 /* Same mask, but for extended and packet split descriptors */ 110 #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ 111 E1000_RXDEXT_STATERR_CE | \ 112 E1000_RXDEXT_STATERR_SE | \ 113 E1000_RXDEXT_STATERR_SEQ | \ 114 E1000_RXDEXT_STATERR_CXE | \ 115 E1000_RXDEXT_STATERR_RXE) 116 117 #define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000 118 119 /* Management Control */ 120 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ 121 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ 122 #define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ 123 #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ 124 #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ 125 /* Enable MAC address filtering */ 126 #define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 127 /* Enable MNG packets to host memory */ 128 #define E1000_MANC_EN_MNG2HOST 0x00200000 129 130 /* Receive Control */ 131 #define E1000_RCTL_EN 0x00000002 /* enable */ 132 #define E1000_RCTL_SBP 0x00000004 /* store bad packet */ 133 #define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ 134 #define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ 135 #define E1000_RCTL_LPE 0x00000020 /* long packet enable */ 136 #define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ 137 #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ 138 #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ 139 #define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */ 140 #define E1000_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min threshold size */ 141 #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ 142 #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ 143 /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ 144 #define E1000_RCTL_SZ_2048 0x00000000 /* Rx buffer size 2048 */ 145 #define E1000_RCTL_SZ_1024 0x00010000 /* Rx buffer size 1024 */ 146 #define E1000_RCTL_SZ_512 0x00020000 /* Rx buffer size 512 */ 147 #define E1000_RCTL_SZ_256 0x00030000 /* Rx buffer size 256 */ 148 /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */ 149 #define E1000_RCTL_SZ_16384 0x00010000 /* Rx buffer size 16384 */ 150 #define E1000_RCTL_SZ_8192 0x00020000 /* Rx buffer size 8192 */ 151 #define E1000_RCTL_SZ_4096 0x00030000 /* Rx buffer size 4096 */ 152 #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ 153 #define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ 154 #define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */ 155 #define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ 156 #define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ 157 158 /* 159 * Use byte values for the following shift parameters 160 * Usage: 161 * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) & 162 * E1000_PSRCTL_BSIZE0_MASK) | 163 * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) & 164 * E1000_PSRCTL_BSIZE1_MASK) | 165 * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) & 166 * E1000_PSRCTL_BSIZE2_MASK) | 167 * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |; 168 * E1000_PSRCTL_BSIZE3_MASK)) 169 * where value0 = [128..16256], default=256 170 * value1 = [1024..64512], default=4096 171 * value2 = [0..64512], default=4096 172 * value3 = [0..64512], default=0 173 */ 174 175 #define E1000_PSRCTL_BSIZE0_MASK 0x0000007F 176 #define E1000_PSRCTL_BSIZE1_MASK 0x00003F00 177 #define E1000_PSRCTL_BSIZE2_MASK 0x003F0000 178 #define E1000_PSRCTL_BSIZE3_MASK 0x3F000000 179 180 #define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */ 181 #define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */ 182 #define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */ 183 #define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */ 184 185 /* SWFW_SYNC Definitions */ 186 #define E1000_SWFW_EEP_SM 0x1 187 #define E1000_SWFW_PHY0_SM 0x2 188 #define E1000_SWFW_PHY1_SM 0x4 189 #define E1000_SWFW_CSR_SM 0x8 190 191 /* Device Control */ 192 #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ 193 #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */ 194 #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ 195 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ 196 #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ 197 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ 198 #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ 199 #define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */ 200 #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ 201 #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ 202 #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ 203 #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ 204 #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ 205 #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ 206 #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ 207 #define E1000_CTRL_RST 0x04000000 /* Global reset */ 208 #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ 209 #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ 210 #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ 211 #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ 212 213 /* 214 * Bit definitions for the Management Data IO (MDIO) and Management Data 215 * Clock (MDC) pins in the Device Control Register. 216 */ 217 218 /* Device Status */ 219 #define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ 220 #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ 221 #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ 222 #define E1000_STATUS_FUNC_SHIFT 2 223 #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ 224 #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ 225 #define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ 226 #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ 227 #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ 228 #define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion by NVM */ 229 #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */ 230 231 /* Constants used to interpret the masked PCI-X bus speed. */ 232 233 #define HALF_DUPLEX 1 234 #define FULL_DUPLEX 2 235 236 237 #define ADVERTISE_10_HALF 0x0001 238 #define ADVERTISE_10_FULL 0x0002 239 #define ADVERTISE_100_HALF 0x0004 240 #define ADVERTISE_100_FULL 0x0008 241 #define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */ 242 #define ADVERTISE_1000_FULL 0x0020 243 244 /* 1000/H is not supported, nor spec-compliant. */ 245 #define E1000_ALL_SPEED_DUPLEX ( ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 246 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 247 ADVERTISE_1000_FULL) 248 #define E1000_ALL_NOT_GIG ( ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 249 ADVERTISE_100_HALF | ADVERTISE_100_FULL) 250 #define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL) 251 #define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL) 252 #define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF) 253 254 #define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX 255 256 /* LED Control */ 257 #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F 258 #define E1000_LEDCTL_LED0_MODE_SHIFT 0 259 #define E1000_LEDCTL_LED0_IVRT 0x00000040 260 #define E1000_LEDCTL_LED0_BLINK 0x00000080 261 262 #define E1000_LEDCTL_MODE_LED_ON 0xE 263 #define E1000_LEDCTL_MODE_LED_OFF 0xF 264 265 /* Transmit Descriptor bit definitions */ 266 #define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */ 267 #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 268 #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 269 #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ 270 #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 271 #define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 272 #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ 273 #define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ 274 #define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ 275 #define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 276 #define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ 277 #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 278 #define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ 279 #define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ 280 #define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ 281 #define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ 282 #define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ 283 #define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ 284 #define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ 285 286 /* Transmit Control */ 287 #define E1000_TCTL_EN 0x00000002 /* enable Tx */ 288 #define E1000_TCTL_PSP 0x00000008 /* pad short packets */ 289 #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ 290 #define E1000_TCTL_COLD 0x003ff000 /* collision distance */ 291 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ 292 #define E1000_TCTL_MULR 0x10000000 /* Multiple request support */ 293 294 /* Transmit Arbitration Count */ 295 296 /* SerDes Control */ 297 #define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400 298 299 /* Receive Checksum Control */ 300 #define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ 301 #define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ 302 303 /* Header split receive */ 304 #define E1000_RFCTL_ACK_DIS 0x00001000 305 #define E1000_RFCTL_EXTEN 0x00008000 306 #define E1000_RFCTL_IPV6_EX_DIS 0x00010000 307 #define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 308 309 /* Collision related configuration parameters */ 310 #define E1000_COLLISION_THRESHOLD 15 311 #define E1000_CT_SHIFT 4 312 #define E1000_COLLISION_DISTANCE 63 313 #define E1000_COLD_SHIFT 12 314 315 /* Default values for the transmit IPG register */ 316 #define DEFAULT_82543_TIPG_IPGT_COPPER 8 317 318 #define E1000_TIPG_IPGT_MASK 0x000003FF 319 320 #define DEFAULT_82543_TIPG_IPGR1 8 321 #define E1000_TIPG_IPGR1_SHIFT 10 322 323 #define DEFAULT_82543_TIPG_IPGR2 6 324 #define DEFAULT_80003ES2LAN_TIPG_IPGR2 7 325 #define E1000_TIPG_IPGR2_SHIFT 20 326 327 #define MAX_JUMBO_FRAME_SIZE 0x3F00 328 329 /* Extended Configuration Control and Size */ 330 #define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020 331 #define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001 332 #define E1000_EXTCNF_CTRL_SWFLAG 0x00000020 333 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000 334 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16 335 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000 336 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16 337 338 #define E1000_PHY_CTRL_D0A_LPLU 0x00000002 339 #define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004 340 #define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008 341 #define E1000_PHY_CTRL_GBE_DISABLE 0x00000040 342 343 #define E1000_KABGTXD_BGSQLBIAS 0x00050000 344 345 /* PBA constants */ 346 #define E1000_PBA_8K 0x0008 /* 8KB */ 347 #define E1000_PBA_16K 0x0010 /* 16KB */ 348 349 #define E1000_PBS_16K E1000_PBA_16K 350 351 #define IFS_MAX 80 352 #define IFS_MIN 40 353 #define IFS_RATIO 4 354 #define IFS_STEP 10 355 #define MIN_NUM_XMITS 1000 356 357 /* SW Semaphore Register */ 358 #define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ 359 #define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ 360 #define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */ 361 362 /* Interrupt Cause Read */ 363 #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ 364 #define E1000_ICR_LSC 0x00000004 /* Link Status Change */ 365 #define E1000_ICR_RXSEQ 0x00000008 /* Rx sequence error */ 366 #define E1000_ICR_RXDMT0 0x00000010 /* Rx desc min. threshold (0) */ 367 #define E1000_ICR_RXT0 0x00000080 /* Rx timer intr (ring 0) */ 368 #define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver should claim the interrupt */ 369 #define E1000_ICR_RXQ0 0x00100000 /* Rx Queue 0 Interrupt */ 370 #define E1000_ICR_RXQ1 0x00200000 /* Rx Queue 1 Interrupt */ 371 #define E1000_ICR_TXQ0 0x00400000 /* Tx Queue 0 Interrupt */ 372 #define E1000_ICR_TXQ1 0x00800000 /* Tx Queue 1 Interrupt */ 373 #define E1000_ICR_OTHER 0x01000000 /* Other Interrupts */ 374 375 /* PBA ECC Register */ 376 #define E1000_PBA_ECC_COUNTER_MASK 0xFFF00000 /* ECC counter mask */ 377 #define E1000_PBA_ECC_COUNTER_SHIFT 20 /* ECC counter shift value */ 378 #define E1000_PBA_ECC_CORR_EN 0x00000001 /* ECC correction enable */ 379 #define E1000_PBA_ECC_STAT_CLR 0x00000002 /* Clear ECC error counter */ 380 #define E1000_PBA_ECC_INT_EN 0x00000004 /* Enable ICR bit 5 for ECC */ 381 382 /* 383 * This defines the bits that are set in the Interrupt Mask 384 * Set/Read Register. Each bit is documented below: 385 * o RXT0 = Receiver Timer Interrupt (ring 0) 386 * o TXDW = Transmit Descriptor Written Back 387 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) 388 * o RXSEQ = Receive Sequence Error 389 * o LSC = Link Status Change 390 */ 391 #define IMS_ENABLE_MASK ( \ 392 E1000_IMS_RXT0 | \ 393 E1000_IMS_TXDW | \ 394 E1000_IMS_RXDMT0 | \ 395 E1000_IMS_RXSEQ | \ 396 E1000_IMS_LSC) 397 398 /* Interrupt Mask Set */ 399 #define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 400 #define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ 401 #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */ 402 #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */ 403 #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* Rx timer intr */ 404 #define E1000_IMS_RXQ0 E1000_ICR_RXQ0 /* Rx Queue 0 Interrupt */ 405 #define E1000_IMS_RXQ1 E1000_ICR_RXQ1 /* Rx Queue 1 Interrupt */ 406 #define E1000_IMS_TXQ0 E1000_ICR_TXQ0 /* Tx Queue 0 Interrupt */ 407 #define E1000_IMS_TXQ1 E1000_ICR_TXQ1 /* Tx Queue 1 Interrupt */ 408 #define E1000_IMS_OTHER E1000_ICR_OTHER /* Other Interrupts */ 409 410 /* Interrupt Cause Set */ 411 #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ 412 #define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */ 413 #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */ 414 415 /* Transmit Descriptor Control */ 416 #define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */ 417 #define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */ 418 #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ 419 #define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */ 420 /* Enable the counting of desc. still to be processed. */ 421 #define E1000_TXDCTL_COUNT_DESC 0x00400000 422 423 /* Flow Control Constants */ 424 #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 425 #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 426 #define FLOW_CONTROL_TYPE 0x8808 427 428 /* 802.1q VLAN Packet Size */ 429 #define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ 430 431 /* Receive Address */ 432 /* 433 * Number of high/low register pairs in the RAR. The RAR (Receive Address 434 * Registers) holds the directed and multicast addresses that we monitor. 435 * Technically, we have 16 spots. However, we reserve one of these spots 436 * (RAR[15]) for our directed address used by controllers with 437 * manageability enabled, allowing us room for 15 multicast addresses. 438 */ 439 #define E1000_RAR_ENTRIES 15 440 #define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ 441 442 /* Error Codes */ 443 #define E1000_ERR_NVM 1 444 #define E1000_ERR_PHY 2 445 #define E1000_ERR_CONFIG 3 446 #define E1000_ERR_PARAM 4 447 #define E1000_ERR_MAC_INIT 5 448 #define E1000_ERR_PHY_TYPE 6 449 #define E1000_ERR_RESET 9 450 #define E1000_ERR_MASTER_REQUESTS_PENDING 10 451 #define E1000_ERR_HOST_INTERFACE_COMMAND 11 452 #define E1000_BLK_PHY_RESET 12 453 #define E1000_ERR_SWFW_SYNC 13 454 #define E1000_NOT_IMPLEMENTED 14 455 456 /* Loop limit on how long we wait for auto-negotiation to complete */ 457 #define FIBER_LINK_UP_LIMIT 50 458 #define COPPER_LINK_UP_LIMIT 10 459 #define PHY_AUTO_NEG_LIMIT 45 460 #define PHY_FORCE_LIMIT 20 461 /* Number of 100 microseconds we wait for PCI Express master disable */ 462 #define MASTER_DISABLE_TIMEOUT 800 463 /* Number of milliseconds we wait for PHY configuration done after MAC reset */ 464 #define PHY_CFG_TIMEOUT 100 465 /* Number of 2 milliseconds we wait for acquiring MDIO ownership. */ 466 #define MDIO_OWNERSHIP_TIMEOUT 10 467 /* Number of milliseconds for NVM auto read done after MAC reset. */ 468 #define AUTO_READ_DONE_TIMEOUT 10 469 470 /* Flow Control */ 471 #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ 472 473 /* Transmit Configuration Word */ 474 #define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */ 475 #define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ 476 #define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ 477 #define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */ 478 #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */ 479 480 /* Receive Configuration Word */ 481 #define E1000_RXCW_IV 0x08000000 /* Receive config invalid */ 482 #define E1000_RXCW_C 0x20000000 /* Receive config */ 483 #define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */ 484 485 /* PCI Express Control */ 486 #define E1000_GCR_RXD_NO_SNOOP 0x00000001 487 #define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002 488 #define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004 489 #define E1000_GCR_TXD_NO_SNOOP 0x00000008 490 #define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010 491 #define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020 492 493 #define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \ 494 E1000_GCR_RXDSCW_NO_SNOOP | \ 495 E1000_GCR_RXDSCR_NO_SNOOP | \ 496 E1000_GCR_TXD_NO_SNOOP | \ 497 E1000_GCR_TXDSCW_NO_SNOOP | \ 498 E1000_GCR_TXDSCR_NO_SNOOP) 499 500 /* PHY Control Register */ 501 #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ 502 #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ 503 #define MII_CR_POWER_DOWN 0x0800 /* Power down */ 504 #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ 505 #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ 506 #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ 507 #define MII_CR_SPEED_1000 0x0040 508 #define MII_CR_SPEED_100 0x2000 509 #define MII_CR_SPEED_10 0x0000 510 511 /* PHY Status Register */ 512 #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ 513 #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ 514 515 /* Autoneg Advertisement Register */ 516 #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ 517 #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ 518 #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ 519 #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ 520 #define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ 521 #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ 522 523 /* Link Partner Ability Register (Base Page) */ 524 #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ 525 #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */ 526 527 /* Autoneg Expansion Register */ 528 #define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */ 529 530 /* 1000BASE-T Control Register */ 531 #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ 532 #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ 533 /* 0=DTE device */ 534 #define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */ 535 /* 0=Configure PHY as Slave */ 536 #define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */ 537 /* 0=Automatic Master/Slave config */ 538 539 /* 1000BASE-T Status Register */ 540 #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ 541 #define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ 542 543 544 /* PHY 1000 MII Register/Bit Definitions */ 545 /* PHY Registers defined by IEEE */ 546 #define PHY_CONTROL 0x00 /* Control Register */ 547 #define PHY_STATUS 0x01 /* Status Register */ 548 #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ 549 #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ 550 #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ 551 #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ 552 #define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */ 553 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ 554 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ 555 #define PHY_EXT_STATUS 0x0F /* Extended Status Reg */ 556 557 /* NVM Control */ 558 #define E1000_EECD_SK 0x00000001 /* NVM Clock */ 559 #define E1000_EECD_CS 0x00000002 /* NVM Chip Select */ 560 #define E1000_EECD_DI 0x00000004 /* NVM Data In */ 561 #define E1000_EECD_DO 0x00000008 /* NVM Data Out */ 562 #define E1000_EECD_REQ 0x00000040 /* NVM Access Request */ 563 #define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */ 564 #define E1000_EECD_PRES 0x00000100 /* NVM Present */ 565 #define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */ 566 /* NVM Addressing bits based on type (0-small, 1-large) */ 567 #define E1000_EECD_ADDR_BITS 0x00000400 568 #define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */ 569 #define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */ 570 #define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */ 571 #define E1000_EECD_SIZE_EX_SHIFT 11 572 #define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */ 573 #define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */ 574 #define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ 575 #define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES) 576 577 #define E1000_NVM_RW_REG_DATA 16 /* Offset to data in NVM read/write registers */ 578 #define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ 579 #define E1000_NVM_RW_REG_START 1 /* Start operation */ 580 #define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ 581 #define E1000_NVM_POLL_WRITE 1 /* Flag for polling for write complete */ 582 #define E1000_NVM_POLL_READ 0 /* Flag for polling for read complete */ 583 #define E1000_FLASH_UPDATES 2000 584 585 /* NVM Word Offsets */ 586 #define NVM_ID_LED_SETTINGS 0x0004 587 #define NVM_INIT_CONTROL2_REG 0x000F 588 #define NVM_INIT_CONTROL3_PORT_B 0x0014 589 #define NVM_INIT_3GIO_3 0x001A 590 #define NVM_INIT_CONTROL3_PORT_A 0x0024 591 #define NVM_CFG 0x0012 592 #define NVM_ALT_MAC_ADDR_PTR 0x0037 593 #define NVM_CHECKSUM_REG 0x003F 594 595 #define E1000_NVM_CFG_DONE_PORT_0 0x40000 /* MNG config cycle done */ 596 #define E1000_NVM_CFG_DONE_PORT_1 0x80000 /* ...for second port */ 597 598 /* Mask bits for fields in Word 0x0f of the NVM */ 599 #define NVM_WORD0F_PAUSE_MASK 0x3000 600 #define NVM_WORD0F_PAUSE 0x1000 601 #define NVM_WORD0F_ASM_DIR 0x2000 602 603 /* Mask bits for fields in Word 0x1a of the NVM */ 604 #define NVM_WORD1A_ASPM_MASK 0x000C 605 606 /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */ 607 #define NVM_SUM 0xBABA 608 609 /* PBA (printed board assembly) number words */ 610 #define NVM_PBA_OFFSET_0 8 611 #define NVM_PBA_OFFSET_1 9 612 613 #define NVM_WORD_SIZE_BASE_SHIFT 6 614 615 /* NVM Commands - SPI */ 616 #define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ 617 #define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */ 618 #define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */ 619 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ 620 #define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */ 621 #define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */ 622 623 /* SPI NVM Status Register */ 624 #define NVM_STATUS_RDY_SPI 0x01 625 626 /* Word definitions for ID LED Settings */ 627 #define ID_LED_RESERVED_0000 0x0000 628 #define ID_LED_RESERVED_FFFF 0xFFFF 629 #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ 630 (ID_LED_OFF1_OFF2 << 8) | \ 631 (ID_LED_DEF1_DEF2 << 4) | \ 632 (ID_LED_DEF1_DEF2)) 633 #define ID_LED_DEF1_DEF2 0x1 634 #define ID_LED_DEF1_ON2 0x2 635 #define ID_LED_DEF1_OFF2 0x3 636 #define ID_LED_ON1_DEF2 0x4 637 #define ID_LED_ON1_ON2 0x5 638 #define ID_LED_ON1_OFF2 0x6 639 #define ID_LED_OFF1_DEF2 0x7 640 #define ID_LED_OFF1_ON2 0x8 641 #define ID_LED_OFF1_OFF2 0x9 642 643 #define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF 644 #define IGP_ACTIVITY_LED_ENABLE 0x0300 645 #define IGP_LED3_MODE 0x07000000 646 647 /* PCI/PCI-X/PCI-EX Config space */ 648 #define PCI_HEADER_TYPE_REGISTER 0x0E 649 #define PCIE_LINK_STATUS 0x12 650 651 #define PCI_HEADER_TYPE_MULTIFUNC 0x80 652 #define PCIE_LINK_WIDTH_MASK 0x3F0 653 #define PCIE_LINK_WIDTH_SHIFT 4 654 655 #define PHY_REVISION_MASK 0xFFFFFFF0 656 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ 657 #define MAX_PHY_MULTI_PAGE_REG 0xF 658 659 /* Bit definitions for valid PHY IDs. */ 660 /* 661 * I = Integrated 662 * E = External 663 */ 664 #define M88E1000_E_PHY_ID 0x01410C50 665 #define M88E1000_I_PHY_ID 0x01410C30 666 #define M88E1011_I_PHY_ID 0x01410C20 667 #define IGP01E1000_I_PHY_ID 0x02A80380 668 #define M88E1111_I_PHY_ID 0x01410CC0 669 #define GG82563_E_PHY_ID 0x01410CA0 670 #define IGP03E1000_E_PHY_ID 0x02A80390 671 #define IFE_E_PHY_ID 0x02A80330 672 #define IFE_PLUS_E_PHY_ID 0x02A80320 673 #define IFE_C_E_PHY_ID 0x02A80310 674 #define BME1000_E_PHY_ID 0x01410CB0 675 #define BME1000_E_PHY_ID_R2 0x01410CB1 676 677 /* M88E1000 Specific Registers */ 678 #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ 679 #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */ 680 #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */ 681 682 #define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */ 683 #define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */ 684 685 /* M88E1000 PHY Specific Control Register */ 686 #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */ 687 #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */ 688 /* Manual MDI configuration */ 689 #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ 690 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */ 691 #define M88E1000_PSCR_AUTO_X_1000T 0x0040 692 /* Auto crossover enabled all speeds */ 693 #define M88E1000_PSCR_AUTO_X_MODE 0x0060 694 /* 695 * 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold) 696 * 0=Normal 10BASE-T Rx Threshold 697 */ 698 #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ 699 700 /* M88E1000 PHY Specific Status Register */ 701 #define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ 702 #define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */ 703 #define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ 704 /* 0=<50M; 1=50-80M; 2=80-110M; 3=110-140M; 4=>140M */ 705 #define M88E1000_PSSR_CABLE_LENGTH 0x0380 706 #define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ 707 #define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ 708 709 #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 710 711 /* 712 * Number of times we will attempt to autonegotiate before downshifting if we 713 * are the master 714 */ 715 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 716 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000 717 /* 718 * Number of times we will attempt to autonegotiate before downshifting if we 719 * are the slave 720 */ 721 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300 722 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 723 #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ 724 725 /* M88EC018 Rev 2 specific DownShift settings */ 726 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00 727 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800 728 729 /* BME1000 PHY Specific Control Register */ 730 #define BME1000_PSCR_ENABLE_DOWNSHIFT 0x0800 /* 1 = enable downshift */ 731 732 733 #define PHY_PAGE_SHIFT 5 734 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \ 735 ((reg) & MAX_PHY_REG_ADDRESS)) 736 737 /* 738 * Bits... 739 * 15-5: page 740 * 4-0: register offset 741 */ 742 #define GG82563_PAGE_SHIFT 5 743 #define GG82563_REG(page, reg) \ 744 (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS)) 745 #define GG82563_MIN_ALT_REG 30 746 747 /* GG82563 Specific Registers */ 748 #define GG82563_PHY_SPEC_CTRL \ 749 GG82563_REG(0, 16) /* PHY Specific Control */ 750 #define GG82563_PHY_PAGE_SELECT \ 751 GG82563_REG(0, 22) /* Page Select */ 752 #define GG82563_PHY_SPEC_CTRL_2 \ 753 GG82563_REG(0, 26) /* PHY Specific Control 2 */ 754 #define GG82563_PHY_PAGE_SELECT_ALT \ 755 GG82563_REG(0, 29) /* Alternate Page Select */ 756 757 #define GG82563_PHY_MAC_SPEC_CTRL \ 758 GG82563_REG(2, 21) /* MAC Specific Control Register */ 759 760 #define GG82563_PHY_DSP_DISTANCE \ 761 GG82563_REG(5, 26) /* DSP Distance */ 762 763 /* Page 193 - Port Control Registers */ 764 #define GG82563_PHY_KMRN_MODE_CTRL \ 765 GG82563_REG(193, 16) /* Kumeran Mode Control */ 766 #define GG82563_PHY_PWR_MGMT_CTRL \ 767 GG82563_REG(193, 20) /* Power Management Control */ 768 769 /* Page 194 - KMRN Registers */ 770 #define GG82563_PHY_INBAND_CTRL \ 771 GG82563_REG(194, 18) /* Inband Control */ 772 773 /* MDI Control */ 774 #define E1000_MDIC_REG_SHIFT 16 775 #define E1000_MDIC_PHY_SHIFT 21 776 #define E1000_MDIC_OP_WRITE 0x04000000 777 #define E1000_MDIC_OP_READ 0x08000000 778 #define E1000_MDIC_READY 0x10000000 779 #define E1000_MDIC_ERROR 0x40000000 780 781 /* SerDes Control */ 782 #define E1000_GEN_POLL_TIMEOUT 640 783 784 #endif /* _E1000_DEFINES_H_ */ 785