1 /*
2 * SH-X3 Setup
3 *
4 * Copyright (C) 2007 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10 #include <linux/platform_device.h>
11 #include <linux/init.h>
12 #include <linux/serial.h>
13 #include <linux/serial_sci.h>
14 #include <linux/io.h>
15 #include <asm/mmzone.h>
16
17 static struct plat_sci_port sci_platform_data[] = {
18 {
19 .mapbase = 0xffc30000,
20 .flags = UPF_BOOT_AUTOCONF,
21 .type = PORT_SCIF,
22 .irqs = { 40, 41, 43, 42 },
23 }, {
24 .mapbase = 0xffc40000,
25 .flags = UPF_BOOT_AUTOCONF,
26 .type = PORT_SCIF,
27 .irqs = { 44, 45, 47, 46 },
28 }, {
29 .mapbase = 0xffc50000,
30 .flags = UPF_BOOT_AUTOCONF,
31 .type = PORT_SCIF,
32 .irqs = { 48, 49, 51, 50 },
33 }, {
34 .mapbase = 0xffc60000,
35 .flags = UPF_BOOT_AUTOCONF,
36 .type = PORT_SCIF,
37 .irqs = { 52, 53, 55, 54 },
38 }, {
39 .flags = 0,
40 }
41 };
42
43 static struct platform_device sci_device = {
44 .name = "sh-sci",
45 .id = -1,
46 .dev = {
47 .platform_data = sci_platform_data,
48 },
49 };
50
51 static struct platform_device *shx3_devices[] __initdata = {
52 &sci_device,
53 };
54
shx3_devices_setup(void)55 static int __init shx3_devices_setup(void)
56 {
57 return platform_add_devices(shx3_devices,
58 ARRAY_SIZE(shx3_devices));
59 }
60 __initcall(shx3_devices_setup);
61
62 enum {
63 UNUSED = 0,
64
65 /* interrupt sources */
66 IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
67 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
68 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
69 IRL_HHLL, IRL_HHLH, IRL_HHHL,
70 IRQ0, IRQ1, IRQ2, IRQ3,
71 HUDII,
72 TMU0, TMU1, TMU2, TMU3, TMU4, TMU5,
73 PCII0, PCII1, PCII2, PCII3, PCII4,
74 PCII5, PCII6, PCII7, PCII8, PCII9,
75 SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
76 SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
77 SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI,
78 SCIF3_ERI, SCIF3_RXI, SCIF3_BRI, SCIF3_TXI,
79 DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2, DMAC0_DMINT3,
80 DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE,
81 DU,
82 DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8, DMAC1_DMINT9,
83 DMAC1_DMINT10, DMAC1_DMINT11, DMAC1_DMAE,
84 IIC, VIN0, VIN1, VCORE0, ATAPI,
85 DTU0_TEND, DTU0_AE, DTU0_TMISS,
86 DTU1_TEND, DTU1_AE, DTU1_TMISS,
87 DTU2_TEND, DTU2_AE, DTU2_TMISS,
88 DTU3_TEND, DTU3_AE, DTU3_TMISS,
89 FE0, FE1,
90 GPIO0, GPIO1, GPIO2, GPIO3,
91 PAM, IRM,
92 INTICI0, INTICI1, INTICI2, INTICI3,
93 INTICI4, INTICI5, INTICI6, INTICI7,
94
95 /* interrupt groups */
96 IRL, PCII56789, SCIF0, SCIF1, SCIF2, SCIF3,
97 DMAC0, DMAC1, DTU0, DTU1, DTU2, DTU3,
98 };
99
100 static struct intc_vect vectors[] __initdata = {
101 INTC_VECT(HUDII, 0x3e0),
102 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
103 INTC_VECT(TMU2, 0x440), INTC_VECT(TMU3, 0x460),
104 INTC_VECT(TMU4, 0x480), INTC_VECT(TMU5, 0x4a0),
105 INTC_VECT(PCII0, 0x500), INTC_VECT(PCII1, 0x520),
106 INTC_VECT(PCII2, 0x540), INTC_VECT(PCII3, 0x560),
107 INTC_VECT(PCII4, 0x580), INTC_VECT(PCII5, 0x5a0),
108 INTC_VECT(PCII6, 0x5c0), INTC_VECT(PCII7, 0x5e0),
109 INTC_VECT(PCII8, 0x600), INTC_VECT(PCII9, 0x620),
110 INTC_VECT(SCIF0_ERI, 0x700), INTC_VECT(SCIF0_RXI, 0x720),
111 INTC_VECT(SCIF0_BRI, 0x740), INTC_VECT(SCIF0_TXI, 0x760),
112 INTC_VECT(SCIF1_ERI, 0x780), INTC_VECT(SCIF1_RXI, 0x7a0),
113 INTC_VECT(SCIF1_BRI, 0x7c0), INTC_VECT(SCIF1_TXI, 0x7e0),
114 INTC_VECT(SCIF2_ERI, 0x800), INTC_VECT(SCIF2_RXI, 0x820),
115 INTC_VECT(SCIF2_BRI, 0x840), INTC_VECT(SCIF2_TXI, 0x860),
116 INTC_VECT(SCIF3_ERI, 0x880), INTC_VECT(SCIF3_RXI, 0x8a0),
117 INTC_VECT(SCIF3_BRI, 0x8c0), INTC_VECT(SCIF3_TXI, 0x8e0),
118 INTC_VECT(DMAC0_DMINT0, 0x900), INTC_VECT(DMAC0_DMINT1, 0x920),
119 INTC_VECT(DMAC0_DMINT2, 0x940), INTC_VECT(DMAC0_DMINT3, 0x960),
120 INTC_VECT(DMAC0_DMINT4, 0x980), INTC_VECT(DMAC0_DMINT5, 0x9a0),
121 INTC_VECT(DMAC0_DMAE, 0x9c0),
122 INTC_VECT(DU, 0x9e0),
123 INTC_VECT(DMAC1_DMINT6, 0xa00), INTC_VECT(DMAC1_DMINT7, 0xa20),
124 INTC_VECT(DMAC1_DMINT8, 0xa40), INTC_VECT(DMAC1_DMINT9, 0xa60),
125 INTC_VECT(DMAC1_DMINT10, 0xa80), INTC_VECT(DMAC1_DMINT11, 0xaa0),
126 INTC_VECT(DMAC1_DMAE, 0xac0),
127 INTC_VECT(IIC, 0xae0),
128 INTC_VECT(VIN0, 0xb00), INTC_VECT(VIN1, 0xb20),
129 INTC_VECT(VCORE0, 0xb00), INTC_VECT(ATAPI, 0xb60),
130 INTC_VECT(DTU0_TEND, 0xc00), INTC_VECT(DTU0_AE, 0xc20),
131 INTC_VECT(DTU0_TMISS, 0xc40),
132 INTC_VECT(DTU1_TEND, 0xc60), INTC_VECT(DTU1_AE, 0xc80),
133 INTC_VECT(DTU1_TMISS, 0xca0),
134 INTC_VECT(DTU2_TEND, 0xcc0), INTC_VECT(DTU2_AE, 0xce0),
135 INTC_VECT(DTU2_TMISS, 0xd00),
136 INTC_VECT(DTU3_TEND, 0xd20), INTC_VECT(DTU3_AE, 0xd40),
137 INTC_VECT(DTU3_TMISS, 0xd60),
138 INTC_VECT(FE0, 0xe00), INTC_VECT(FE1, 0xe20),
139 INTC_VECT(GPIO0, 0xe40), INTC_VECT(GPIO1, 0xe60),
140 INTC_VECT(GPIO2, 0xe80), INTC_VECT(GPIO3, 0xea0),
141 INTC_VECT(PAM, 0xec0), INTC_VECT(IRM, 0xee0),
142 INTC_VECT(INTICI0, 0xf00), INTC_VECT(INTICI1, 0xf20),
143 INTC_VECT(INTICI2, 0xf40), INTC_VECT(INTICI3, 0xf60),
144 INTC_VECT(INTICI4, 0xf80), INTC_VECT(INTICI5, 0xfa0),
145 INTC_VECT(INTICI6, 0xfc0), INTC_VECT(INTICI7, 0xfe0),
146 };
147
148 static struct intc_group groups[] __initdata = {
149 INTC_GROUP(IRL, IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
150 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
151 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
152 IRL_HHLL, IRL_HHLH, IRL_HHHL),
153 INTC_GROUP(PCII56789, PCII5, PCII6, PCII7, PCII8, PCII9),
154 INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
155 INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
156 INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI),
157 INTC_GROUP(SCIF3, SCIF3_ERI, SCIF3_RXI, SCIF3_BRI, SCIF3_TXI),
158 INTC_GROUP(DMAC0, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
159 DMAC0_DMINT3, DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE),
160 INTC_GROUP(DMAC1, DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8,
161 DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11),
162 INTC_GROUP(DTU0, DTU0_TEND, DTU0_AE, DTU0_TMISS),
163 INTC_GROUP(DTU1, DTU1_TEND, DTU1_AE, DTU1_TMISS),
164 INTC_GROUP(DTU2, DTU2_TEND, DTU2_AE, DTU2_TMISS),
165 INTC_GROUP(DTU3, DTU3_TEND, DTU3_AE, DTU3_TMISS),
166 };
167
168 static struct intc_mask_reg mask_registers[] __initdata = {
169 { 0xfe410030, 0xfe410050, 32, /* CnINTMSK0 / CnINTMSKCLR0 */
170 { IRQ0, IRQ1, IRQ2, IRQ3 } },
171 { 0xfe410040, 0xfe410060, 32, /* CnINTMSK1 / CnINTMSKCLR1 */
172 { IRL } },
173 { 0xfe410820, 0xfe410850, 32, /* CnINT2MSK0 / CnINT2MSKCLR0 */
174 { FE1, FE0, 0, ATAPI, VCORE0, VIN1, VIN0, IIC,
175 DU, GPIO3, GPIO2, GPIO1, GPIO0, PAM, 0, 0,
176 0, 0, 0, 0, 0, 0, 0, 0, /* HUDI bits ignored */
177 0, TMU5, TMU4, TMU3, TMU2, TMU1, TMU0, 0, } },
178 { 0xfe410830, 0xfe410860, 32, /* CnINT2MSK1 / CnINT2MSKCLR1 */
179 { 0, 0, 0, 0, DTU3, DTU2, DTU1, DTU0, /* IRM bits ignored */
180 PCII9, PCII8, PCII7, PCII6, PCII5, PCII4, PCII3, PCII2,
181 PCII1, PCII0, DMAC1_DMAE, DMAC1_DMINT11,
182 DMAC1_DMINT10, DMAC1_DMINT9, DMAC1_DMINT8, DMAC1_DMINT7,
183 DMAC1_DMINT6, DMAC0_DMAE, DMAC0_DMINT5, DMAC0_DMINT4,
184 DMAC0_DMINT3, DMAC0_DMINT2, DMAC0_DMINT1, DMAC0_DMINT0 } },
185 { 0xfe410840, 0xfe410870, 32, /* CnINT2MSK2 / CnINT2MSKCLR2 */
186 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
187 SCIF3_TXI, SCIF3_BRI, SCIF3_RXI, SCIF3_ERI,
188 SCIF2_TXI, SCIF2_BRI, SCIF2_RXI, SCIF2_ERI,
189 SCIF1_TXI, SCIF1_BRI, SCIF1_RXI, SCIF1_ERI,
190 SCIF0_TXI, SCIF0_BRI, SCIF0_RXI, SCIF0_ERI } },
191 };
192
193 static struct intc_prio_reg prio_registers[] __initdata = {
194 { 0xfe410010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
195
196 { 0xfe410800, 0, 32, 4, /* INT2PRI0 */ { 0, HUDII, TMU5, TMU4,
197 TMU3, TMU2, TMU1, TMU0 } },
198 { 0xfe410804, 0, 32, 4, /* INT2PRI1 */ { DTU3, DTU2, DTU1, DTU0,
199 SCIF3, SCIF2,
200 SCIF1, SCIF0 } },
201 { 0xfe410808, 0, 32, 4, /* INT2PRI2 */ { DMAC1, DMAC0,
202 PCII56789, PCII4,
203 PCII3, PCII2,
204 PCII1, PCII0 } },
205 { 0xfe41080c, 0, 32, 4, /* INT2PRI3 */ { FE1, FE0, ATAPI, VCORE0,
206 VIN1, VIN0, IIC, DU} },
207 { 0xfe410810, 0, 32, 4, /* INT2PRI4 */ { 0, 0, PAM, GPIO3,
208 GPIO2, GPIO1, GPIO0, IRM } },
209 { 0xfe410090, 0xfe4100a0, 32, 4, /* CnICIPRI / CnICIPRICLR */
210 { INTICI7, INTICI6, INTICI5, INTICI4,
211 INTICI3, INTICI2, INTICI1, INTICI0 }, INTC_SMP(4, 4) },
212 };
213
214 static DECLARE_INTC_DESC(intc_desc, "shx3", vectors, groups,
215 mask_registers, prio_registers, NULL);
216
217 /* Support for external interrupt pins in IRQ mode */
218 static struct intc_vect vectors_irq[] __initdata = {
219 INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
220 INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
221 };
222
223 static struct intc_sense_reg sense_registers[] __initdata = {
224 { 0xfe41001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
225 };
226
227 static DECLARE_INTC_DESC(intc_desc_irq, "shx3-irq", vectors_irq, groups,
228 mask_registers, prio_registers, sense_registers);
229
230 /* External interrupt pins in IRL mode */
231 static struct intc_vect vectors_irl[] __initdata = {
232 INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
233 INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
234 INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
235 INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0),
236 INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320),
237 INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360),
238 INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0),
239 INTC_VECT(IRL_HHHL, 0x3c0),
240 };
241
242 static DECLARE_INTC_DESC(intc_desc_irl, "shx3-irl", vectors_irl, groups,
243 mask_registers, prio_registers, NULL);
244
plat_irq_setup_pins(int mode)245 void __init plat_irq_setup_pins(int mode)
246 {
247 switch (mode) {
248 case IRQ_MODE_IRQ:
249 register_intc_controller(&intc_desc_irq);
250 break;
251 case IRQ_MODE_IRL3210:
252 register_intc_controller(&intc_desc_irl);
253 break;
254 default:
255 BUG();
256 }
257 }
258
plat_irq_setup(void)259 void __init plat_irq_setup(void)
260 {
261 register_intc_controller(&intc_desc);
262 }
263
plat_mem_setup(void)264 void __init plat_mem_setup(void)
265 {
266 unsigned int nid = 1;
267
268 /* Register CPU#0 URAM space as Node 1 */
269 setup_bootmem_node(nid++, 0x145f0000, 0x14610000); /* CPU0 */
270
271 #if 0
272 /* XXX: Not yet.. */
273 setup_bootmem_node(nid++, 0x14df0000, 0x14e10000); /* CPU1 */
274 setup_bootmem_node(nid++, 0x155f0000, 0x15610000); /* CPU2 */
275 setup_bootmem_node(nid++, 0x15df0000, 0x15e10000); /* CPU3 */
276 #endif
277
278 setup_bootmem_node(nid++, 0x16000000, 0x16020000); /* CSM */
279 }
280