1 /* 2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved. 3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved. 4 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public 7 * License as published by the Free Software Foundation; 8 * either version 2, or (at your option) any later version. 9 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even 12 * the implied warranty of MERCHANTABILITY or FITNESS FOR 13 * A PARTICULAR PURPOSE.See the GNU General Public License 14 * for more details. 15 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 20 */ 21 22 #ifndef __SHARE_H__ 23 #define __SHARE_H__ 24 25 /* Define Return Value */ 26 #define FAIL -1 27 #define OK 1 28 29 #ifndef NULL 30 #define NULL 0 31 #endif 32 33 /* Define Bit Field */ 34 #define BIT0 0x01 35 #define BIT1 0x02 36 #define BIT2 0x04 37 #define BIT3 0x08 38 #define BIT4 0x10 39 #define BIT5 0x20 40 #define BIT6 0x40 41 #define BIT7 0x80 42 43 /* Video Memory Size */ 44 #define VIDEO_MEMORY_SIZE_16M 0x1000000 45 46 /* Definition Mode Index 47 */ 48 #define VIA_RES_640X480 0 49 #define VIA_RES_800X600 1 50 #define VIA_RES_1024X768 2 51 #define VIA_RES_1152X864 3 52 #define VIA_RES_1280X1024 4 53 #define VIA_RES_1600X1200 5 54 #define VIA_RES_1440X1050 6 55 #define VIA_RES_1280X768 7 56 #define VIA_RES_1280X960 8 57 #define VIA_RES_1920X1440 9 58 #define VIA_RES_848X480 10 59 #define VIA_RES_1400X1050 11 60 #define VIA_RES_720X480 12 61 #define VIA_RES_720X576 13 62 #define VIA_RES_1024X512 14 63 #define VIA_RES_856X480 15 64 #define VIA_RES_1024X576 16 65 #define VIA_RES_640X400 17 66 #define VIA_RES_1280X720 18 67 #define VIA_RES_1920X1080 19 68 #define VIA_RES_800X480 20 69 #define VIA_RES_1368X768 21 70 #define VIA_RES_1024X600 22 71 #define VIA_RES_1280X800 23 72 #define VIA_RES_1680X1050 24 73 #define VIA_RES_960X600 25 74 #define VIA_RES_1000X600 26 75 #define VIA_RES_1088X612 27 76 #define VIA_RES_1152X720 28 77 #define VIA_RES_1200X720 29 78 #define VIA_RES_1280X600 30 79 #define VIA_RES_1360X768 31 80 #define VIA_RES_1366X768 32 81 #define VIA_RES_1440X900 33 82 #define VIA_RES_1600X900 34 83 #define VIA_RES_1600X1024 35 84 #define VIA_RES_1792X1344 36 85 #define VIA_RES_1856X1392 37 86 #define VIA_RES_1920X1200 38 87 #define VIA_RES_2048X1536 39 88 #define VIA_RES_480X640 40 89 90 /*Reduce Blanking*/ 91 #define VIA_RES_1360X768_RB 131 92 #define VIA_RES_1440X900_RB 133 93 #define VIA_RES_1400X1050_RB 111 94 #define VIA_RES_1600X900_RB 134 95 #define VIA_RES_1680X1050_RB 124 96 #define VIA_RES_1920X1080_RB 119 97 #define VIA_RES_1920X1200_RB 138 98 99 #define VIA_RES_INVALID 255 100 101 /* standard VGA IO port 102 */ 103 #define VIARMisc 0x3CC 104 #define VIAWMisc 0x3C2 105 #define VIAStatus 0x3DA 106 #define VIACR 0x3D4 107 #define VIASR 0x3C4 108 #define VIAGR 0x3CE 109 #define VIAAR 0x3C0 110 111 #define StdCR 0x19 112 #define StdSR 0x04 113 #define StdGR 0x09 114 #define StdAR 0x14 115 116 #define PatchCR 11 117 118 /* Display path */ 119 #define IGA1 1 120 #define IGA2 2 121 #define IGA1_IGA2 3 122 123 /* Define Color Depth */ 124 #define MODE_8BPP 1 125 #define MODE_16BPP 2 126 #define MODE_32BPP 4 127 128 #define GR20 0x20 129 #define GR21 0x21 130 #define GR22 0x22 131 132 /* Sequencer Registers */ 133 #define SR01 0x01 134 #define SR10 0x10 135 #define SR12 0x12 136 #define SR15 0x15 137 #define SR16 0x16 138 #define SR17 0x17 139 #define SR18 0x18 140 #define SR1B 0x1B 141 #define SR1A 0x1A 142 #define SR1C 0x1C 143 #define SR1D 0x1D 144 #define SR1E 0x1E 145 #define SR1F 0x1F 146 #define SR20 0x20 147 #define SR21 0x21 148 #define SR22 0x22 149 #define SR2A 0x2A 150 #define SR2D 0x2D 151 #define SR2E 0x2E 152 153 #define SR30 0x30 154 #define SR39 0x39 155 #define SR3D 0x3D 156 #define SR3E 0x3E 157 #define SR3F 0x3F 158 #define SR40 0x40 159 #define SR43 0x43 160 #define SR44 0x44 161 #define SR45 0x45 162 #define SR46 0x46 163 #define SR47 0x47 164 #define SR48 0x48 165 #define SR49 0x49 166 #define SR4A 0x4A 167 #define SR4B 0x4B 168 #define SR4C 0x4C 169 #define SR52 0x52 170 #define SR5E 0x5E 171 #define SR65 0x65 172 173 /* CRT Controller Registers */ 174 #define CR00 0x00 175 #define CR01 0x01 176 #define CR02 0x02 177 #define CR03 0x03 178 #define CR04 0x04 179 #define CR05 0x05 180 #define CR06 0x06 181 #define CR07 0x07 182 #define CR08 0x08 183 #define CR09 0x09 184 #define CR0A 0x0A 185 #define CR0B 0x0B 186 #define CR0C 0x0C 187 #define CR0D 0x0D 188 #define CR0E 0x0E 189 #define CR0F 0x0F 190 #define CR10 0x10 191 #define CR11 0x11 192 #define CR12 0x12 193 #define CR13 0x13 194 #define CR14 0x14 195 #define CR15 0x15 196 #define CR16 0x16 197 #define CR17 0x17 198 #define CR18 0x18 199 200 /* Extend CRT Controller Registers */ 201 #define CR30 0x30 202 #define CR31 0x31 203 #define CR32 0x32 204 #define CR33 0x33 205 #define CR34 0x34 206 #define CR35 0x35 207 #define CR36 0x36 208 #define CR37 0x37 209 #define CR38 0x38 210 #define CR39 0x39 211 #define CR3A 0x3A 212 #define CR3B 0x3B 213 #define CR3C 0x3C 214 #define CR3D 0x3D 215 #define CR3E 0x3E 216 #define CR3F 0x3F 217 #define CR40 0x40 218 #define CR41 0x41 219 #define CR42 0x42 220 #define CR43 0x43 221 #define CR44 0x44 222 #define CR45 0x45 223 #define CR46 0x46 224 #define CR47 0x47 225 #define CR48 0x48 226 #define CR49 0x49 227 #define CR4A 0x4A 228 #define CR4B 0x4B 229 #define CR4C 0x4C 230 #define CR4D 0x4D 231 #define CR4E 0x4E 232 #define CR4F 0x4F 233 #define CR50 0x50 234 #define CR51 0x51 235 #define CR52 0x52 236 #define CR53 0x53 237 #define CR54 0x54 238 #define CR55 0x55 239 #define CR56 0x56 240 #define CR57 0x57 241 #define CR58 0x58 242 #define CR59 0x59 243 #define CR5A 0x5A 244 #define CR5B 0x5B 245 #define CR5C 0x5C 246 #define CR5D 0x5D 247 #define CR5E 0x5E 248 #define CR5F 0x5F 249 #define CR60 0x60 250 #define CR61 0x61 251 #define CR62 0x62 252 #define CR63 0x63 253 #define CR64 0x64 254 #define CR65 0x65 255 #define CR66 0x66 256 #define CR67 0x67 257 #define CR68 0x68 258 #define CR69 0x69 259 #define CR6A 0x6A 260 #define CR6B 0x6B 261 #define CR6C 0x6C 262 #define CR6D 0x6D 263 #define CR6E 0x6E 264 #define CR6F 0x6F 265 #define CR70 0x70 266 #define CR71 0x71 267 #define CR72 0x72 268 #define CR73 0x73 269 #define CR74 0x74 270 #define CR75 0x75 271 #define CR76 0x76 272 #define CR77 0x77 273 #define CR78 0x78 274 #define CR79 0x79 275 #define CR7A 0x7A 276 #define CR7B 0x7B 277 #define CR7C 0x7C 278 #define CR7D 0x7D 279 #define CR7E 0x7E 280 #define CR7F 0x7F 281 #define CR80 0x80 282 #define CR81 0x81 283 #define CR82 0x82 284 #define CR83 0x83 285 #define CR84 0x84 286 #define CR85 0x85 287 #define CR86 0x86 288 #define CR87 0x87 289 #define CR88 0x88 290 #define CR89 0x89 291 #define CR8A 0x8A 292 #define CR8B 0x8B 293 #define CR8C 0x8C 294 #define CR8D 0x8D 295 #define CR8E 0x8E 296 #define CR8F 0x8F 297 #define CR90 0x90 298 #define CR91 0x91 299 #define CR92 0x92 300 #define CR93 0x93 301 #define CR94 0x94 302 #define CR95 0x95 303 #define CR96 0x96 304 #define CR97 0x97 305 #define CR98 0x98 306 #define CR99 0x99 307 #define CR9A 0x9A 308 #define CR9B 0x9B 309 #define CR9C 0x9C 310 #define CR9D 0x9D 311 #define CR9E 0x9E 312 #define CR9F 0x9F 313 #define CRA0 0xA0 314 #define CRA1 0xA1 315 #define CRA2 0xA2 316 #define CRA3 0xA3 317 #define CRD2 0xD2 318 #define CRD3 0xD3 319 #define CRD4 0xD4 320 321 /* LUT Table*/ 322 #define LUT_DATA 0x3C9 /* DACDATA */ 323 #define LUT_INDEX_READ 0x3C7 /* DACRX */ 324 #define LUT_INDEX_WRITE 0x3C8 /* DACWX */ 325 #define DACMASK 0x3C6 326 327 /* Definition Device */ 328 #define DEVICE_CRT 0x01 329 #define DEVICE_DVI 0x03 330 #define DEVICE_LCD 0x04 331 332 /* Device output interface */ 333 #define INTERFACE_NONE 0x00 334 #define INTERFACE_ANALOG_RGB 0x01 335 #define INTERFACE_DVP0 0x02 336 #define INTERFACE_DVP1 0x03 337 #define INTERFACE_DFP_HIGH 0x04 338 #define INTERFACE_DFP_LOW 0x05 339 #define INTERFACE_DFP 0x06 340 #define INTERFACE_LVDS0 0x07 341 #define INTERFACE_LVDS1 0x08 342 #define INTERFACE_LVDS0LVDS1 0x09 343 #define INTERFACE_TMDS 0x0A 344 345 #define HW_LAYOUT_LCD_ONLY 0x01 346 #define HW_LAYOUT_DVI_ONLY 0x02 347 #define HW_LAYOUT_LCD_DVI 0x03 348 #define HW_LAYOUT_LCD1_LCD2 0x04 349 #define HW_LAYOUT_LCD_EXTERNAL_LCD2 0x10 350 351 /* Definition Refresh Rate */ 352 #define REFRESH_50 50 353 #define REFRESH_60 60 354 #define REFRESH_75 75 355 #define REFRESH_85 85 356 #define REFRESH_100 100 357 #define REFRESH_120 120 358 359 /* Definition Sync Polarity*/ 360 #define NEGATIVE 1 361 #define POSITIVE 0 362 363 /*480x640@60 Sync Polarity (GTF) 364 */ 365 #define M480X640_R60_HSP NEGATIVE 366 #define M480X640_R60_VSP POSITIVE 367 368 /*640x480@60 Sync Polarity (VESA Mode) 369 */ 370 #define M640X480_R60_HSP NEGATIVE 371 #define M640X480_R60_VSP NEGATIVE 372 373 /*640x480@75 Sync Polarity (VESA Mode) 374 */ 375 #define M640X480_R75_HSP NEGATIVE 376 #define M640X480_R75_VSP NEGATIVE 377 378 /*640x480@85 Sync Polarity (VESA Mode) 379 */ 380 #define M640X480_R85_HSP NEGATIVE 381 #define M640X480_R85_VSP NEGATIVE 382 383 /*640x480@100 Sync Polarity (GTF Mode) 384 */ 385 #define M640X480_R100_HSP NEGATIVE 386 #define M640X480_R100_VSP POSITIVE 387 388 /*640x480@120 Sync Polarity (GTF Mode) 389 */ 390 #define M640X480_R120_HSP NEGATIVE 391 #define M640X480_R120_VSP POSITIVE 392 393 /*720x480@60 Sync Polarity (GTF Mode) 394 */ 395 #define M720X480_R60_HSP NEGATIVE 396 #define M720X480_R60_VSP POSITIVE 397 398 /*720x576@60 Sync Polarity (GTF Mode) 399 */ 400 #define M720X576_R60_HSP NEGATIVE 401 #define M720X576_R60_VSP POSITIVE 402 403 /*800x600@60 Sync Polarity (VESA Mode) 404 */ 405 #define M800X600_R60_HSP POSITIVE 406 #define M800X600_R60_VSP POSITIVE 407 408 /*800x600@75 Sync Polarity (VESA Mode) 409 */ 410 #define M800X600_R75_HSP POSITIVE 411 #define M800X600_R75_VSP POSITIVE 412 413 /*800x600@85 Sync Polarity (VESA Mode) 414 */ 415 #define M800X600_R85_HSP POSITIVE 416 #define M800X600_R85_VSP POSITIVE 417 418 /*800x600@100 Sync Polarity (GTF Mode) 419 */ 420 #define M800X600_R100_HSP NEGATIVE 421 #define M800X600_R100_VSP POSITIVE 422 423 /*800x600@120 Sync Polarity (GTF Mode) 424 */ 425 #define M800X600_R120_HSP NEGATIVE 426 #define M800X600_R120_VSP POSITIVE 427 428 /*800x480@60 Sync Polarity (CVT Mode) 429 */ 430 #define M800X480_R60_HSP NEGATIVE 431 #define M800X480_R60_VSP POSITIVE 432 433 /*848x480@60 Sync Polarity (CVT Mode) 434 */ 435 #define M848X480_R60_HSP NEGATIVE 436 #define M848X480_R60_VSP POSITIVE 437 438 /*852x480@60 Sync Polarity (GTF Mode) 439 */ 440 #define M852X480_R60_HSP NEGATIVE 441 #define M852X480_R60_VSP POSITIVE 442 443 /*1024x512@60 Sync Polarity (GTF Mode) 444 */ 445 #define M1024X512_R60_HSP NEGATIVE 446 #define M1024X512_R60_VSP POSITIVE 447 448 /*1024x600@60 Sync Polarity (GTF Mode) 449 */ 450 #define M1024X600_R60_HSP NEGATIVE 451 #define M1024X600_R60_VSP POSITIVE 452 453 /*1024x768@60 Sync Polarity (VESA Mode) 454 */ 455 #define M1024X768_R60_HSP NEGATIVE 456 #define M1024X768_R60_VSP NEGATIVE 457 458 /*1024x768@75 Sync Polarity (VESA Mode) 459 */ 460 #define M1024X768_R75_HSP POSITIVE 461 #define M1024X768_R75_VSP POSITIVE 462 463 /*1024x768@85 Sync Polarity (VESA Mode) 464 */ 465 #define M1024X768_R85_HSP POSITIVE 466 #define M1024X768_R85_VSP POSITIVE 467 468 /*1024x768@100 Sync Polarity (GTF Mode) 469 */ 470 #define M1024X768_R100_HSP NEGATIVE 471 #define M1024X768_R100_VSP POSITIVE 472 473 /*1152x864@75 Sync Polarity (VESA Mode) 474 */ 475 #define M1152X864_R75_HSP POSITIVE 476 #define M1152X864_R75_VSP POSITIVE 477 478 /*1280x720@60 Sync Polarity (GTF Mode) 479 */ 480 #define M1280X720_R60_HSP NEGATIVE 481 #define M1280X720_R60_VSP POSITIVE 482 483 /* 1280x768@50 Sync Polarity (GTF Mode) */ 484 #define M1280X768_R50_HSP NEGATIVE 485 #define M1280X768_R50_VSP POSITIVE 486 487 /*1280x768@60 Sync Polarity (GTF Mode) 488 */ 489 #define M1280X768_R60_HSP NEGATIVE 490 #define M1280X768_R60_VSP POSITIVE 491 492 /*1280x800@60 Sync Polarity (CVT Mode) 493 */ 494 #define M1280X800_R60_HSP NEGATIVE 495 #define M1280X800_R60_VSP POSITIVE 496 497 /*1280x960@60 Sync Polarity (VESA Mode) 498 */ 499 #define M1280X960_R60_HSP POSITIVE 500 #define M1280X960_R60_VSP POSITIVE 501 502 /*1280x1024@60 Sync Polarity (VESA Mode) 503 */ 504 #define M1280X1024_R60_HSP POSITIVE 505 #define M1280X1024_R60_VSP POSITIVE 506 507 /* 1360x768@60 Sync Polarity (CVT Mode) */ 508 #define M1360X768_R60_HSP POSITIVE 509 #define M1360X768_R60_VSP POSITIVE 510 511 /* 1360x768@60 Sync Polarity (CVT Reduce Blanking Mode) */ 512 #define M1360X768_RB_R60_HSP POSITIVE 513 #define M1360X768_RB_R60_VSP NEGATIVE 514 515 /* 1368x768@50 Sync Polarity (GTF Mode) */ 516 #define M1368X768_R50_HSP NEGATIVE 517 #define M1368X768_R50_VSP POSITIVE 518 519 /* 1368x768@60 Sync Polarity (VESA Mode) */ 520 #define M1368X768_R60_HSP NEGATIVE 521 #define M1368X768_R60_VSP POSITIVE 522 523 /*1280x1024@75 Sync Polarity (VESA Mode) 524 */ 525 #define M1280X1024_R75_HSP POSITIVE 526 #define M1280X1024_R75_VSP POSITIVE 527 528 /*1280x1024@85 Sync Polarity (VESA Mode) 529 */ 530 #define M1280X1024_R85_HSP POSITIVE 531 #define M1280X1024_R85_VSP POSITIVE 532 533 /*1440x1050@60 Sync Polarity (GTF Mode) 534 */ 535 #define M1440X1050_R60_HSP NEGATIVE 536 #define M1440X1050_R60_VSP POSITIVE 537 538 /*1600x1200@60 Sync Polarity (VESA Mode) 539 */ 540 #define M1600X1200_R60_HSP POSITIVE 541 #define M1600X1200_R60_VSP POSITIVE 542 543 /*1600x1200@75 Sync Polarity (VESA Mode) 544 */ 545 #define M1600X1200_R75_HSP POSITIVE 546 #define M1600X1200_R75_VSP POSITIVE 547 548 /* 1680x1050@60 Sync Polarity (CVT Mode) */ 549 #define M1680x1050_R60_HSP NEGATIVE 550 #define M1680x1050_R60_VSP NEGATIVE 551 552 /* 1680x1050@60 Sync Polarity (CVT Reduce Blanking Mode) */ 553 #define M1680x1050_RB_R60_HSP POSITIVE 554 #define M1680x1050_RB_R60_VSP NEGATIVE 555 556 /* 1680x1050@75 Sync Polarity (CVT Mode) */ 557 #define M1680x1050_R75_HSP NEGATIVE 558 #define M1680x1050_R75_VSP POSITIVE 559 560 /*1920x1080@60 Sync Polarity (CVT Mode) 561 */ 562 #define M1920X1080_R60_HSP NEGATIVE 563 #define M1920X1080_R60_VSP POSITIVE 564 565 /* 1920x1080@60 Sync Polarity (CVT Reduce Blanking Mode) */ 566 #define M1920X1080_RB_R60_HSP POSITIVE 567 #define M1920X1080_RB_R60_VSP NEGATIVE 568 569 /*1920x1440@60 Sync Polarity (VESA Mode) 570 */ 571 #define M1920X1440_R60_HSP NEGATIVE 572 #define M1920X1440_R60_VSP POSITIVE 573 574 /*1920x1440@75 Sync Polarity (VESA Mode) 575 */ 576 #define M1920X1440_R75_HSP NEGATIVE 577 #define M1920X1440_R75_VSP POSITIVE 578 579 #if 0 580 /* 1400x1050@60 Sync Polarity (VESA Mode) */ 581 #define M1400X1050_R60_HSP NEGATIVE 582 #define M1400X1050_R60_VSP NEGATIVE 583 #endif 584 585 /* 1400x1050@60 Sync Polarity (CVT Mode) */ 586 #define M1400X1050_R60_HSP NEGATIVE 587 #define M1400X1050_R60_VSP POSITIVE 588 589 /* 1400x1050@60 Sync Polarity (CVT Reduce Blanking Mode) */ 590 #define M1400X1050_RB_R60_HSP POSITIVE 591 #define M1400X1050_RB_R60_VSP NEGATIVE 592 593 /* 1400x1050@75 Sync Polarity (CVT Mode) */ 594 #define M1400X1050_R75_HSP NEGATIVE 595 #define M1400X1050_R75_VSP POSITIVE 596 597 /* 960x600@60 Sync Polarity (CVT Mode) */ 598 #define M960X600_R60_HSP NEGATIVE 599 #define M960X600_R60_VSP POSITIVE 600 601 /* 1000x600@60 Sync Polarity (GTF Mode) */ 602 #define M1000X600_R60_HSP NEGATIVE 603 #define M1000X600_R60_VSP POSITIVE 604 605 /* 1024x576@60 Sync Polarity (GTF Mode) */ 606 #define M1024X576_R60_HSP NEGATIVE 607 #define M1024X576_R60_VSP POSITIVE 608 609 /*1024x600@60 Sync Polarity (GTF Mode)*/ 610 #define M1024X600_R60_HSP NEGATIVE 611 #define M1024X600_R60_VSP POSITIVE 612 613 /* 1088x612@60 Sync Polarity (CVT Mode) */ 614 #define M1088X612_R60_HSP NEGATIVE 615 #define M1088X612_R60_VSP POSITIVE 616 617 /* 1152x720@60 Sync Polarity (CVT Mode) */ 618 #define M1152X720_R60_HSP NEGATIVE 619 #define M1152X720_R60_VSP POSITIVE 620 621 /* 1200x720@60 Sync Polarity (GTF Mode) */ 622 #define M1200X720_R60_HSP NEGATIVE 623 #define M1200X720_R60_VSP POSITIVE 624 625 /* 1280x600@60 Sync Polarity (GTF Mode) */ 626 #define M1280x600_R60_HSP NEGATIVE 627 #define M1280x600_R60_VSP POSITIVE 628 629 /* 1280x720@50 Sync Polarity (GTF Mode) */ 630 #define M1280X720_R50_HSP NEGATIVE 631 #define M1280X720_R50_VSP POSITIVE 632 633 /* 1280x720@60 Sync Polarity (CEA Mode) */ 634 #define M1280X720_CEA_R60_HSP POSITIVE 635 #define M1280X720_CEA_R60_VSP POSITIVE 636 637 /* 1440x900@60 Sync Polarity (CVT Mode) */ 638 #define M1440X900_R60_HSP NEGATIVE 639 #define M1440X900_R60_VSP POSITIVE 640 641 /* 1440x900@75 Sync Polarity (CVT Mode) */ 642 #define M1440X900_R75_HSP NEGATIVE 643 #define M1440X900_R75_VSP POSITIVE 644 645 /* 1440x900@60 Sync Polarity (CVT Reduce Blanking Mode) */ 646 #define M1440X900_RB_R60_HSP POSITIVE 647 #define M1440X900_RB_R60_VSP NEGATIVE 648 649 /* 1600x900@60 Sync Polarity (CVT Mode) */ 650 #define M1600X900_R60_HSP NEGATIVE 651 #define M1600X900_R60_VSP POSITIVE 652 653 /* 1600x900@60 Sync Polarity (CVT Reduce Blanking Mode) */ 654 #define M1600X900_RB_R60_HSP POSITIVE 655 #define M1600X900_RB_R60_VSP NEGATIVE 656 657 /* 1600x1024@60 Sync Polarity (GTF Mode) */ 658 #define M1600X1024_R60_HSP NEGATIVE 659 #define M1600X1024_R60_VSP POSITIVE 660 661 /* 1792x1344@60 Sync Polarity (DMT Mode) */ 662 #define M1792x1344_R60_HSP NEGATIVE 663 #define M1792x1344_R60_VSP POSITIVE 664 665 /* 1856x1392@60 Sync Polarity (DMT Mode) */ 666 #define M1856x1392_R60_HSP NEGATIVE 667 #define M1856x1392_R60_VSP POSITIVE 668 669 /* 1920x1200@60 Sync Polarity (CVT Mode) */ 670 #define M1920X1200_R60_HSP NEGATIVE 671 #define M1920X1200_R60_VSP POSITIVE 672 673 /* 1920x1200@60 Sync Polarity (CVT Reduce Blanking Mode) */ 674 #define M1920X1200_RB_R60_HSP POSITIVE 675 #define M1920X1200_RB_R60_VSP NEGATIVE 676 677 /* 1920x1080@60 Sync Polarity (CEA Mode) */ 678 #define M1920X1080_CEA_R60_HSP POSITIVE 679 #define M1920X1080_CEA_R60_VSP POSITIVE 680 681 /* 2048x1536@60 Sync Polarity (CVT Mode) */ 682 #define M2048x1536_R60_HSP NEGATIVE 683 #define M2048x1536_R60_VSP POSITIVE 684 685 /* define PLL index: */ 686 #define CLK_25_175M 25175000 687 #define CLK_26_880M 26880000 688 #define CLK_29_581M 29581000 689 #define CLK_31_490M 31490000 690 #define CLK_31_500M 31500000 691 #define CLK_31_728M 31728000 692 #define CLK_32_668M 32688000 693 #define CLK_36_000M 36000000 694 #define CLK_40_000M 40000000 695 #define CLK_41_291M 41291000 696 #define CLK_43_163M 43163000 697 #define CLK_45_250M 45250000 /* 45.46MHz */ 698 #define CLK_46_000M 46000000 699 #define CLK_46_996M 46996000 700 #define CLK_48_000M 48000000 701 #define CLK_48_875M 48875000 702 #define CLK_49_500M 49500000 703 #define CLK_52_406M 52406000 704 #define CLK_52_977M 52977000 705 #define CLK_56_250M 56250000 706 #define CLK_60_466M 60466000 707 #define CLK_61_500M 61500000 708 #define CLK_65_000M 65000000 709 #define CLK_65_178M 65178000 710 #define CLK_66_750M 66750000 /* 67.116MHz */ 711 #define CLK_68_179M 68179000 712 #define CLK_69_924M 69924000 713 #define CLK_70_159M 70159000 714 #define CLK_72_000M 72000000 715 #define CLK_74_270M 74270000 716 #define CLK_78_750M 78750000 717 #define CLK_80_136M 80136000 718 #define CLK_83_375M 83375000 719 #define CLK_83_950M 83950000 720 #define CLK_84_750M 84750000 /* 84.537Mhz */ 721 #define CLK_85_860M 85860000 722 #define CLK_88_750M 88750000 723 #define CLK_94_500M 94500000 724 #define CLK_97_750M 97750000 725 #define CLK_101_000M 101000000 726 #define CLK_106_500M 106500000 727 #define CLK_108_000M 108000000 728 #define CLK_113_309M 113309000 729 #define CLK_118_840M 118840000 730 #define CLK_119_000M 119000000 731 #define CLK_121_750M 121750000 /* 121.704MHz */ 732 #define CLK_125_104M 125104000 733 #define CLK_133_308M 133308000 734 #define CLK_135_000M 135000000 735 #define CLK_136_700M 136700000 736 #define CLK_138_400M 138400000 737 #define CLK_146_760M 146760000 738 #define CLK_148_500M 148500000 739 740 #define CLK_153_920M 153920000 741 #define CLK_156_000M 156000000 742 #define CLK_157_500M 157500000 743 #define CLK_162_000M 162000000 744 #define CLK_187_000M 187000000 745 #define CLK_193_295M 193295000 746 #define CLK_202_500M 202500000 747 #define CLK_204_000M 204000000 748 #define CLK_218_500M 218500000 749 #define CLK_234_000M 234000000 750 #define CLK_267_250M 267250000 751 #define CLK_297_500M 297500000 752 #define CLK_74_481M 74481000 753 #define CLK_172_798M 172798000 754 #define CLK_122_614M 122614000 755 756 /* CLE266 PLL value 757 */ 758 #define CLE266_PLL_25_175M 0x0000C763 759 #define CLE266_PLL_26_880M 0x0000440F 760 #define CLE266_PLL_29_581M 0x00008421 761 #define CLE266_PLL_31_490M 0x00004721 762 #define CLE266_PLL_31_500M 0x0000C3B5 763 #define CLE266_PLL_31_728M 0x0000471F 764 #define CLE266_PLL_32_668M 0x0000C449 765 #define CLE266_PLL_36_000M 0x0000C5E5 766 #define CLE266_PLL_40_000M 0x0000C459 767 #define CLE266_PLL_41_291M 0x00004417 768 #define CLE266_PLL_43_163M 0x0000C579 769 #define CLE266_PLL_45_250M 0x0000C57F /* 45.46MHz */ 770 #define CLE266_PLL_46_000M 0x0000875A 771 #define CLE266_PLL_46_996M 0x0000C4E9 772 #define CLE266_PLL_48_000M 0x00001443 773 #define CLE266_PLL_48_875M 0x00001D63 774 #define CLE266_PLL_49_500M 0x00008653 775 #define CLE266_PLL_52_406M 0x0000C475 776 #define CLE266_PLL_52_977M 0x00004525 777 #define CLE266_PLL_56_250M 0x000047B7 778 #define CLE266_PLL_60_466M 0x0000494C 779 #define CLE266_PLL_61_500M 0x00001456 780 #define CLE266_PLL_65_000M 0x000086ED 781 #define CLE266_PLL_65_178M 0x0000855B 782 #define CLE266_PLL_66_750M 0x0000844B /* 67.116MHz */ 783 #define CLE266_PLL_68_179M 0x00000413 784 #define CLE266_PLL_69_924M 0x00001153 785 #define CLE266_PLL_70_159M 0x00001462 786 #define CLE266_PLL_72_000M 0x00001879 787 #define CLE266_PLL_74_270M 0x00004853 788 #define CLE266_PLL_78_750M 0x00004321 789 #define CLE266_PLL_80_136M 0x0000051C 790 #define CLE266_PLL_83_375M 0x0000C25D 791 #define CLE266_PLL_83_950M 0x00000729 792 #define CLE266_PLL_84_750M 0x00008576 /* 84.537MHz */ 793 #define CLE266_PLL_85_860M 0x00004754 794 #define CLE266_PLL_88_750M 0x0000051F 795 #define CLE266_PLL_94_500M 0x00000521 796 #define CLE266_PLL_97_750M 0x00004652 797 #define CLE266_PLL_101_000M 0x0000497F 798 #define CLE266_PLL_106_500M 0x00008477 /* 106.491463 MHz */ 799 #define CLE266_PLL_108_000M 0x00008479 800 #define CLE266_PLL_113_309M 0x00000C5F 801 #define CLE266_PLL_118_840M 0x00004553 802 #define CLE266_PLL_119_000M 0x00000D6C 803 #define CLE266_PLL_121_750M 0x00004555 /* 121.704MHz */ 804 #define CLE266_PLL_125_104M 0x000006B5 805 #define CLE266_PLL_133_308M 0x0000465F 806 #define CLE266_PLL_135_000M 0x0000455E 807 #define CLE266_PLL_136_700M 0x00000C73 808 #define CLE266_PLL_138_400M 0x00000957 809 #define CLE266_PLL_146_760M 0x00004567 810 #define CLE266_PLL_148_500M 0x00000853 811 #define CLE266_PLL_153_920M 0x00000856 812 #define CLE266_PLL_156_000M 0x0000456D 813 #define CLE266_PLL_157_500M 0x000005B7 814 #define CLE266_PLL_162_000M 0x00004571 815 #define CLE266_PLL_187_000M 0x00000976 816 #define CLE266_PLL_193_295M 0x0000086C 817 #define CLE266_PLL_202_500M 0x00000763 818 #define CLE266_PLL_204_000M 0x00000764 819 #define CLE266_PLL_218_500M 0x0000065C 820 #define CLE266_PLL_234_000M 0x00000662 821 #define CLE266_PLL_267_250M 0x00000670 822 #define CLE266_PLL_297_500M 0x000005E6 823 #define CLE266_PLL_74_481M 0x0000051A 824 #define CLE266_PLL_172_798M 0x00004579 825 #define CLE266_PLL_122_614M 0x0000073C 826 827 /* K800 PLL value 828 */ 829 #define K800_PLL_25_175M 0x00539001 830 #define K800_PLL_26_880M 0x001C8C80 831 #define K800_PLL_29_581M 0x00409080 832 #define K800_PLL_31_490M 0x006F9001 833 #define K800_PLL_31_500M 0x008B9002 834 #define K800_PLL_31_728M 0x00AF9003 835 #define K800_PLL_32_668M 0x00909002 836 #define K800_PLL_36_000M 0x009F9002 837 #define K800_PLL_40_000M 0x00578C02 838 #define K800_PLL_41_291M 0x00438C01 839 #define K800_PLL_43_163M 0x00778C03 840 #define K800_PLL_45_250M 0x007D8C83 /* 45.46MHz */ 841 #define K800_PLL_46_000M 0x00658C02 842 #define K800_PLL_46_996M 0x00818C83 843 #define K800_PLL_48_000M 0x00848C83 844 #define K800_PLL_48_875M 0x00508C81 845 #define K800_PLL_49_500M 0x00518C01 846 #define K800_PLL_52_406M 0x00738C02 847 #define K800_PLL_52_977M 0x00928C83 848 #define K800_PLL_56_250M 0x007C8C02 849 #define K800_PLL_60_466M 0x00A78C83 850 #define K800_PLL_61_500M 0x00AA8C83 851 #define K800_PLL_65_000M 0x006B8C01 852 #define K800_PLL_65_178M 0x00B48C83 853 #define K800_PLL_66_750M 0x00948C82 /* 67.116MHz */ 854 #define K800_PLL_68_179M 0x00708C01 855 #define K800_PLL_69_924M 0x00C18C83 856 #define K800_PLL_70_159M 0x00C28C83 857 #define K800_PLL_72_000M 0x009F8C82 858 #define K800_PLL_74_270M 0x00ce0c03 859 #define K800_PLL_78_750M 0x00408801 860 #define K800_PLL_80_136M 0x00428801 861 #define K800_PLL_83_375M 0x005B0882 862 #define K800_PLL_83_950M 0x00738803 863 #define K800_PLL_84_750M 0x00748883 /* 84.477MHz */ 864 #define K800_PLL_85_860M 0x00768883 865 #define K800_PLL_88_750M 0x007A8883 866 #define K800_PLL_94_500M 0x00828803 867 #define K800_PLL_97_750M 0x00878883 868 #define K800_PLL_101_000M 0x008B8883 869 #define K800_PLL_106_500M 0x00758882 /* 106.491463 MHz */ 870 #define K800_PLL_108_000M 0x00778882 871 #define K800_PLL_113_309M 0x005D8881 872 #define K800_PLL_118_840M 0x00A48883 873 #define K800_PLL_119_000M 0x00838882 874 #define K800_PLL_121_750M 0x00A88883 /* 121.704MHz */ 875 #define K800_PLL_125_104M 0x00688801 876 #define K800_PLL_133_308M 0x005D8801 877 #define K800_PLL_135_000M 0x001A4081 878 #define K800_PLL_136_700M 0x00BD8883 879 #define K800_PLL_138_400M 0x00728881 880 #define K800_PLL_146_760M 0x00CC8883 881 #define K800_PLL_148_500M 0x00ce0803 882 #define K800_PLL_153_920M 0x00548482 883 #define K800_PLL_156_000M 0x006B8483 884 #define K800_PLL_157_500M 0x00142080 885 #define K800_PLL_162_000M 0x006F8483 886 #define K800_PLL_187_000M 0x00818483 887 #define K800_PLL_193_295M 0x004F8481 888 #define K800_PLL_202_500M 0x00538481 889 #define K800_PLL_204_000M 0x008D8483 890 #define K800_PLL_218_500M 0x00978483 891 #define K800_PLL_234_000M 0x00608401 892 #define K800_PLL_267_250M 0x006E8481 893 #define K800_PLL_297_500M 0x00A48402 894 #define K800_PLL_74_481M 0x007B8C81 895 #define K800_PLL_172_798M 0x00778483 896 #define K800_PLL_122_614M 0x00878882 897 898 /* PLL for VT3324 */ 899 #define CX700_25_175M 0x008B1003 900 #define CX700_26_719M 0x00931003 901 #define CX700_26_880M 0x00941003 902 #define CX700_29_581M 0x00A49003 903 #define CX700_31_490M 0x00AE1003 904 #define CX700_31_500M 0x00AE1003 905 #define CX700_31_728M 0x00AF1003 906 #define CX700_32_668M 0x00B51003 907 #define CX700_36_000M 0x00C81003 908 #define CX700_40_000M 0x006E0C03 909 #define CX700_41_291M 0x00710C03 910 #define CX700_43_163M 0x00770C03 911 #define CX700_45_250M 0x007D0C03 /* 45.46MHz */ 912 #define CX700_46_000M 0x007F0C03 913 #define CX700_46_996M 0x00818C83 914 #define CX700_48_000M 0x00840C03 915 #define CX700_48_875M 0x00508C81 916 #define CX700_49_500M 0x00880C03 917 #define CX700_52_406M 0x00730C02 918 #define CX700_52_977M 0x00920C03 919 #define CX700_56_250M 0x009B0C03 920 #define CX700_60_466M 0x00460C00 921 #define CX700_61_500M 0x00AA0C03 922 #define CX700_65_000M 0x006B0C01 923 #define CX700_65_178M 0x006B0C01 924 #define CX700_66_750M 0x00940C02 /*67.116MHz */ 925 #define CX700_68_179M 0x00BC0C03 926 #define CX700_69_924M 0x00C10C03 927 #define CX700_70_159M 0x00C20C03 928 #define CX700_72_000M 0x009F0C02 929 #define CX700_74_270M 0x00CE0C03 930 #define CX700_74_481M 0x00CE0C03 931 #define CX700_78_750M 0x006C0803 932 #define CX700_80_136M 0x006E0803 933 #define CX700_83_375M 0x005B0882 934 #define CX700_83_950M 0x00730803 935 #define CX700_84_750M 0x00740803 /* 84.537Mhz */ 936 #define CX700_85_860M 0x00760803 937 #define CX700_88_750M 0x00AC8885 938 #define CX700_94_500M 0x00820803 939 #define CX700_97_750M 0x00870803 940 #define CX700_101_000M 0x008B0803 941 #define CX700_106_500M 0x00750802 942 #define CX700_108_000M 0x00950803 943 #define CX700_113_309M 0x005D0801 944 #define CX700_118_840M 0x00A40803 945 #define CX700_119_000M 0x00830802 946 #define CX700_121_750M 0x00420800 /* 121.704MHz */ 947 #define CX700_125_104M 0x00AD0803 948 #define CX700_133_308M 0x00930802 949 #define CX700_135_000M 0x00950802 950 #define CX700_136_700M 0x00BD0803 951 #define CX700_138_400M 0x00720801 952 #define CX700_146_760M 0x00CC0803 953 #define CX700_148_500M 0x00a40802 954 #define CX700_153_920M 0x00540402 955 #define CX700_156_000M 0x006B0403 956 #define CX700_157_500M 0x006C0403 957 #define CX700_162_000M 0x006F0403 958 #define CX700_172_798M 0x00770403 959 #define CX700_187_000M 0x00810403 960 #define CX700_193_295M 0x00850403 961 #define CX700_202_500M 0x008C0403 962 #define CX700_204_000M 0x008D0403 963 #define CX700_218_500M 0x00970403 964 #define CX700_234_000M 0x00600401 965 #define CX700_267_250M 0x00B90403 966 #define CX700_297_500M 0x00CE0403 967 #define CX700_122_614M 0x00870802 968 969 /* Definition CRTC Timing Index */ 970 #define H_TOTAL_INDEX 0 971 #define H_ADDR_INDEX 1 972 #define H_BLANK_START_INDEX 2 973 #define H_BLANK_END_INDEX 3 974 #define H_SYNC_START_INDEX 4 975 #define H_SYNC_END_INDEX 5 976 #define V_TOTAL_INDEX 6 977 #define V_ADDR_INDEX 7 978 #define V_BLANK_START_INDEX 8 979 #define V_BLANK_END_INDEX 9 980 #define V_SYNC_START_INDEX 10 981 #define V_SYNC_END_INDEX 11 982 #define H_TOTAL_SHADOW_INDEX 12 983 #define H_BLANK_END_SHADOW_INDEX 13 984 #define V_TOTAL_SHADOW_INDEX 14 985 #define V_ADDR_SHADOW_INDEX 15 986 #define V_BLANK_SATRT_SHADOW_INDEX 16 987 #define V_BLANK_END_SHADOW_INDEX 17 988 #define V_SYNC_SATRT_SHADOW_INDEX 18 989 #define V_SYNC_END_SHADOW_INDEX 19 990 991 /* Definition Video Mode Pixel Clock (picoseconds) 992 */ 993 #define RES_480X640_60HZ_PIXCLOCK 39722 994 #define RES_640X480_60HZ_PIXCLOCK 39722 995 #define RES_640X480_75HZ_PIXCLOCK 31747 996 #define RES_640X480_85HZ_PIXCLOCK 27777 997 #define RES_640X480_100HZ_PIXCLOCK 23168 998 #define RES_640X480_120HZ_PIXCLOCK 19081 999 #define RES_720X480_60HZ_PIXCLOCK 37020 1000 #define RES_720X576_60HZ_PIXCLOCK 30611 1001 #define RES_800X600_60HZ_PIXCLOCK 25000 1002 #define RES_800X600_75HZ_PIXCLOCK 20203 1003 #define RES_800X600_85HZ_PIXCLOCK 17777 1004 #define RES_800X600_100HZ_PIXCLOCK 14667 1005 #define RES_800X600_120HZ_PIXCLOCK 11912 1006 #define RES_800X480_60HZ_PIXCLOCK 33805 1007 #define RES_848X480_60HZ_PIXCLOCK 31756 1008 #define RES_856X480_60HZ_PIXCLOCK 31518 1009 #define RES_1024X512_60HZ_PIXCLOCK 24218 1010 #define RES_1024X600_60HZ_PIXCLOCK 20460 1011 #define RES_1024X768_60HZ_PIXCLOCK 15385 1012 #define RES_1024X768_75HZ_PIXCLOCK 12699 1013 #define RES_1024X768_85HZ_PIXCLOCK 10582 1014 #define RES_1024X768_100HZ_PIXCLOCK 8825 1015 #define RES_1152X864_75HZ_PIXCLOCK 9259 1016 #define RES_1280X768_60HZ_PIXCLOCK 12480 1017 #define RES_1280X800_60HZ_PIXCLOCK 11994 1018 #define RES_1280X960_60HZ_PIXCLOCK 9259 1019 #define RES_1280X1024_60HZ_PIXCLOCK 9260 1020 #define RES_1280X1024_75HZ_PIXCLOCK 7408 1021 #define RES_1280X768_85HZ_PIXCLOCK 6349 1022 #define RES_1440X1050_60HZ_PIXCLOCK 7993 1023 #define RES_1600X1200_60HZ_PIXCLOCK 6172 1024 #define RES_1600X1200_75HZ_PIXCLOCK 4938 1025 #define RES_1280X720_60HZ_PIXCLOCK 13426 1026 #define RES_1920X1080_60HZ_PIXCLOCK 5787 1027 #define RES_1400X1050_60HZ_PIXCLOCK 8214 1028 #define RES_1400X1050_75HZ_PIXCLOCK 6410 1029 #define RES_1368X768_60HZ_PIXCLOCK 11647 1030 #define RES_960X600_60HZ_PIXCLOCK 22099 1031 #define RES_1000X600_60HZ_PIXCLOCK 20834 1032 #define RES_1024X576_60HZ_PIXCLOCK 21278 1033 #define RES_1088X612_60HZ_PIXCLOCK 18877 1034 #define RES_1152X720_60HZ_PIXCLOCK 14981 1035 #define RES_1200X720_60HZ_PIXCLOCK 14253 1036 #define RES_1280X600_60HZ_PIXCLOCK 16260 1037 #define RES_1280X720_50HZ_PIXCLOCK 16538 1038 #define RES_1280X768_50HZ_PIXCLOCK 15342 1039 #define RES_1366X768_50HZ_PIXCLOCK 14301 1040 #define RES_1366X768_60HZ_PIXCLOCK 11646 1041 #define RES_1360X768_60HZ_PIXCLOCK 11799 1042 #define RES_1440X900_60HZ_PIXCLOCK 9390 1043 #define RES_1440X900_75HZ_PIXCLOCK 7315 1044 #define RES_1600X900_60HZ_PIXCLOCK 8415 1045 #define RES_1600X1024_60HZ_PIXCLOCK 7315 1046 #define RES_1680X1050_60HZ_PIXCLOCK 6814 1047 #define RES_1680X1050_75HZ_PIXCLOCK 5348 1048 #define RES_1792X1344_60HZ_PIXCLOCK 4902 1049 #define RES_1856X1392_60HZ_PIXCLOCK 4577 1050 #define RES_1920X1200_60HZ_PIXCLOCK 5173 1051 #define RES_1920X1440_60HZ_PIXCLOCK 4274 1052 #define RES_1920X1440_75HZ_PIXCLOCK 3367 1053 #define RES_2048X1536_60HZ_PIXCLOCK 3742 1054 1055 #define RES_1360X768_RB_60HZ_PIXCLOCK 13889 1056 #define RES_1400X1050_RB_60HZ_PIXCLOCK 9901 1057 #define RES_1440X900_RB_60HZ_PIXCLOCK 11268 1058 #define RES_1600X900_RB_60HZ_PIXCLOCK 10230 1059 #define RES_1680X1050_RB_60HZ_PIXCLOCK 8403 1060 #define RES_1920X1080_RB_60HZ_PIXCLOCK 7225 1061 #define RES_1920X1200_RB_60HZ_PIXCLOCK 6497 1062 1063 /* LCD display method 1064 */ 1065 #define LCD_EXPANDSION 0x00 1066 #define LCD_CENTERING 0x01 1067 1068 /* LCD mode 1069 */ 1070 #define LCD_OPENLDI 0x00 1071 #define LCD_SPWG 0x01 1072 1073 /* Define display timing 1074 */ 1075 struct display_timing { 1076 u16 hor_total; 1077 u16 hor_addr; 1078 u16 hor_blank_start; 1079 u16 hor_blank_end; 1080 u16 hor_sync_start; 1081 u16 hor_sync_end; 1082 u16 ver_total; 1083 u16 ver_addr; 1084 u16 ver_blank_start; 1085 u16 ver_blank_end; 1086 u16 ver_sync_start; 1087 u16 ver_sync_end; 1088 }; 1089 1090 struct crt_mode_table { 1091 int refresh_rate; 1092 unsigned long clk; 1093 int h_sync_polarity; 1094 int v_sync_polarity; 1095 struct display_timing crtc; 1096 }; 1097 1098 struct io_reg { 1099 int port; 1100 u8 index; 1101 u8 mask; 1102 u8 value; 1103 }; 1104 1105 #endif /* __SHARE_H__ */ 1106