1 /*************************************************************************** 2 * 3 * Copyright (C) 2007,2008 SMSC 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation; either version 2 8 * of the License, or (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 18 * 19 *************************************************************************** 20 */ 21 22 #ifndef _SMSC9420_H 23 #define _SMSC9420_H 24 25 #define TX_RING_SIZE (32) 26 #define RX_RING_SIZE (128) 27 28 /* interrupt deassertion in multiples of 10us */ 29 #define INT_DEAS_TIME (50) 30 31 #define NAPI_WEIGHT (64) 32 #define SMSC_BAR (3) 33 34 #ifdef __BIG_ENDIAN 35 /* Register set is duplicated for BE at an offset of 0x200 */ 36 #define LAN9420_CPSR_ENDIAN_OFFSET (0x200) 37 #else 38 #define LAN9420_CPSR_ENDIAN_OFFSET (0) 39 #endif 40 41 #define PCI_VENDOR_ID_9420 (0x1055) 42 #define PCI_DEVICE_ID_9420 (0xE420) 43 44 #define LAN_REGISTER_EXTENT (0x400) 45 46 #define SMSC9420_EEPROM_SIZE ((u32)11) 47 #define SMSC9420_EEPROM_MAGIC (0x9420) 48 49 #define PKT_BUF_SZ (VLAN_ETH_FRAME_LEN + NET_IP_ALIGN + 4) 50 51 /***********************************************/ 52 /* DMA Controller Control and Status Registers */ 53 /***********************************************/ 54 #define BUS_MODE (0x00) 55 #define BUS_MODE_SWR_ (BIT(0)) 56 #define BUS_MODE_DMA_BURST_LENGTH_1 (BIT(8)) 57 #define BUS_MODE_DMA_BURST_LENGTH_2 (BIT(9)) 58 #define BUS_MODE_DMA_BURST_LENGTH_4 (BIT(10)) 59 #define BUS_MODE_DMA_BURST_LENGTH_8 (BIT(11)) 60 #define BUS_MODE_DMA_BURST_LENGTH_16 (BIT(12)) 61 #define BUS_MODE_DMA_BURST_LENGTH_32 (BIT(13)) 62 #define BUS_MODE_DBO_ (BIT(20)) 63 64 #define TX_POLL_DEMAND (0x04) 65 66 #define RX_POLL_DEMAND (0x08) 67 68 #define RX_BASE_ADDR (0x0C) 69 70 #define TX_BASE_ADDR (0x10) 71 72 #define DMAC_STATUS (0x14) 73 #define DMAC_STS_TS_ (7 << 20) 74 #define DMAC_STS_RS_ (7 << 17) 75 #define DMAC_STS_NIS_ (BIT(16)) 76 #define DMAC_STS_AIS_ (BIT(15)) 77 #define DMAC_STS_RWT_ (BIT(9)) 78 #define DMAC_STS_RXPS_ (BIT(8)) 79 #define DMAC_STS_RXBU_ (BIT(7)) 80 #define DMAC_STS_RX_ (BIT(6)) 81 #define DMAC_STS_TXUNF_ (BIT(5)) 82 #define DMAC_STS_TXBU_ (BIT(2)) 83 #define DMAC_STS_TXPS_ (BIT(1)) 84 #define DMAC_STS_TX_ (BIT(0)) 85 86 #define DMAC_CONTROL (0x18) 87 #define DMAC_CONTROL_TTM_ (BIT(22)) 88 #define DMAC_CONTROL_SF_ (BIT(21)) 89 #define DMAC_CONTROL_ST_ (BIT(13)) 90 #define DMAC_CONTROL_OSF_ (BIT(2)) 91 #define DMAC_CONTROL_SR_ (BIT(1)) 92 93 #define DMAC_INTR_ENA (0x1C) 94 #define DMAC_INTR_ENA_NIS_ (BIT(16)) 95 #define DMAC_INTR_ENA_AIS_ (BIT(15)) 96 #define DMAC_INTR_ENA_RWT_ (BIT(9)) 97 #define DMAC_INTR_ENA_RXPS_ (BIT(8)) 98 #define DMAC_INTR_ENA_RXBU_ (BIT(7)) 99 #define DMAC_INTR_ENA_RX_ (BIT(6)) 100 #define DMAC_INTR_ENA_TXBU_ (BIT(2)) 101 #define DMAC_INTR_ENA_TXPS_ (BIT(1)) 102 #define DMAC_INTR_ENA_TX_ (BIT(0)) 103 104 #define MISS_FRAME_CNTR (0x20) 105 106 #define TX_BUFF_ADDR (0x50) 107 108 #define RX_BUFF_ADDR (0x54) 109 110 /* Transmit Descriptor Bit Defs */ 111 #define TDES0_OWN_ (0x80000000) 112 #define TDES0_ERROR_SUMMARY_ (0x00008000) 113 #define TDES0_LOSS_OF_CARRIER_ (0x00000800) 114 #define TDES0_NO_CARRIER_ (0x00000400) 115 #define TDES0_LATE_COLLISION_ (0x00000200) 116 #define TDES0_EXCESSIVE_COLLISIONS_ (0x00000100) 117 #define TDES0_HEARTBEAT_FAIL_ (0x00000080) 118 #define TDES0_COLLISION_COUNT_MASK_ (0x00000078) 119 #define TDES0_COLLISION_COUNT_SHFT_ (3) 120 #define TDES0_EXCESSIVE_DEFERRAL_ (0x00000004) 121 #define TDES0_DEFERRED_ (0x00000001) 122 123 #define TDES1_IC_ 0x80000000 124 #define TDES1_LS_ 0x40000000 125 #define TDES1_FS_ 0x20000000 126 #define TDES1_TXCSEN_ 0x08000000 127 #define TDES1_TER_ (BIT(25)) 128 #define TDES1_TCH_ 0x01000000 129 130 /* Receive Descriptor 0 Bit Defs */ 131 #define RDES0_OWN_ (0x80000000) 132 #define RDES0_FRAME_LENGTH_MASK_ (0x07FF0000) 133 #define RDES0_FRAME_LENGTH_SHFT_ (16) 134 #define RDES0_ERROR_SUMMARY_ (0x00008000) 135 #define RDES0_DESCRIPTOR_ERROR_ (0x00004000) 136 #define RDES0_LENGTH_ERROR_ (0x00001000) 137 #define RDES0_RUNT_FRAME_ (0x00000800) 138 #define RDES0_MULTICAST_FRAME_ (0x00000400) 139 #define RDES0_FIRST_DESCRIPTOR_ (0x00000200) 140 #define RDES0_LAST_DESCRIPTOR_ (0x00000100) 141 #define RDES0_FRAME_TOO_LONG_ (0x00000080) 142 #define RDES0_COLLISION_SEEN_ (0x00000040) 143 #define RDES0_FRAME_TYPE_ (0x00000020) 144 #define RDES0_WATCHDOG_TIMEOUT_ (0x00000010) 145 #define RDES0_MII_ERROR_ (0x00000008) 146 #define RDES0_DRIBBLING_BIT_ (0x00000004) 147 #define RDES0_CRC_ERROR_ (0x00000002) 148 149 /* Receive Descriptor 1 Bit Defs */ 150 #define RDES1_RER_ (0x02000000) 151 152 /***********************************************/ 153 /* MAC Control and Status Registers */ 154 /***********************************************/ 155 #define MAC_CR (0x80) 156 #define MAC_CR_RXALL_ (0x80000000) 157 #define MAC_CR_DIS_RXOWN_ (0x00800000) 158 #define MAC_CR_LOOPBK_ (0x00200000) 159 #define MAC_CR_FDPX_ (0x00100000) 160 #define MAC_CR_MCPAS_ (0x00080000) 161 #define MAC_CR_PRMS_ (0x00040000) 162 #define MAC_CR_INVFILT_ (0x00020000) 163 #define MAC_CR_PASSBAD_ (0x00010000) 164 #define MAC_CR_HFILT_ (0x00008000) 165 #define MAC_CR_HPFILT_ (0x00002000) 166 #define MAC_CR_LCOLL_ (0x00001000) 167 #define MAC_CR_DIS_BCAST_ (0x00000800) 168 #define MAC_CR_DIS_RTRY_ (0x00000400) 169 #define MAC_CR_PADSTR_ (0x00000100) 170 #define MAC_CR_BOLMT_MSK (0x000000C0) 171 #define MAC_CR_MFCHK_ (0x00000020) 172 #define MAC_CR_TXEN_ (0x00000008) 173 #define MAC_CR_RXEN_ (0x00000004) 174 175 #define ADDRH (0x84) 176 177 #define ADDRL (0x88) 178 179 #define HASHH (0x8C) 180 181 #define HASHL (0x90) 182 183 #define MII_ACCESS (0x94) 184 #define MII_ACCESS_MII_BUSY_ (0x00000001) 185 #define MII_ACCESS_MII_WRITE_ (0x00000002) 186 #define MII_ACCESS_MII_READ_ (0x00000000) 187 #define MII_ACCESS_INDX_MSK_ (0x000007C0) 188 #define MII_ACCESS_PHYADDR_MSK_ (0x0000F8C0) 189 #define MII_ACCESS_INDX_SHFT_CNT (6) 190 #define MII_ACCESS_PHYADDR_SHFT_CNT (11) 191 192 #define MII_DATA (0x98) 193 194 #define FLOW (0x9C) 195 196 #define VLAN1 (0xA0) 197 198 #define VLAN2 (0xA4) 199 200 #define WUFF (0xA8) 201 202 #define WUCSR (0xAC) 203 204 #define COE_CR (0xB0) 205 #define TX_COE_EN (0x00010000) 206 #define RX_COE_MODE (0x00000002) 207 #define RX_COE_EN (0x00000001) 208 209 /***********************************************/ 210 /* System Control and Status Registers */ 211 /***********************************************/ 212 #define ID_REV (0xC0) 213 214 #define INT_CTL (0xC4) 215 #define INT_CTL_SW_INT_EN_ (0x00008000) 216 #define INT_CTL_SBERR_INT_EN_ (1 << 12) 217 #define INT_CTL_MBERR_INT_EN_ (1 << 13) 218 #define INT_CTL_GPT_INT_EN_ (0x00000008) 219 #define INT_CTL_PHY_INT_EN_ (0x00000004) 220 #define INT_CTL_WAKE_INT_EN_ (0x00000002) 221 222 #define INT_STAT (0xC8) 223 #define INT_STAT_SW_INT_ (1 << 15) 224 #define INT_STAT_MBERR_INT_ (1 << 13) 225 #define INT_STAT_SBERR_INT_ (1 << 12) 226 #define INT_STAT_GPT_INT_ (1 << 3) 227 #define INT_STAT_PHY_INT_ (0x00000004) 228 #define INT_STAT_WAKE_INT_ (0x00000002) 229 #define INT_STAT_DMAC_INT_ (0x00000001) 230 231 #define INT_CFG (0xCC) 232 #define INT_CFG_IRQ_INT_ (0x00080000) 233 #define INT_CFG_IRQ_EN_ (0x00040000) 234 #define INT_CFG_INT_DEAS_CLR_ (0x00000200) 235 #define INT_CFG_INT_DEAS_MASK (0x000000FF) 236 237 #define GPIO_CFG (0xD0) 238 #define GPIO_CFG_LED_3_ (0x40000000) 239 #define GPIO_CFG_LED_2_ (0x20000000) 240 #define GPIO_CFG_LED_1_ (0x10000000) 241 #define GPIO_CFG_EEPR_EN_ (0x00700000) 242 243 #define GPT_CFG (0xD4) 244 #define GPT_CFG_TIMER_EN_ (0x20000000) 245 246 #define GPT_CNT (0xD8) 247 248 #define BUS_CFG (0xDC) 249 #define BUS_CFG_RXTXWEIGHT_1_1 (0 << 25) 250 #define BUS_CFG_RXTXWEIGHT_2_1 (1 << 25) 251 #define BUS_CFG_RXTXWEIGHT_3_1 (2 << 25) 252 #define BUS_CFG_RXTXWEIGHT_4_1 (3 << 25) 253 254 #define PMT_CTRL (0xE0) 255 256 #define FREE_RUN (0xF4) 257 258 #define E2P_CMD (0xF8) 259 #define E2P_CMD_EPC_BUSY_ (0x80000000) 260 #define E2P_CMD_EPC_CMD_ (0x70000000) 261 #define E2P_CMD_EPC_CMD_READ_ (0x00000000) 262 #define E2P_CMD_EPC_CMD_EWDS_ (0x10000000) 263 #define E2P_CMD_EPC_CMD_EWEN_ (0x20000000) 264 #define E2P_CMD_EPC_CMD_WRITE_ (0x30000000) 265 #define E2P_CMD_EPC_CMD_WRAL_ (0x40000000) 266 #define E2P_CMD_EPC_CMD_ERASE_ (0x50000000) 267 #define E2P_CMD_EPC_CMD_ERAL_ (0x60000000) 268 #define E2P_CMD_EPC_CMD_RELOAD_ (0x70000000) 269 #define E2P_CMD_EPC_TIMEOUT_ (0x00000200) 270 #define E2P_CMD_MAC_ADDR_LOADED_ (0x00000100) 271 #define E2P_CMD_EPC_ADDR_ (0x000000FF) 272 273 #define E2P_DATA (0xFC) 274 #define E2P_DATA_EEPROM_DATA_ (0x000000FF) 275 276 #endif /* _SMSC9420_H */ 277