1 /* linux/arch/arm/plat-s3c64xx/include/mach/irqs.h 2 * 3 * Copyright 2008 Openmoko, Inc. 4 * Copyright 2008 Simtec Electronics 5 * Ben Dooks <ben@simtec.co.uk> 6 * http://armlinux.simtec.co.uk/ 7 * 8 * S3C64XX - Common IRQ support 9 */ 10 11 #ifndef __ASM_PLAT_S3C64XX_IRQS_H 12 #define __ASM_PLAT_S3C64XX_IRQS_H __FILE__ 13 14 /* we keep the first set of CPU IRQs out of the range of 15 * the ISA space, so that the PC104 has them to itself 16 * and we don't end up having to do horrible things to the 17 * standard ISA drivers.... 18 * 19 * note, since we're using the VICs, our start must be a 20 * mulitple of 32 to allow the common code to work 21 */ 22 23 #define S3C_IRQ_OFFSET (32) 24 25 #define S3C_IRQ(x) ((x) + S3C_IRQ_OFFSET) 26 27 #define S3C_VIC0_BASE S3C_IRQ(0) 28 #define S3C_VIC1_BASE S3C_IRQ(32) 29 30 /* UART interrupts, each UART has 4 intterupts per channel so 31 * use the space between the ISA and S3C main interrupts. Note, these 32 * are not in the same order as the S3C24XX series! */ 33 34 #define IRQ_S3CUART_BASE0 (16) 35 #define IRQ_S3CUART_BASE1 (20) 36 #define IRQ_S3CUART_BASE2 (24) 37 #define IRQ_S3CUART_BASE3 (28) 38 39 #define UART_IRQ_RXD (0) 40 #define UART_IRQ_ERR (1) 41 #define UART_IRQ_TXD (2) 42 #define UART_IRQ_MODEM (3) 43 44 #define IRQ_S3CUART_RX0 (IRQ_S3CUART_BASE0 + UART_IRQ_RXD) 45 #define IRQ_S3CUART_TX0 (IRQ_S3CUART_BASE0 + UART_IRQ_TXD) 46 #define IRQ_S3CUART_ERR0 (IRQ_S3CUART_BASE0 + UART_IRQ_ERR) 47 48 #define IRQ_S3CUART_RX1 (IRQ_S3CUART_BASE1 + UART_IRQ_RXD) 49 #define IRQ_S3CUART_TX1 (IRQ_S3CUART_BASE1 + UART_IRQ_TXD) 50 #define IRQ_S3CUART_ERR1 (IRQ_S3CUART_BASE1 + UART_IRQ_ERR) 51 52 #define IRQ_S3CUART_RX2 (IRQ_S3CUART_BASE2 + UART_IRQ_RXD) 53 #define IRQ_S3CUART_TX2 (IRQ_S3CUART_BASE2 + UART_IRQ_TXD) 54 #define IRQ_S3CUART_ERR2 (IRQ_S3CUART_BASE2 + UART_IRQ_ERR) 55 56 #define IRQ_S3CUART_RX3 (IRQ_S3CUART_BASE3 + UART_IRQ_RXD) 57 #define IRQ_S3CUART_TX3 (IRQ_S3CUART_BASE3 + UART_IRQ_TXD) 58 #define IRQ_S3CUART_ERR3 (IRQ_S3CUART_BASE3 + UART_IRQ_ERR) 59 60 /* VIC based IRQs */ 61 62 #define S3C64XX_IRQ_VIC0(x) (S3C_VIC0_BASE + (x)) 63 #define S3C64XX_IRQ_VIC1(x) (S3C_VIC1_BASE + (x)) 64 65 /* VIC0 */ 66 67 #define IRQ_EINT0_3 S3C64XX_IRQ_VIC0(0) 68 #define IRQ_EINT4_11 S3C64XX_IRQ_VIC0(1) 69 #define IRQ_RTC_TIC S3C64XX_IRQ_VIC0(2) 70 #define IRQ_CAMIF_C S3C64XX_IRQ_VIC0(3) 71 #define IRQ_CAMIF_P S3C64XX_IRQ_VIC0(4) 72 #define IRQ_CAMIF_MC S3C64XX_IRQ_VIC0(5) 73 #define IRQ_S3C6410_IIC1 S3C64XX_IRQ_VIC0(5) 74 #define IRQ_S3C6410_IIS S3C64XX_IRQ_VIC0(6) 75 #define IRQ_S3C6400_CAMIF_MP S3C64XX_IRQ_VIC0(6) 76 #define IRQ_CAMIF_WE_C S3C64XX_IRQ_VIC0(7) 77 #define IRQ_S3C6410_G3D S3C64XX_IRQ_VIC0(8) 78 #define IRQ_S3C6400_CAMIF_WE_P S3C64XX_IRQ_VIC0(8) 79 #define IRQ_POST0 S3C64XX_IRQ_VIC0(9) 80 #define IRQ_ROTATOR S3C64XX_IRQ_VIC0(10) 81 #define IRQ_2D S3C64XX_IRQ_VIC0(11) 82 #define IRQ_TVENC S3C64XX_IRQ_VIC0(12) 83 #define IRQ_SCALER S3C64XX_IRQ_VIC0(13) 84 #define IRQ_BATF S3C64XX_IRQ_VIC0(14) 85 #define IRQ_JPEG S3C64XX_IRQ_VIC0(15) 86 #define IRQ_MFC S3C64XX_IRQ_VIC0(16) 87 #define IRQ_SDMA0 S3C64XX_IRQ_VIC0(17) 88 #define IRQ_SDMA1 S3C64XX_IRQ_VIC0(18) 89 #define IRQ_ARM_DMAERR S3C64XX_IRQ_VIC0(19) 90 #define IRQ_ARM_DMA S3C64XX_IRQ_VIC0(20) 91 #define IRQ_ARM_DMAS S3C64XX_IRQ_VIC0(21) 92 #define IRQ_KEYPAD S3C64XX_IRQ_VIC0(22) 93 #define IRQ_TIMER0_VIC S3C64XX_IRQ_VIC0(23) 94 #define IRQ_TIMER1_VIC S3C64XX_IRQ_VIC0(24) 95 #define IRQ_TIMER2_VIC S3C64XX_IRQ_VIC0(25) 96 #define IRQ_WDT S3C64XX_IRQ_VIC0(26) 97 #define IRQ_TIMER3_VIC S3C64XX_IRQ_VIC0(27) 98 #define IRQ_TIMER4_VIC S3C64XX_IRQ_VIC0(28) 99 #define IRQ_LCD_FIFO S3C64XX_IRQ_VIC0(29) 100 #define IRQ_LCD_VSYNC S3C64XX_IRQ_VIC0(30) 101 #define IRQ_LCD_SYSTEM S3C64XX_IRQ_VIC0(31) 102 103 /* VIC1 */ 104 105 #define IRQ_EINT12_19 S3C64XX_IRQ_VIC1(0) 106 #define IRQ_EINT20_27 S3C64XX_IRQ_VIC1(1) 107 #define IRQ_PCM0 S3C64XX_IRQ_VIC1(2) 108 #define IRQ_PCM1 S3C64XX_IRQ_VIC1(3) 109 #define IRQ_AC97 S3C64XX_IRQ_VIC1(4) 110 #define IRQ_UART0 S3C64XX_IRQ_VIC1(5) 111 #define IRQ_UART1 S3C64XX_IRQ_VIC1(6) 112 #define IRQ_UART2 S3C64XX_IRQ_VIC1(7) 113 #define IRQ_UART3 S3C64XX_IRQ_VIC1(8) 114 #define IRQ_DMA0 S3C64XX_IRQ_VIC1(9) 115 #define IRQ_DMA1 S3C64XX_IRQ_VIC1(10) 116 #define IRQ_ONENAND0 S3C64XX_IRQ_VIC1(11) 117 #define IRQ_ONENAND1 S3C64XX_IRQ_VIC1(12) 118 #define IRQ_NFC S3C64XX_IRQ_VIC1(13) 119 #define IRQ_CFCON S3C64XX_IRQ_VIC1(14) 120 #define IRQ_USBH S3C64XX_IRQ_VIC1(15) 121 #define IRQ_SPI0 S3C64XX_IRQ_VIC1(16) 122 #define IRQ_SPI1 S3C64XX_IRQ_VIC1(17) 123 #define IRQ_IIC S3C64XX_IRQ_VIC1(18) 124 #define IRQ_HSItx S3C64XX_IRQ_VIC1(19) 125 #define IRQ_HSIrx S3C64XX_IRQ_VIC1(20) 126 #define IRQ_RESERVED S3C64XX_IRQ_VIC1(21) 127 #define IRQ_MSM S3C64XX_IRQ_VIC1(22) 128 #define IRQ_HOSTIF S3C64XX_IRQ_VIC1(23) 129 #define IRQ_HSMMC0 S3C64XX_IRQ_VIC1(24) 130 #define IRQ_HSMMC1 S3C64XX_IRQ_VIC1(25) 131 #define IRQ_HSMMC2 IRQ_SPI1 /* shared with SPI1 */ 132 #define IRQ_OTG S3C64XX_IRQ_VIC1(26) 133 #define IRQ_IRDA S3C64XX_IRQ_VIC1(27) 134 #define IRQ_RTC_ALARM S3C64XX_IRQ_VIC1(28) 135 #define IRQ_SEC S3C64XX_IRQ_VIC1(29) 136 #define IRQ_PENDN S3C64XX_IRQ_VIC1(30) 137 #define IRQ_TC IRQ_PENDN 138 #define IRQ_ADC S3C64XX_IRQ_VIC1(31) 139 140 #define S3C64XX_TIMER_IRQ(x) S3C_IRQ(64 + (x)) 141 142 #define IRQ_TIMER0 S3C64XX_TIMER_IRQ(0) 143 #define IRQ_TIMER1 S3C64XX_TIMER_IRQ(1) 144 #define IRQ_TIMER2 S3C64XX_TIMER_IRQ(2) 145 #define IRQ_TIMER3 S3C64XX_TIMER_IRQ(3) 146 #define IRQ_TIMER4 S3C64XX_TIMER_IRQ(4) 147 148 /* compatibility for device defines */ 149 150 #define IRQ_IIC1 IRQ_S3C6410_IIC1 151 152 /* Since the IRQ_EINT(x) are a linear mapping on current s3c64xx series 153 * we just defined them as an IRQ_EINT(x) macro from S3C_IRQ_EINT_BASE 154 * which we place after the pair of VICs. */ 155 156 #define S3C_IRQ_EINT_BASE S3C_IRQ(64+5) 157 158 #define S3C_EINT(x) ((x) + S3C_IRQ_EINT_BASE) 159 #define IRQ_EINT(x) S3C_EINT(x) 160 161 /* Next the external interrupt groups. These are similar to the IRQ_EINT(x) 162 * that they are sourced from the GPIO pins but with a different scheme for 163 * priority and source indication. 164 * 165 * The IRQ_EINT(x) can be thought of as 'group 0' of the available GPIO 166 * interrupts, but for historical reasons they are kept apart from these 167 * next interrupts. 168 * 169 * Use IRQ_EINT_GROUP(group, offset) to get the number for use in the 170 * machine specific support files. 171 */ 172 173 #define IRQ_EINT_GROUP1_NR (15) 174 #define IRQ_EINT_GROUP2_NR (8) 175 #define IRQ_EINT_GROUP3_NR (5) 176 #define IRQ_EINT_GROUP4_NR (14) 177 #define IRQ_EINT_GROUP5_NR (7) 178 #define IRQ_EINT_GROUP6_NR (10) 179 #define IRQ_EINT_GROUP7_NR (16) 180 #define IRQ_EINT_GROUP8_NR (15) 181 #define IRQ_EINT_GROUP9_NR (9) 182 183 #define IRQ_EINT_GROUP_BASE S3C_EINT(28) 184 #define IRQ_EINT_GROUP1_BASE (IRQ_EINT_GROUP_BASE + 0x00) 185 #define IRQ_EINT_GROUP2_BASE (IRQ_EINT_GROUP1_BASE + IRQ_EINT_GROUP1_NR) 186 #define IRQ_EINT_GROUP3_BASE (IRQ_EINT_GROUP2_BASE + IRQ_EINT_GROUP2_NR) 187 #define IRQ_EINT_GROUP4_BASE (IRQ_EINT_GROUP3_BASE + IRQ_EINT_GROUP3_NR) 188 #define IRQ_EINT_GROUP5_BASE (IRQ_EINT_GROUP4_BASE + IRQ_EINT_GROUP4_NR) 189 #define IRQ_EINT_GROUP6_BASE (IRQ_EINT_GROUP5_BASE + IRQ_EINT_GROUP5_NR) 190 #define IRQ_EINT_GROUP7_BASE (IRQ_EINT_GROUP6_BASE + IRQ_EINT_GROUP6_NR) 191 #define IRQ_EINT_GROUP8_BASE (IRQ_EINT_GROUP7_BASE + IRQ_EINT_GROUP7_NR) 192 #define IRQ_EINT_GROUP9_BASE (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR) 193 194 #define IRQ_EINT_GROUP(group, no) (IRQ_EINT_GROUP##group##_BASE + (no)) 195 196 /* Set the default NR_IRQS */ 197 198 #define NR_IRQS (IRQ_EINT_GROUP9_BASE + IRQ_EINT_GROUP9_NR + 1) 199 200 #endif /* __ASM_PLAT_S3C64XX_IRQS_H */ 201 202