1 #ifndef __MMU_H 2 #define __MMU_H 3 4 #include <linux/const.h> 5 #include <asm/page.h> 6 #include <asm/hypervisor.h> 7 8 #define CTX_NR_BITS 13 9 10 #define TAG_CONTEXT_BITS ((_AC(1,UL) << CTX_NR_BITS) - _AC(1,UL)) 11 12 /* UltraSPARC-III+ and later have a feature whereby you can 13 * select what page size the various Data-TLB instances in the 14 * chip. In order to gracefully support this, we put the version 15 * field in a spot outside of the areas of the context register 16 * where this parameter is specified. 17 */ 18 #define CTX_VERSION_SHIFT 22 19 #define CTX_VERSION_MASK ((~0UL) << CTX_VERSION_SHIFT) 20 21 #define CTX_PGSZ_8KB _AC(0x0,UL) 22 #define CTX_PGSZ_64KB _AC(0x1,UL) 23 #define CTX_PGSZ_512KB _AC(0x2,UL) 24 #define CTX_PGSZ_4MB _AC(0x3,UL) 25 #define CTX_PGSZ_BITS _AC(0x7,UL) 26 #define CTX_PGSZ0_NUC_SHIFT 61 27 #define CTX_PGSZ1_NUC_SHIFT 58 28 #define CTX_PGSZ0_SHIFT 16 29 #define CTX_PGSZ1_SHIFT 19 30 #define CTX_PGSZ_MASK ((CTX_PGSZ_BITS << CTX_PGSZ0_SHIFT) | \ 31 (CTX_PGSZ_BITS << CTX_PGSZ1_SHIFT)) 32 33 #if defined(CONFIG_SPARC64_PAGE_SIZE_8KB) 34 #define CTX_PGSZ_BASE CTX_PGSZ_8KB 35 #elif defined(CONFIG_SPARC64_PAGE_SIZE_64KB) 36 #define CTX_PGSZ_BASE CTX_PGSZ_64KB 37 #else 38 #error No page size specified in kernel configuration 39 #endif 40 41 #if defined(CONFIG_HUGETLB_PAGE_SIZE_4MB) 42 #define CTX_PGSZ_HUGE CTX_PGSZ_4MB 43 #elif defined(CONFIG_HUGETLB_PAGE_SIZE_512K) 44 #define CTX_PGSZ_HUGE CTX_PGSZ_512KB 45 #elif defined(CONFIG_HUGETLB_PAGE_SIZE_64K) 46 #define CTX_PGSZ_HUGE CTX_PGSZ_64KB 47 #endif 48 49 #define CTX_PGSZ_KERN CTX_PGSZ_4MB 50 51 /* Thus, when running on UltraSPARC-III+ and later, we use the following 52 * PRIMARY_CONTEXT register values for the kernel context. 53 */ 54 #define CTX_CHEETAH_PLUS_NUC \ 55 ((CTX_PGSZ_KERN << CTX_PGSZ0_NUC_SHIFT) | \ 56 (CTX_PGSZ_BASE << CTX_PGSZ1_NUC_SHIFT)) 57 58 #define CTX_CHEETAH_PLUS_CTX0 \ 59 ((CTX_PGSZ_KERN << CTX_PGSZ0_SHIFT) | \ 60 (CTX_PGSZ_BASE << CTX_PGSZ1_SHIFT)) 61 62 /* If you want "the TLB context number" use CTX_NR_MASK. If you 63 * want "the bits I program into the context registers" use 64 * CTX_HW_MASK. 65 */ 66 #define CTX_NR_MASK TAG_CONTEXT_BITS 67 #define CTX_HW_MASK (CTX_NR_MASK | CTX_PGSZ_MASK) 68 69 #define CTX_FIRST_VERSION ((_AC(1,UL) << CTX_VERSION_SHIFT) + _AC(1,UL)) 70 #define CTX_VALID(__ctx) \ 71 (!(((__ctx.sparc64_ctx_val) ^ tlb_context_cache) & CTX_VERSION_MASK)) 72 #define CTX_HWBITS(__ctx) ((__ctx.sparc64_ctx_val) & CTX_HW_MASK) 73 #define CTX_NRBITS(__ctx) ((__ctx.sparc64_ctx_val) & CTX_NR_MASK) 74 75 #ifndef __ASSEMBLY__ 76 77 #define TSB_ENTRY_ALIGNMENT 16 78 79 struct tsb { 80 unsigned long tag; 81 unsigned long pte; 82 } __attribute__((aligned(TSB_ENTRY_ALIGNMENT))); 83 84 extern void __tsb_insert(unsigned long ent, unsigned long tag, unsigned long pte); 85 extern void tsb_flush(unsigned long ent, unsigned long tag); 86 extern void tsb_init(struct tsb *tsb, unsigned long size); 87 88 struct tsb_config { 89 struct tsb *tsb; 90 unsigned long tsb_rss_limit; 91 unsigned long tsb_nentries; 92 unsigned long tsb_reg_val; 93 unsigned long tsb_map_vaddr; 94 unsigned long tsb_map_pte; 95 }; 96 97 #define MM_TSB_BASE 0 98 99 #ifdef CONFIG_HUGETLB_PAGE 100 #define MM_TSB_HUGE 1 101 #define MM_NUM_TSBS 2 102 #else 103 #define MM_NUM_TSBS 1 104 #endif 105 106 typedef struct { 107 spinlock_t lock; 108 unsigned long sparc64_ctx_val; 109 unsigned long huge_pte_count; 110 struct tsb_config tsb_block[MM_NUM_TSBS]; 111 struct hv_tsb_descr tsb_descr[MM_NUM_TSBS]; 112 } mm_context_t; 113 114 #endif /* !__ASSEMBLY__ */ 115 116 #define TSB_CONFIG_TSB 0x00 117 #define TSB_CONFIG_RSS_LIMIT 0x08 118 #define TSB_CONFIG_NENTRIES 0x10 119 #define TSB_CONFIG_REG_VAL 0x18 120 #define TSB_CONFIG_MAP_VADDR 0x20 121 #define TSB_CONFIG_MAP_PTE 0x28 122 123 #endif /* __MMU_H */ 124