1 /* 2 * Contains the definition of registers common to all PowerPC variants. 3 * If a register definition has been changed in a different PowerPC 4 * variant, we will case it in #ifndef XXX ... #endif, and have the 5 * number used in the Programming Environments Manual For 32-Bit 6 * Implementations of the PowerPC Architecture (a.k.a. Green Book) here. 7 */ 8 9 #ifndef _ASM_POWERPC_REG_H 10 #define _ASM_POWERPC_REG_H 11 #ifdef __KERNEL__ 12 13 #include <linux/stringify.h> 14 #include <asm/cputable.h> 15 16 /* Pickup Book E specific registers. */ 17 #if defined(CONFIG_BOOKE) || defined(CONFIG_40x) 18 #include <asm/reg_booke.h> 19 #endif /* CONFIG_BOOKE || CONFIG_40x */ 20 21 #ifdef CONFIG_FSL_EMB_PERFMON 22 #include <asm/reg_fsl_emb.h> 23 #endif 24 25 #ifdef CONFIG_8xx 26 #include <asm/reg_8xx.h> 27 #endif /* CONFIG_8xx */ 28 29 #define MSR_SF_LG 63 /* Enable 64 bit mode */ 30 #define MSR_ISF_LG 61 /* Interrupt 64b mode valid on 630 */ 31 #define MSR_HV_LG 60 /* Hypervisor state */ 32 #define MSR_VEC_LG 25 /* Enable AltiVec */ 33 #define MSR_VSX_LG 23 /* Enable VSX */ 34 #define MSR_POW_LG 18 /* Enable Power Management */ 35 #define MSR_WE_LG 18 /* Wait State Enable */ 36 #define MSR_TGPR_LG 17 /* TLB Update registers in use */ 37 #define MSR_CE_LG 17 /* Critical Interrupt Enable */ 38 #define MSR_ILE_LG 16 /* Interrupt Little Endian */ 39 #define MSR_EE_LG 15 /* External Interrupt Enable */ 40 #define MSR_PR_LG 14 /* Problem State / Privilege Level */ 41 #define MSR_FP_LG 13 /* Floating Point enable */ 42 #define MSR_ME_LG 12 /* Machine Check Enable */ 43 #define MSR_FE0_LG 11 /* Floating Exception mode 0 */ 44 #define MSR_SE_LG 10 /* Single Step */ 45 #define MSR_BE_LG 9 /* Branch Trace */ 46 #define MSR_DE_LG 9 /* Debug Exception Enable */ 47 #define MSR_FE1_LG 8 /* Floating Exception mode 1 */ 48 #define MSR_IP_LG 6 /* Exception prefix 0x000/0xFFF */ 49 #define MSR_IR_LG 5 /* Instruction Relocate */ 50 #define MSR_DR_LG 4 /* Data Relocate */ 51 #define MSR_PE_LG 3 /* Protection Enable */ 52 #define MSR_PX_LG 2 /* Protection Exclusive Mode */ 53 #define MSR_PMM_LG 2 /* Performance monitor */ 54 #define MSR_RI_LG 1 /* Recoverable Exception */ 55 #define MSR_LE_LG 0 /* Little Endian */ 56 57 #ifdef __ASSEMBLY__ 58 #define __MASK(X) (1<<(X)) 59 #else 60 #define __MASK(X) (1UL<<(X)) 61 #endif 62 63 #ifdef CONFIG_PPC64 64 #define MSR_SF __MASK(MSR_SF_LG) /* Enable 64 bit mode */ 65 #define MSR_ISF __MASK(MSR_ISF_LG) /* Interrupt 64b mode valid on 630 */ 66 #define MSR_HV __MASK(MSR_HV_LG) /* Hypervisor state */ 67 #else 68 /* so tests for these bits fail on 32-bit */ 69 #define MSR_SF 0 70 #define MSR_ISF 0 71 #define MSR_HV 0 72 #endif 73 74 #define MSR_VEC __MASK(MSR_VEC_LG) /* Enable AltiVec */ 75 #define MSR_VSX __MASK(MSR_VSX_LG) /* Enable VSX */ 76 #define MSR_POW __MASK(MSR_POW_LG) /* Enable Power Management */ 77 #define MSR_WE __MASK(MSR_WE_LG) /* Wait State Enable */ 78 #define MSR_TGPR __MASK(MSR_TGPR_LG) /* TLB Update registers in use */ 79 #define MSR_CE __MASK(MSR_CE_LG) /* Critical Interrupt Enable */ 80 #define MSR_ILE __MASK(MSR_ILE_LG) /* Interrupt Little Endian */ 81 #define MSR_EE __MASK(MSR_EE_LG) /* External Interrupt Enable */ 82 #define MSR_PR __MASK(MSR_PR_LG) /* Problem State / Privilege Level */ 83 #define MSR_FP __MASK(MSR_FP_LG) /* Floating Point enable */ 84 #define MSR_ME __MASK(MSR_ME_LG) /* Machine Check Enable */ 85 #define MSR_FE0 __MASK(MSR_FE0_LG) /* Floating Exception mode 0 */ 86 #define MSR_SE __MASK(MSR_SE_LG) /* Single Step */ 87 #define MSR_BE __MASK(MSR_BE_LG) /* Branch Trace */ 88 #define MSR_DE __MASK(MSR_DE_LG) /* Debug Exception Enable */ 89 #define MSR_FE1 __MASK(MSR_FE1_LG) /* Floating Exception mode 1 */ 90 #define MSR_IP __MASK(MSR_IP_LG) /* Exception prefix 0x000/0xFFF */ 91 #define MSR_IR __MASK(MSR_IR_LG) /* Instruction Relocate */ 92 #define MSR_DR __MASK(MSR_DR_LG) /* Data Relocate */ 93 #define MSR_PE __MASK(MSR_PE_LG) /* Protection Enable */ 94 #define MSR_PX __MASK(MSR_PX_LG) /* Protection Exclusive Mode */ 95 #ifndef MSR_PMM 96 #define MSR_PMM __MASK(MSR_PMM_LG) /* Performance monitor */ 97 #endif 98 #define MSR_RI __MASK(MSR_RI_LG) /* Recoverable Exception */ 99 #define MSR_LE __MASK(MSR_LE_LG) /* Little Endian */ 100 101 #ifdef CONFIG_PPC64 102 #define MSR_ MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_ISF |MSR_HV 103 #define MSR_KERNEL MSR_ | MSR_SF 104 105 #define MSR_USER32 MSR_ | MSR_PR | MSR_EE 106 #define MSR_USER64 MSR_USER32 | MSR_SF 107 108 #else /* 32-bit */ 109 /* Default MSR for kernel mode. */ 110 #ifndef MSR_KERNEL /* reg_booke.h also defines this */ 111 #define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR) 112 #endif 113 114 #define MSR_USER (MSR_KERNEL|MSR_PR|MSR_EE) 115 #endif 116 117 /* Floating Point Status and Control Register (FPSCR) Fields */ 118 #define FPSCR_FX 0x80000000 /* FPU exception summary */ 119 #define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */ 120 #define FPSCR_VX 0x20000000 /* Invalid operation summary */ 121 #define FPSCR_OX 0x10000000 /* Overflow exception summary */ 122 #define FPSCR_UX 0x08000000 /* Underflow exception summary */ 123 #define FPSCR_ZX 0x04000000 /* Zero-divide exception summary */ 124 #define FPSCR_XX 0x02000000 /* Inexact exception summary */ 125 #define FPSCR_VXSNAN 0x01000000 /* Invalid op for SNaN */ 126 #define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */ 127 #define FPSCR_VXIDI 0x00400000 /* Invalid op for Inv / Inv */ 128 #define FPSCR_VXZDZ 0x00200000 /* Invalid op for Zero / Zero */ 129 #define FPSCR_VXIMZ 0x00100000 /* Invalid op for Inv * Zero */ 130 #define FPSCR_VXVC 0x00080000 /* Invalid op for Compare */ 131 #define FPSCR_FR 0x00040000 /* Fraction rounded */ 132 #define FPSCR_FI 0x00020000 /* Fraction inexact */ 133 #define FPSCR_FPRF 0x0001f000 /* FPU Result Flags */ 134 #define FPSCR_FPCC 0x0000f000 /* FPU Condition Codes */ 135 #define FPSCR_VXSOFT 0x00000400 /* Invalid op for software request */ 136 #define FPSCR_VXSQRT 0x00000200 /* Invalid op for square root */ 137 #define FPSCR_VXCVI 0x00000100 /* Invalid op for integer convert */ 138 #define FPSCR_VE 0x00000080 /* Invalid op exception enable */ 139 #define FPSCR_OE 0x00000040 /* IEEE overflow exception enable */ 140 #define FPSCR_UE 0x00000020 /* IEEE underflow exception enable */ 141 #define FPSCR_ZE 0x00000010 /* IEEE zero divide exception enable */ 142 #define FPSCR_XE 0x00000008 /* FP inexact exception enable */ 143 #define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */ 144 #define FPSCR_RN 0x00000003 /* FPU rounding control */ 145 146 /* Special Purpose Registers (SPRNs)*/ 147 #define SPRN_CTR 0x009 /* Count Register */ 148 #define SPRN_DSCR 0x11 149 #define SPRN_CTRLF 0x088 150 #define SPRN_CTRLT 0x098 151 #define CTRL_CT 0xc0000000 /* current thread */ 152 #define CTRL_CT0 0x80000000 /* thread 0 */ 153 #define CTRL_CT1 0x40000000 /* thread 1 */ 154 #define CTRL_TE 0x00c00000 /* thread enable */ 155 #define CTRL_RUNLATCH 0x1 156 #define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */ 157 #define DABR_TRANSLATION (1UL << 2) 158 #define SPRN_DABR2 0x13D /* e300 */ 159 #define SPRN_DABRX 0x3F7 /* Data Address Breakpoint Register Extension */ 160 #define DABRX_USER (1UL << 0) 161 #define DABRX_KERNEL (1UL << 1) 162 #define SPRN_DAR 0x013 /* Data Address Register */ 163 #define SPRN_DBCR 0x136 /* e300 Data Breakpoint Control Reg */ 164 #define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */ 165 #define DSISR_NOHPTE 0x40000000 /* no translation found */ 166 #define DSISR_PROTFAULT 0x08000000 /* protection fault */ 167 #define DSISR_ISSTORE 0x02000000 /* access was a store */ 168 #define DSISR_DABRMATCH 0x00400000 /* hit data breakpoint */ 169 #define DSISR_NOSEGMENT 0x00200000 /* STAB/SLB miss */ 170 #define SPRN_TBRL 0x10C /* Time Base Read Lower Register (user, R/O) */ 171 #define SPRN_TBRU 0x10D /* Time Base Read Upper Register (user, R/O) */ 172 #define SPRN_TBWL 0x11C /* Time Base Lower Register (super, R/W) */ 173 #define SPRN_TBWU 0x11D /* Time Base Upper Register (super, R/W) */ 174 #define SPRN_SPURR 0x134 /* Scaled PURR */ 175 #define SPRN_HIOR 0x137 /* 970 Hypervisor interrupt offset */ 176 #define SPRN_LPCR 0x13E /* LPAR Control Register */ 177 #define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */ 178 #define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */ 179 #define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */ 180 #define SPRN_DBAT1U 0x21A /* Data BAT 1 Upper Register */ 181 #define SPRN_DBAT2L 0x21D /* Data BAT 2 Lower Register */ 182 #define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */ 183 #define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */ 184 #define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */ 185 #define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */ 186 #define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */ 187 #define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */ 188 #define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */ 189 #define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */ 190 #define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */ 191 #define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */ 192 #define SPRN_DBAT7U 0x23E /* Data BAT 7 Upper Register */ 193 194 #define SPRN_DEC 0x016 /* Decrement Register */ 195 #define SPRN_DER 0x095 /* Debug Enable Regsiter */ 196 #define DER_RSTE 0x40000000 /* Reset Interrupt */ 197 #define DER_CHSTPE 0x20000000 /* Check Stop */ 198 #define DER_MCIE 0x10000000 /* Machine Check Interrupt */ 199 #define DER_EXTIE 0x02000000 /* External Interrupt */ 200 #define DER_ALIE 0x01000000 /* Alignment Interrupt */ 201 #define DER_PRIE 0x00800000 /* Program Interrupt */ 202 #define DER_FPUVIE 0x00400000 /* FP Unavailable Interrupt */ 203 #define DER_DECIE 0x00200000 /* Decrementer Interrupt */ 204 #define DER_SYSIE 0x00040000 /* System Call Interrupt */ 205 #define DER_TRE 0x00020000 /* Trace Interrupt */ 206 #define DER_SEIE 0x00004000 /* FP SW Emulation Interrupt */ 207 #define DER_ITLBMSE 0x00002000 /* Imp. Spec. Instruction TLB Miss */ 208 #define DER_ITLBERE 0x00001000 /* Imp. Spec. Instruction TLB Error */ 209 #define DER_DTLBMSE 0x00000800 /* Imp. Spec. Data TLB Miss */ 210 #define DER_DTLBERE 0x00000400 /* Imp. Spec. Data TLB Error */ 211 #define DER_LBRKE 0x00000008 /* Load/Store Breakpoint Interrupt */ 212 #define DER_IBRKE 0x00000004 /* Instruction Breakpoint Interrupt */ 213 #define DER_EBRKE 0x00000002 /* External Breakpoint Interrupt */ 214 #define DER_DPIE 0x00000001 /* Dev. Port Nonmaskable Request */ 215 #define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */ 216 #define SPRN_EAR 0x11A /* External Address Register */ 217 #define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */ 218 #define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */ 219 #define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */ 220 #define HID0_EMCP (1<<31) /* Enable Machine Check pin */ 221 #define HID0_EBA (1<<29) /* Enable Bus Address Parity */ 222 #define HID0_EBD (1<<28) /* Enable Bus Data Parity */ 223 #define HID0_SBCLK (1<<27) 224 #define HID0_EICE (1<<26) 225 #define HID0_TBEN (1<<26) /* Timebase enable - 745x */ 226 #define HID0_ECLK (1<<25) 227 #define HID0_PAR (1<<24) 228 #define HID0_STEN (1<<24) /* Software table search enable - 745x */ 229 #define HID0_HIGH_BAT (1<<23) /* Enable high BATs - 7455 */ 230 #define HID0_DOZE (1<<23) 231 #define HID0_NAP (1<<22) 232 #define HID0_SLEEP (1<<21) 233 #define HID0_DPM (1<<20) 234 #define HID0_BHTCLR (1<<18) /* Clear branch history table - 7450 */ 235 #define HID0_XAEN (1<<17) /* Extended addressing enable - 7450 */ 236 #define HID0_NHR (1<<16) /* Not hard reset (software bit-7450)*/ 237 #define HID0_ICE (1<<15) /* Instruction Cache Enable */ 238 #define HID0_DCE (1<<14) /* Data Cache Enable */ 239 #define HID0_ILOCK (1<<13) /* Instruction Cache Lock */ 240 #define HID0_DLOCK (1<<12) /* Data Cache Lock */ 241 #define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */ 242 #define HID0_DCI (1<<10) /* Data Cache Invalidate */ 243 #define HID0_SPD (1<<9) /* Speculative disable */ 244 #define HID0_DAPUEN (1<<8) /* Debug APU enable */ 245 #define HID0_SGE (1<<7) /* Store Gathering Enable */ 246 #define HID0_SIED (1<<7) /* Serial Instr. Execution [Disable] */ 247 #define HID0_DCFA (1<<6) /* Data Cache Flush Assist */ 248 #define HID0_LRSTK (1<<4) /* Link register stack - 745x */ 249 #define HID0_BTIC (1<<5) /* Branch Target Instr Cache Enable */ 250 #define HID0_ABE (1<<3) /* Address Broadcast Enable */ 251 #define HID0_FOLD (1<<3) /* Branch Folding enable - 745x */ 252 #define HID0_BHTE (1<<2) /* Branch History Table Enable */ 253 #define HID0_BTCD (1<<1) /* Branch target cache disable */ 254 #define HID0_NOPDST (1<<1) /* No-op dst, dstt, etc. instr. */ 255 #define HID0_NOPTI (1<<0) /* No-op dcbt and dcbst instr. */ 256 257 #define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */ 258 #define HID1_EMCP (1<<31) /* 7450 Machine Check Pin Enable */ 259 #define HID1_DFS (1<<22) /* 7447A Dynamic Frequency Scaling */ 260 #define HID1_PC0 (1<<16) /* 7450 PLL_CFG[0] */ 261 #define HID1_PC1 (1<<15) /* 7450 PLL_CFG[1] */ 262 #define HID1_PC2 (1<<14) /* 7450 PLL_CFG[2] */ 263 #define HID1_PC3 (1<<13) /* 7450 PLL_CFG[3] */ 264 #define HID1_SYNCBE (1<<11) /* 7450 ABE for sync, eieio */ 265 #define HID1_ABE (1<<10) /* 7450 Address Broadcast Enable */ 266 #define HID1_PS (1<<16) /* 750FX PLL selection */ 267 #define SPRN_HID2 0x3F8 /* Hardware Implementation Register 2 */ 268 #define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */ 269 #define SPRN_IABR2 0x3FA /* 83xx */ 270 #define SPRN_IBCR 0x135 /* 83xx Insn Breakpoint Control Reg */ 271 #define SPRN_HID4 0x3F4 /* 970 HID4 */ 272 #define SPRN_HID5 0x3F6 /* 970 HID5 */ 273 #define SPRN_HID6 0x3F9 /* BE HID 6 */ 274 #define HID6_LB (0x0F<<12) /* Concurrent Large Page Modes */ 275 #define HID6_DLP (1<<20) /* Disable all large page modes (4K only) */ 276 #define SPRN_TSC_CELL 0x399 /* Thread switch control on Cell */ 277 #define TSC_CELL_DEC_ENABLE_0 0x400000 /* Decrementer Interrupt */ 278 #define TSC_CELL_DEC_ENABLE_1 0x200000 /* Decrementer Interrupt */ 279 #define TSC_CELL_EE_ENABLE 0x100000 /* External Interrupt */ 280 #define TSC_CELL_EE_BOOST 0x080000 /* External Interrupt Boost */ 281 #define SPRN_TSC 0x3FD /* Thread switch control on others */ 282 #define SPRN_TST 0x3FC /* Thread switch timeout on others */ 283 #if !defined(SPRN_IAC1) && !defined(SPRN_IAC2) 284 #define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */ 285 #define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */ 286 #endif 287 #define SPRN_IBAT0L 0x211 /* Instruction BAT 0 Lower Register */ 288 #define SPRN_IBAT0U 0x210 /* Instruction BAT 0 Upper Register */ 289 #define SPRN_IBAT1L 0x213 /* Instruction BAT 1 Lower Register */ 290 #define SPRN_IBAT1U 0x212 /* Instruction BAT 1 Upper Register */ 291 #define SPRN_IBAT2L 0x215 /* Instruction BAT 2 Lower Register */ 292 #define SPRN_IBAT2U 0x214 /* Instruction BAT 2 Upper Register */ 293 #define SPRN_IBAT3L 0x217 /* Instruction BAT 3 Lower Register */ 294 #define SPRN_IBAT3U 0x216 /* Instruction BAT 3 Upper Register */ 295 #define SPRN_IBAT4L 0x231 /* Instruction BAT 4 Lower Register */ 296 #define SPRN_IBAT4U 0x230 /* Instruction BAT 4 Upper Register */ 297 #define SPRN_IBAT5L 0x233 /* Instruction BAT 5 Lower Register */ 298 #define SPRN_IBAT5U 0x232 /* Instruction BAT 5 Upper Register */ 299 #define SPRN_IBAT6L 0x235 /* Instruction BAT 6 Lower Register */ 300 #define SPRN_IBAT6U 0x234 /* Instruction BAT 6 Upper Register */ 301 #define SPRN_IBAT7L 0x237 /* Instruction BAT 7 Lower Register */ 302 #define SPRN_IBAT7U 0x236 /* Instruction BAT 7 Upper Register */ 303 #define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */ 304 #define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */ 305 #define SPRN_ICTRL 0x3F3 /* 1011 7450 icache and interrupt ctrl */ 306 #define ICTRL_EICE 0x08000000 /* enable icache parity errs */ 307 #define ICTRL_EDC 0x04000000 /* enable dcache parity errs */ 308 #define ICTRL_EICP 0x00000100 /* enable icache par. check */ 309 #define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */ 310 #define SPRN_IMMR 0x27E /* Internal Memory Map Register */ 311 #define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */ 312 #define SPRN_L2CR2 0x3f8 313 #define L2CR_L2E 0x80000000 /* L2 enable */ 314 #define L2CR_L2PE 0x40000000 /* L2 parity enable */ 315 #define L2CR_L2SIZ_MASK 0x30000000 /* L2 size mask */ 316 #define L2CR_L2SIZ_256KB 0x10000000 /* L2 size 256KB */ 317 #define L2CR_L2SIZ_512KB 0x20000000 /* L2 size 512KB */ 318 #define L2CR_L2SIZ_1MB 0x30000000 /* L2 size 1MB */ 319 #define L2CR_L2CLK_MASK 0x0e000000 /* L2 clock mask */ 320 #define L2CR_L2CLK_DISABLED 0x00000000 /* L2 clock disabled */ 321 #define L2CR_L2CLK_DIV1 0x02000000 /* L2 clock / 1 */ 322 #define L2CR_L2CLK_DIV1_5 0x04000000 /* L2 clock / 1.5 */ 323 #define L2CR_L2CLK_DIV2 0x08000000 /* L2 clock / 2 */ 324 #define L2CR_L2CLK_DIV2_5 0x0a000000 /* L2 clock / 2.5 */ 325 #define L2CR_L2CLK_DIV3 0x0c000000 /* L2 clock / 3 */ 326 #define L2CR_L2RAM_MASK 0x01800000 /* L2 RAM type mask */ 327 #define L2CR_L2RAM_FLOW 0x00000000 /* L2 RAM flow through */ 328 #define L2CR_L2RAM_PIPE 0x01000000 /* L2 RAM pipelined */ 329 #define L2CR_L2RAM_PIPE_LW 0x01800000 /* L2 RAM pipelined latewr */ 330 #define L2CR_L2DO 0x00400000 /* L2 data only */ 331 #define L2CR_L2I 0x00200000 /* L2 global invalidate */ 332 #define L2CR_L2CTL 0x00100000 /* L2 RAM control */ 333 #define L2CR_L2WT 0x00080000 /* L2 write-through */ 334 #define L2CR_L2TS 0x00040000 /* L2 test support */ 335 #define L2CR_L2OH_MASK 0x00030000 /* L2 output hold mask */ 336 #define L2CR_L2OH_0_5 0x00000000 /* L2 output hold 0.5 ns */ 337 #define L2CR_L2OH_1_0 0x00010000 /* L2 output hold 1.0 ns */ 338 #define L2CR_L2SL 0x00008000 /* L2 DLL slow */ 339 #define L2CR_L2DF 0x00004000 /* L2 differential clock */ 340 #define L2CR_L2BYP 0x00002000 /* L2 DLL bypass */ 341 #define L2CR_L2IP 0x00000001 /* L2 GI in progress */ 342 #define L2CR_L2IO_745x 0x00100000 /* L2 instr. only (745x) */ 343 #define L2CR_L2DO_745x 0x00010000 /* L2 data only (745x) */ 344 #define L2CR_L2REP_745x 0x00001000 /* L2 repl. algorithm (745x) */ 345 #define L2CR_L2HWF_745x 0x00000800 /* L2 hardware flush (745x) */ 346 #define SPRN_L3CR 0x3FA /* Level 3 Cache Control Regsiter */ 347 #define L3CR_L3E 0x80000000 /* L3 enable */ 348 #define L3CR_L3PE 0x40000000 /* L3 data parity enable */ 349 #define L3CR_L3APE 0x20000000 /* L3 addr parity enable */ 350 #define L3CR_L3SIZ 0x10000000 /* L3 size */ 351 #define L3CR_L3CLKEN 0x08000000 /* L3 clock enable */ 352 #define L3CR_L3RES 0x04000000 /* L3 special reserved bit */ 353 #define L3CR_L3CLKDIV 0x03800000 /* L3 clock divisor */ 354 #define L3CR_L3IO 0x00400000 /* L3 instruction only */ 355 #define L3CR_L3SPO 0x00040000 /* L3 sample point override */ 356 #define L3CR_L3CKSP 0x00030000 /* L3 clock sample point */ 357 #define L3CR_L3PSP 0x0000e000 /* L3 P-clock sample point */ 358 #define L3CR_L3REP 0x00001000 /* L3 replacement algorithm */ 359 #define L3CR_L3HWF 0x00000800 /* L3 hardware flush */ 360 #define L3CR_L3I 0x00000400 /* L3 global invalidate */ 361 #define L3CR_L3RT 0x00000300 /* L3 SRAM type */ 362 #define L3CR_L3NIRCA 0x00000080 /* L3 non-integer ratio clock adj. */ 363 #define L3CR_L3DO 0x00000040 /* L3 data only mode */ 364 #define L3CR_PMEN 0x00000004 /* L3 private memory enable */ 365 #define L3CR_PMSIZ 0x00000001 /* L3 private memory size */ 366 367 #define SPRN_MSSCR0 0x3f6 /* Memory Subsystem Control Register 0 */ 368 #define SPRN_MSSSR0 0x3f7 /* Memory Subsystem Status Register 1 */ 369 #define SPRN_LDSTCR 0x3f8 /* Load/Store control register */ 370 #define SPRN_LDSTDB 0x3f4 /* */ 371 #define SPRN_LR 0x008 /* Link Register */ 372 #ifndef SPRN_PIR 373 #define SPRN_PIR 0x3FF /* Processor Identification Register */ 374 #endif 375 #define SPRN_PTEHI 0x3D5 /* 981 7450 PTE HI word (S/W TLB load) */ 376 #define SPRN_PTELO 0x3D6 /* 982 7450 PTE LO word (S/W TLB load) */ 377 #define SPRN_PURR 0x135 /* Processor Utilization of Resources Reg */ 378 #define SPRN_PVR 0x11F /* Processor Version Register */ 379 #define SPRN_RPA 0x3D6 /* Required Physical Address Register */ 380 #define SPRN_SDA 0x3BF /* Sampled Data Address Register */ 381 #define SPRN_SDR1 0x019 /* MMU Hash Base Register */ 382 #define SPRN_ASR 0x118 /* Address Space Register */ 383 #define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */ 384 #define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */ 385 #define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */ 386 #define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */ 387 #define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */ 388 #define SPRN_SPRG4 0x114 /* Special Purpose Register General 4 */ 389 #define SPRN_SPRG5 0x115 /* Special Purpose Register General 5 */ 390 #define SPRN_SPRG6 0x116 /* Special Purpose Register General 6 */ 391 #define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 */ 392 #define SPRN_SRR0 0x01A /* Save/Restore Register 0 */ 393 #define SPRN_SRR1 0x01B /* Save/Restore Register 1 */ 394 #define SRR1_WAKEMASK 0x00380000 /* reason for wakeup */ 395 #define SRR1_WAKERESET 0x00380000 /* System reset */ 396 #define SRR1_WAKESYSERR 0x00300000 /* System error */ 397 #define SRR1_WAKEEE 0x00200000 /* External interrupt */ 398 #define SRR1_WAKEMT 0x00280000 /* mtctrl */ 399 #define SRR1_WAKEDEC 0x00180000 /* Decrementer interrupt */ 400 #define SRR1_WAKETHERM 0x00100000 /* Thermal management interrupt */ 401 #define SPRN_HSRR0 0x13A /* Save/Restore Register 0 */ 402 #define SPRN_HSRR1 0x13B /* Save/Restore Register 1 */ 403 404 #define SPRN_TBCTL 0x35f /* PA6T Timebase control register */ 405 #define TBCTL_FREEZE 0x0000000000000000ull /* Freeze all tbs */ 406 #define TBCTL_RESTART 0x0000000100000000ull /* Restart all tbs */ 407 #define TBCTL_UPDATE_UPPER 0x0000000200000000ull /* Set upper 32 bits */ 408 #define TBCTL_UPDATE_LOWER 0x0000000300000000ull /* Set lower 32 bits */ 409 410 #ifndef SPRN_SVR 411 #define SPRN_SVR 0x11E /* System Version Register */ 412 #endif 413 #define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */ 414 /* these bits were defined in inverted endian sense originally, ugh, confusing */ 415 #define THRM1_TIN (1 << 31) 416 #define THRM1_TIV (1 << 30) 417 #define THRM1_THRES(x) ((x&0x7f)<<23) 418 #define THRM3_SITV(x) ((x&0x3fff)<<1) 419 #define THRM1_TID (1<<2) 420 #define THRM1_TIE (1<<1) 421 #define THRM1_V (1<<0) 422 #define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */ 423 #define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */ 424 #define THRM3_E (1<<0) 425 #define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */ 426 #define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */ 427 #define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */ 428 #define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 */ 429 #define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 */ 430 #define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 */ 431 #define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 */ 432 #define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */ 433 #define SPRN_VRSAVE 0x100 /* Vector Register Save Register */ 434 #define SPRN_XER 0x001 /* Fixed Point Exception Register */ 435 436 #define SPRN_SCOMC 0x114 /* SCOM Access Control */ 437 #define SPRN_SCOMD 0x115 /* SCOM Access DATA */ 438 439 /* Performance monitor SPRs */ 440 #ifdef CONFIG_PPC64 441 #define SPRN_MMCR0 795 442 #define MMCR0_FC 0x80000000UL /* freeze counters */ 443 #define MMCR0_FCS 0x40000000UL /* freeze in supervisor state */ 444 #define MMCR0_KERNEL_DISABLE MMCR0_FCS 445 #define MMCR0_FCP 0x20000000UL /* freeze in problem state */ 446 #define MMCR0_PROBLEM_DISABLE MMCR0_FCP 447 #define MMCR0_FCM1 0x10000000UL /* freeze counters while MSR mark = 1 */ 448 #define MMCR0_FCM0 0x08000000UL /* freeze counters while MSR mark = 0 */ 449 #define MMCR0_PMXE 0x04000000UL /* performance monitor exception enable */ 450 #define MMCR0_FCECE 0x02000000UL /* freeze ctrs on enabled cond or event */ 451 #define MMCR0_TBEE 0x00400000UL /* time base exception enable */ 452 #define MMCR0_PMC1CE 0x00008000UL /* PMC1 count enable*/ 453 #define MMCR0_PMCjCE 0x00004000UL /* PMCj count enable*/ 454 #define MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */ 455 #define MMCR0_PMAO 0x00000080UL /* performance monitor alert has occurred, set to 0 after handling exception */ 456 #define MMCR0_SHRFC 0x00000040UL /* SHRre freeze conditions between threads */ 457 #define MMCR0_FCTI 0x00000008UL /* freeze counters in tags inactive mode */ 458 #define MMCR0_FCTA 0x00000004UL /* freeze counters in tags active mode */ 459 #define MMCR0_FCWAIT 0x00000002UL /* freeze counter in WAIT state */ 460 #define MMCR0_FCHV 0x00000001UL /* freeze conditions in hypervisor mode */ 461 #define SPRN_MMCR1 798 462 #define SPRN_MMCRA 0x312 463 #define MMCRA_SIHV 0x10000000UL /* state of MSR HV when SIAR set */ 464 #define MMCRA_SIPR 0x08000000UL /* state of MSR PR when SIAR set */ 465 #define MMCRA_SLOT 0x07000000UL /* SLOT bits (37-39) */ 466 #define MMCRA_SLOT_SHIFT 24 467 #define MMCRA_SAMPLE_ENABLE 0x00000001UL /* enable sampling */ 468 #define POWER6_MMCRA_SIHV 0x0000040000000000ULL 469 #define POWER6_MMCRA_SIPR 0x0000020000000000ULL 470 #define POWER6_MMCRA_THRM 0x00000020UL 471 #define POWER6_MMCRA_OTHER 0x0000000EUL 472 #define SPRN_PMC1 787 473 #define SPRN_PMC2 788 474 #define SPRN_PMC3 789 475 #define SPRN_PMC4 790 476 #define SPRN_PMC5 791 477 #define SPRN_PMC6 792 478 #define SPRN_PMC7 793 479 #define SPRN_PMC8 794 480 #define SPRN_SIAR 780 481 #define SPRN_SDAR 781 482 483 #define SPRN_PA6T_MMCR0 795 484 #define PA6T_MMCR0_EN0 0x0000000000000001UL 485 #define PA6T_MMCR0_EN1 0x0000000000000002UL 486 #define PA6T_MMCR0_EN2 0x0000000000000004UL 487 #define PA6T_MMCR0_EN3 0x0000000000000008UL 488 #define PA6T_MMCR0_EN4 0x0000000000000010UL 489 #define PA6T_MMCR0_EN5 0x0000000000000020UL 490 #define PA6T_MMCR0_SUPEN 0x0000000000000040UL 491 #define PA6T_MMCR0_PREN 0x0000000000000080UL 492 #define PA6T_MMCR0_HYPEN 0x0000000000000100UL 493 #define PA6T_MMCR0_FCM0 0x0000000000000200UL 494 #define PA6T_MMCR0_FCM1 0x0000000000000400UL 495 #define PA6T_MMCR0_INTGEN 0x0000000000000800UL 496 #define PA6T_MMCR0_INTEN0 0x0000000000001000UL 497 #define PA6T_MMCR0_INTEN1 0x0000000000002000UL 498 #define PA6T_MMCR0_INTEN2 0x0000000000004000UL 499 #define PA6T_MMCR0_INTEN3 0x0000000000008000UL 500 #define PA6T_MMCR0_INTEN4 0x0000000000010000UL 501 #define PA6T_MMCR0_INTEN5 0x0000000000020000UL 502 #define PA6T_MMCR0_DISCNT 0x0000000000040000UL 503 #define PA6T_MMCR0_UOP 0x0000000000080000UL 504 #define PA6T_MMCR0_TRG 0x0000000000100000UL 505 #define PA6T_MMCR0_TRGEN 0x0000000000200000UL 506 #define PA6T_MMCR0_TRGREG 0x0000000001600000UL 507 #define PA6T_MMCR0_SIARLOG 0x0000000002000000UL 508 #define PA6T_MMCR0_SDARLOG 0x0000000004000000UL 509 #define PA6T_MMCR0_PROEN 0x0000000008000000UL 510 #define PA6T_MMCR0_PROLOG 0x0000000010000000UL 511 #define PA6T_MMCR0_DAMEN2 0x0000000020000000UL 512 #define PA6T_MMCR0_DAMEN3 0x0000000040000000UL 513 #define PA6T_MMCR0_DAMEN4 0x0000000080000000UL 514 #define PA6T_MMCR0_DAMEN5 0x0000000100000000UL 515 #define PA6T_MMCR0_DAMSEL2 0x0000000200000000UL 516 #define PA6T_MMCR0_DAMSEL3 0x0000000400000000UL 517 #define PA6T_MMCR0_DAMSEL4 0x0000000800000000UL 518 #define PA6T_MMCR0_DAMSEL5 0x0000001000000000UL 519 #define PA6T_MMCR0_HANDDIS 0x0000002000000000UL 520 #define PA6T_MMCR0_PCTEN 0x0000004000000000UL 521 #define PA6T_MMCR0_SOCEN 0x0000008000000000UL 522 #define PA6T_MMCR0_SOCMOD 0x0000010000000000UL 523 524 #define SPRN_PA6T_MMCR1 798 525 #define PA6T_MMCR1_ES2 0x00000000000000ffUL 526 #define PA6T_MMCR1_ES3 0x000000000000ff00UL 527 #define PA6T_MMCR1_ES4 0x0000000000ff0000UL 528 #define PA6T_MMCR1_ES5 0x00000000ff000000UL 529 530 #define SPRN_PA6T_UPMC0 771 /* User PerfMon Counter 0 */ 531 #define SPRN_PA6T_UPMC1 772 /* ... */ 532 #define SPRN_PA6T_UPMC2 773 533 #define SPRN_PA6T_UPMC3 774 534 #define SPRN_PA6T_UPMC4 775 535 #define SPRN_PA6T_UPMC5 776 536 #define SPRN_PA6T_UMMCR0 779 /* User Monitor Mode Control Register 0 */ 537 #define SPRN_PA6T_SIAR 780 /* Sampled Instruction Address */ 538 #define SPRN_PA6T_UMMCR1 782 /* User Monitor Mode Control Register 1 */ 539 #define SPRN_PA6T_SIER 785 /* Sampled Instruction Event Register */ 540 #define SPRN_PA6T_PMC0 787 541 #define SPRN_PA6T_PMC1 788 542 #define SPRN_PA6T_PMC2 789 543 #define SPRN_PA6T_PMC3 790 544 #define SPRN_PA6T_PMC4 791 545 #define SPRN_PA6T_PMC5 792 546 #define SPRN_PA6T_TSR0 793 /* Timestamp Register 0 */ 547 #define SPRN_PA6T_TSR1 794 /* Timestamp Register 1 */ 548 #define SPRN_PA6T_TSR2 799 /* Timestamp Register 2 */ 549 #define SPRN_PA6T_TSR3 784 /* Timestamp Register 3 */ 550 551 #define SPRN_PA6T_IER 981 /* Icache Error Register */ 552 #define SPRN_PA6T_DER 982 /* Dcache Error Register */ 553 #define SPRN_PA6T_BER 862 /* BIU Error Address Register */ 554 #define SPRN_PA6T_MER 849 /* MMU Error Register */ 555 556 #define SPRN_PA6T_IMA0 880 /* Instruction Match Array 0 */ 557 #define SPRN_PA6T_IMA1 881 /* ... */ 558 #define SPRN_PA6T_IMA2 882 559 #define SPRN_PA6T_IMA3 883 560 #define SPRN_PA6T_IMA4 884 561 #define SPRN_PA6T_IMA5 885 562 #define SPRN_PA6T_IMA6 886 563 #define SPRN_PA6T_IMA7 887 564 #define SPRN_PA6T_IMA8 888 565 #define SPRN_PA6T_IMA9 889 566 #define SPRN_PA6T_BTCR 978 /* Breakpoint and Tagging Control Register */ 567 #define SPRN_PA6T_IMAAT 979 /* Instruction Match Array Action Table */ 568 #define SPRN_PA6T_PCCR 1019 /* Power Counter Control Register */ 569 #define SPRN_BKMK 1020 /* Cell Bookmark Register */ 570 #define SPRN_PA6T_RPCCR 1021 /* Retire PC Trace Control Register */ 571 572 573 #else /* 32-bit */ 574 #define SPRN_MMCR0 952 /* Monitor Mode Control Register 0 */ 575 #define MMCR0_FC 0x80000000UL /* freeze counters */ 576 #define MMCR0_FCS 0x40000000UL /* freeze in supervisor state */ 577 #define MMCR0_FCP 0x20000000UL /* freeze in problem state */ 578 #define MMCR0_FCM1 0x10000000UL /* freeze counters while MSR mark = 1 */ 579 #define MMCR0_FCM0 0x08000000UL /* freeze counters while MSR mark = 0 */ 580 #define MMCR0_PMXE 0x04000000UL /* performance monitor exception enable */ 581 #define MMCR0_FCECE 0x02000000UL /* freeze ctrs on enabled cond or event */ 582 #define MMCR0_TBEE 0x00400000UL /* time base exception enable */ 583 #define MMCR0_PMC1CE 0x00008000UL /* PMC1 count enable*/ 584 #define MMCR0_PMCnCE 0x00004000UL /* count enable for all but PMC 1*/ 585 #define MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */ 586 #define MMCR0_PMC1SEL 0x00001fc0UL /* PMC 1 Event */ 587 #define MMCR0_PMC2SEL 0x0000003fUL /* PMC 2 Event */ 588 589 #define SPRN_MMCR1 956 590 #define MMCR1_PMC3SEL 0xf8000000UL /* PMC 3 Event */ 591 #define MMCR1_PMC4SEL 0x07c00000UL /* PMC 4 Event */ 592 #define MMCR1_PMC5SEL 0x003e0000UL /* PMC 5 Event */ 593 #define MMCR1_PMC6SEL 0x0001f800UL /* PMC 6 Event */ 594 #define SPRN_MMCR2 944 595 #define SPRN_PMC1 953 /* Performance Counter Register 1 */ 596 #define SPRN_PMC2 954 /* Performance Counter Register 2 */ 597 #define SPRN_PMC3 957 /* Performance Counter Register 3 */ 598 #define SPRN_PMC4 958 /* Performance Counter Register 4 */ 599 #define SPRN_PMC5 945 /* Performance Counter Register 5 */ 600 #define SPRN_PMC6 946 /* Performance Counter Register 6 */ 601 602 #define SPRN_SIAR 955 /* Sampled Instruction Address Register */ 603 604 /* Bit definitions for MMCR0 and PMC1 / PMC2. */ 605 #define MMCR0_PMC1_CYCLES (1 << 7) 606 #define MMCR0_PMC1_ICACHEMISS (5 << 7) 607 #define MMCR0_PMC1_DTLB (6 << 7) 608 #define MMCR0_PMC2_DCACHEMISS 0x6 609 #define MMCR0_PMC2_CYCLES 0x1 610 #define MMCR0_PMC2_ITLB 0x7 611 #define MMCR0_PMC2_LOADMISSTIME 0x5 612 #endif 613 614 /* 615 * An mtfsf instruction with the L bit set. On CPUs that support this a 616 * full 64bits of FPSCR is restored and on other CPUs the L bit is ignored. 617 * 618 * Until binutils gets the new form of mtfsf, hardwire the instruction. 619 */ 620 #ifdef CONFIG_PPC64 621 #define MTFSF_L(REG) \ 622 .long (0xfc00058e | ((0xff) << 17) | ((REG) << 11) | (1 << 25)) 623 #else 624 #define MTFSF_L(REG) mtfsf 0xff, (REG) 625 #endif 626 627 /* Processor Version Register (PVR) field extraction */ 628 629 #define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */ 630 #define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */ 631 632 #define __is_processor(pv) (PVR_VER(mfspr(SPRN_PVR)) == (pv)) 633 634 /* 635 * IBM has further subdivided the standard PowerPC 16-bit version and 636 * revision subfields of the PVR for the PowerPC 403s into the following: 637 */ 638 639 #define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */ 640 #define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */ 641 #define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */ 642 #define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */ 643 #define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */ 644 #define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */ 645 646 /* Processor Version Numbers */ 647 648 #define PVR_403GA 0x00200000 649 #define PVR_403GB 0x00200100 650 #define PVR_403GC 0x00200200 651 #define PVR_403GCX 0x00201400 652 #define PVR_405GP 0x40110000 653 #define PVR_STB03XXX 0x40310000 654 #define PVR_NP405H 0x41410000 655 #define PVR_NP405L 0x41610000 656 #define PVR_601 0x00010000 657 #define PVR_602 0x00050000 658 #define PVR_603 0x00030000 659 #define PVR_603e 0x00060000 660 #define PVR_603ev 0x00070000 661 #define PVR_603r 0x00071000 662 #define PVR_604 0x00040000 663 #define PVR_604e 0x00090000 664 #define PVR_604r 0x000A0000 665 #define PVR_620 0x00140000 666 #define PVR_740 0x00080000 667 #define PVR_750 PVR_740 668 #define PVR_740P 0x10080000 669 #define PVR_750P PVR_740P 670 #define PVR_7400 0x000C0000 671 #define PVR_7410 0x800C0000 672 #define PVR_7450 0x80000000 673 #define PVR_8540 0x80200000 674 #define PVR_8560 0x80200000 675 /* 676 * For the 8xx processors, all of them report the same PVR family for 677 * the PowerPC core. The various versions of these processors must be 678 * differentiated by the version number in the Communication Processor 679 * Module (CPM). 680 */ 681 #define PVR_821 0x00500000 682 #define PVR_823 PVR_821 683 #define PVR_850 PVR_821 684 #define PVR_860 PVR_821 685 #define PVR_8240 0x00810100 686 #define PVR_8245 0x80811014 687 #define PVR_8260 PVR_8240 688 689 /* 64-bit processors */ 690 /* XXX the prefix should be PVR_, we'll do a global sweep to fix it one day */ 691 #define PV_NORTHSTAR 0x0033 692 #define PV_PULSAR 0x0034 693 #define PV_POWER4 0x0035 694 #define PV_ICESTAR 0x0036 695 #define PV_SSTAR 0x0037 696 #define PV_POWER4p 0x0038 697 #define PV_970 0x0039 698 #define PV_POWER5 0x003A 699 #define PV_POWER5p 0x003B 700 #define PV_970FX 0x003C 701 #define PV_630 0x0040 702 #define PV_630p 0x0041 703 #define PV_970MP 0x0044 704 #define PV_970GX 0x0045 705 #define PV_BE 0x0070 706 #define PV_PA6T 0x0090 707 708 /* Macros for setting and retrieving special purpose registers */ 709 #ifndef __ASSEMBLY__ 710 #define mfmsr() ({unsigned long rval; \ 711 asm volatile("mfmsr %0" : "=r" (rval)); rval;}) 712 #ifdef CONFIG_PPC64 713 #define __mtmsrd(v, l) asm volatile("mtmsrd %0," __stringify(l) \ 714 : : "r" (v)) 715 #define mtmsrd(v) __mtmsrd((v), 0) 716 #define mtmsr(v) mtmsrd(v) 717 #else 718 #define mtmsr(v) asm volatile("mtmsr %0" : : "r" (v)) 719 #endif 720 721 #define mfspr(rn) ({unsigned long rval; \ 722 asm volatile("mfspr %0," __stringify(rn) \ 723 : "=r" (rval)); rval;}) 724 #define mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : : "r" (v)) 725 726 #ifdef __powerpc64__ 727 #ifdef CONFIG_PPC_CELL 728 #define mftb() ({unsigned long rval; \ 729 asm volatile( \ 730 "90: mftb %0;\n" \ 731 "97: cmpwi %0,0;\n" \ 732 " beq- 90b;\n" \ 733 "99:\n" \ 734 ".section __ftr_fixup,\"a\"\n" \ 735 ".align 3\n" \ 736 "98:\n" \ 737 " .llong %1\n" \ 738 " .llong %1\n" \ 739 " .llong 97b-98b\n" \ 740 " .llong 99b-98b\n" \ 741 " .llong 0\n" \ 742 " .llong 0\n" \ 743 ".previous" \ 744 : "=r" (rval) : "i" (CPU_FTR_CELL_TB_BUG)); rval;}) 745 #else 746 #define mftb() ({unsigned long rval; \ 747 asm volatile("mftb %0" : "=r" (rval)); rval;}) 748 #endif /* !CONFIG_PPC_CELL */ 749 750 #else /* __powerpc64__ */ 751 752 #define mftbl() ({unsigned long rval; \ 753 asm volatile("mftbl %0" : "=r" (rval)); rval;}) 754 #define mftbu() ({unsigned long rval; \ 755 asm volatile("mftbu %0" : "=r" (rval)); rval;}) 756 #endif /* !__powerpc64__ */ 757 758 #define mttbl(v) asm volatile("mttbl %0":: "r"(v)) 759 #define mttbu(v) asm volatile("mttbu %0":: "r"(v)) 760 761 #ifdef CONFIG_PPC32 762 #define mfsrin(v) ({unsigned int rval; \ 763 asm volatile("mfsrin %0,%1" : "=r" (rval) : "r" (v)); \ 764 rval;}) 765 #endif 766 767 #define proc_trap() asm volatile("trap") 768 769 #ifdef CONFIG_PPC64 770 771 extern void ppc64_runlatch_on(void); 772 extern void ppc64_runlatch_off(void); 773 774 extern unsigned long scom970_read(unsigned int address); 775 extern void scom970_write(unsigned int address, unsigned long value); 776 777 #else 778 #define ppc64_runlatch_on() 779 #define ppc64_runlatch_off() 780 781 #endif /* CONFIG_PPC64 */ 782 783 #define __get_SP() ({unsigned long sp; \ 784 asm volatile("mr %0,1": "=r" (sp)); sp;}) 785 786 struct pt_regs; 787 788 extern void ppc_save_regs(struct pt_regs *regs); 789 790 #endif /* __ASSEMBLY__ */ 791 #endif /* __KERNEL__ */ 792 #endif /* _ASM_POWERPC_REG_H */ 793