1 /*
2 * Copyright (c) 2006 - 2008 NetEffect, Inc. All rights reserved.
3 * Copyright (c) 2005 Open Grid Computing, Inc. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
34 #ifndef __NES_H
35 #define __NES_H
36
37 #include <linux/netdevice.h>
38 #include <linux/inetdevice.h>
39 #include <linux/spinlock.h>
40 #include <linux/kernel.h>
41 #include <linux/delay.h>
42 #include <linux/pci.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/workqueue.h>
45 #include <linux/slab.h>
46 #include <asm/io.h>
47 #include <linux/crc32c.h>
48
49 #include <rdma/ib_smi.h>
50 #include <rdma/ib_verbs.h>
51 #include <rdma/ib_pack.h>
52 #include <rdma/rdma_cm.h>
53 #include <rdma/iw_cm.h>
54
55 #define NES_SEND_FIRST_WRITE
56
57 #define QUEUE_DISCONNECTS
58
59 #define DRV_BUILD "1"
60
61 #define DRV_NAME "iw_nes"
62 #define DRV_VERSION "1.0 KO Build " DRV_BUILD
63 #define PFX DRV_NAME ": "
64
65 /*
66 * NetEffect PCI vendor id and NE010 PCI device id.
67 */
68 #ifndef PCI_VENDOR_ID_NETEFFECT /* not in pci.ids yet */
69 #define PCI_VENDOR_ID_NETEFFECT 0x1678
70 #define PCI_DEVICE_ID_NETEFFECT_NE020 0x0100
71 #endif
72
73 #define NE020_REV 4
74 #define NE020_REV1 5
75
76 #define BAR_0 0
77 #define BAR_1 2
78
79 #define RX_BUF_SIZE (1536 + 8)
80 #define NES_REG0_SIZE (4 * 1024)
81 #define NES_TX_TIMEOUT (6*HZ)
82 #define NES_FIRST_QPN 64
83 #define NES_SW_CONTEXT_ALIGN 1024
84
85 #define NES_NIC_MAX_NICS 16
86 #define NES_MAX_ARP_TABLE_SIZE 4096
87
88 #define NES_NIC_CEQ_SIZE 8
89 /* NICs will be on a separate CQ */
90 #define NES_CCEQ_SIZE ((nesadapter->max_cq / nesadapter->port_count) - 32)
91
92 #define NES_MAX_PORT_COUNT 4
93
94 #define MAX_DPC_ITERATIONS 128
95
96 #define NES_DRV_OPT_ENABLE_MPA_VER_0 0x00000001
97 #define NES_DRV_OPT_DISABLE_MPA_CRC 0x00000002
98 #define NES_DRV_OPT_DISABLE_FIRST_WRITE 0x00000004
99 #define NES_DRV_OPT_DISABLE_INTF 0x00000008
100 #define NES_DRV_OPT_ENABLE_MSI 0x00000010
101 #define NES_DRV_OPT_DUAL_LOGICAL_PORT 0x00000020
102 #define NES_DRV_OPT_SUPRESS_OPTION_BC 0x00000040
103 #define NES_DRV_OPT_NO_INLINE_DATA 0x00000080
104 #define NES_DRV_OPT_DISABLE_INT_MOD 0x00000100
105 #define NES_DRV_OPT_DISABLE_VIRT_WQ 0x00000200
106
107 #define NES_AEQ_EVENT_TIMEOUT 2500
108 #define NES_DISCONNECT_EVENT_TIMEOUT 2000
109
110 /* debug levels */
111 /* must match userspace */
112 #define NES_DBG_HW 0x00000001
113 #define NES_DBG_INIT 0x00000002
114 #define NES_DBG_ISR 0x00000004
115 #define NES_DBG_PHY 0x00000008
116 #define NES_DBG_NETDEV 0x00000010
117 #define NES_DBG_CM 0x00000020
118 #define NES_DBG_CM1 0x00000040
119 #define NES_DBG_NIC_RX 0x00000080
120 #define NES_DBG_NIC_TX 0x00000100
121 #define NES_DBG_CQP 0x00000200
122 #define NES_DBG_MMAP 0x00000400
123 #define NES_DBG_MR 0x00000800
124 #define NES_DBG_PD 0x00001000
125 #define NES_DBG_CQ 0x00002000
126 #define NES_DBG_QP 0x00004000
127 #define NES_DBG_MOD_QP 0x00008000
128 #define NES_DBG_AEQ 0x00010000
129 #define NES_DBG_IW_RX 0x00020000
130 #define NES_DBG_IW_TX 0x00040000
131 #define NES_DBG_SHUTDOWN 0x00080000
132 #define NES_DBG_RSVD1 0x10000000
133 #define NES_DBG_RSVD2 0x20000000
134 #define NES_DBG_RSVD3 0x40000000
135 #define NES_DBG_RSVD4 0x80000000
136 #define NES_DBG_ALL 0xffffffff
137
138 #ifdef CONFIG_INFINIBAND_NES_DEBUG
139 #define nes_debug(level, fmt, args...) \
140 do { \
141 if (level & nes_debug_level) \
142 printk(KERN_ERR PFX "%s[%u]: " fmt, __func__, __LINE__, ##args); \
143 } while (0)
144
145 #define assert(expr) \
146 do { \
147 if (!(expr)) { \
148 printk(KERN_ERR PFX "Assertion failed! %s, %s, %s, line %d\n", \
149 #expr, __FILE__, __func__, __LINE__); \
150 } \
151 } while (0)
152
153 #define NES_EVENT_TIMEOUT 1200000
154 #else
155 #define nes_debug(level, fmt, args...)
156 #define assert(expr) do {} while (0)
157
158 #define NES_EVENT_TIMEOUT 100000
159 #endif
160
161 #include "nes_hw.h"
162 #include "nes_verbs.h"
163 #include "nes_context.h"
164 #include "nes_user.h"
165 #include "nes_cm.h"
166
167 extern int max_mtu;
168 #define max_frame_len (max_mtu+ETH_HLEN)
169 extern int interrupt_mod_interval;
170 extern int nes_if_count;
171 extern int mpa_version;
172 extern int disable_mpa_crc;
173 extern unsigned int send_first;
174 extern unsigned int nes_drv_opt;
175 extern unsigned int nes_debug_level;
176 extern unsigned int wqm_quanta;
177 extern struct list_head nes_adapter_list;
178
179 extern atomic_t cm_connects;
180 extern atomic_t cm_accepts;
181 extern atomic_t cm_disconnects;
182 extern atomic_t cm_closes;
183 extern atomic_t cm_connecteds;
184 extern atomic_t cm_connect_reqs;
185 extern atomic_t cm_rejects;
186 extern atomic_t mod_qp_timouts;
187 extern atomic_t qps_created;
188 extern atomic_t qps_destroyed;
189 extern atomic_t sw_qps_destroyed;
190 extern u32 mh_detected;
191 extern u32 mh_pauses_sent;
192 extern u32 cm_packets_sent;
193 extern u32 cm_packets_bounced;
194 extern u32 cm_packets_created;
195 extern u32 cm_packets_received;
196 extern u32 cm_packets_dropped;
197 extern u32 cm_packets_retrans;
198 extern u32 cm_listens_created;
199 extern u32 cm_listens_destroyed;
200 extern u32 cm_backlog_drops;
201 extern atomic_t cm_loopbacks;
202 extern atomic_t cm_nodes_created;
203 extern atomic_t cm_nodes_destroyed;
204 extern atomic_t cm_accel_dropped_pkts;
205 extern atomic_t cm_resets_recvd;
206
207 extern u32 int_mod_timer_init;
208 extern u32 int_mod_cq_depth_256;
209 extern u32 int_mod_cq_depth_128;
210 extern u32 int_mod_cq_depth_32;
211 extern u32 int_mod_cq_depth_24;
212 extern u32 int_mod_cq_depth_16;
213 extern u32 int_mod_cq_depth_4;
214 extern u32 int_mod_cq_depth_1;
215
216 struct nes_device {
217 struct nes_adapter *nesadapter;
218 void __iomem *regs;
219 void __iomem *index_reg;
220 struct pci_dev *pcidev;
221 struct net_device *netdev[NES_NIC_MAX_NICS];
222 u64 link_status_interrupts;
223 struct tasklet_struct dpc_tasklet;
224 spinlock_t indexed_regs_lock;
225 unsigned long csr_start;
226 unsigned long doorbell_region;
227 unsigned long doorbell_start;
228 unsigned long mac_tx_errors;
229 unsigned long mac_pause_frames_sent;
230 unsigned long mac_pause_frames_received;
231 unsigned long mac_rx_errors;
232 unsigned long mac_rx_crc_errors;
233 unsigned long mac_rx_symbol_err_frames;
234 unsigned long mac_rx_jabber_frames;
235 unsigned long mac_rx_oversized_frames;
236 unsigned long mac_rx_short_frames;
237 unsigned long port_rx_discards;
238 unsigned long port_tx_discards;
239 unsigned int mac_index;
240 unsigned int nes_stack_start;
241
242 /* Control Structures */
243 void *cqp_vbase;
244 dma_addr_t cqp_pbase;
245 u32 cqp_mem_size;
246 u8 ceq_index;
247 u8 nic_ceq_index;
248 struct nes_hw_cqp cqp;
249 struct nes_hw_cq ccq;
250 struct list_head cqp_avail_reqs;
251 struct list_head cqp_pending_reqs;
252 struct nes_cqp_request *nes_cqp_requests;
253
254 u32 int_req;
255 u32 int_stat;
256 u32 timer_int_req;
257 u32 timer_only_int_count;
258 u32 intf_int_req;
259 u32 last_mac_tx_pauses;
260 u32 last_used_chunks_tx;
261 struct list_head list;
262
263 u16 base_doorbell_index;
264 u16 currcq_count;
265 u16 deepcq_count;
266 u8 msi_enabled;
267 u8 netdev_count;
268 u8 napi_isr_ran;
269 u8 disable_rx_flow_control;
270 u8 disable_tx_flow_control;
271 };
272
273
get_crc_value(struct nes_v4_quad * nes_quad)274 static inline __le32 get_crc_value(struct nes_v4_quad *nes_quad)
275 {
276 u32 crc_value;
277 crc_value = crc32c(~0, (void *)nes_quad, sizeof (struct nes_v4_quad));
278
279 /*
280 * With commit ef19454b ("[LIB] crc32c: Keep intermediate crc
281 * state in cpu order"), behavior of crc32c changes on
282 * big-endian platforms. Our algorithm expects the previous
283 * behavior; otherwise we have RDMA connection establishment
284 * issue on big-endian.
285 */
286 return cpu_to_le32(crc_value);
287 }
288
289 static inline void
set_wqe_64bit_value(__le32 * wqe_words,u32 index,u64 value)290 set_wqe_64bit_value(__le32 *wqe_words, u32 index, u64 value)
291 {
292 wqe_words[index] = cpu_to_le32((u32) ((unsigned long)value));
293 wqe_words[index + 1] = cpu_to_le32((u32)(upper_32_bits((unsigned long)value)));
294 }
295
296 static inline void
set_wqe_32bit_value(__le32 * wqe_words,u32 index,u32 value)297 set_wqe_32bit_value(__le32 *wqe_words, u32 index, u32 value)
298 {
299 wqe_words[index] = cpu_to_le32(value);
300 }
301
302 static inline void
nes_fill_init_cqp_wqe(struct nes_hw_cqp_wqe * cqp_wqe,struct nes_device * nesdev)303 nes_fill_init_cqp_wqe(struct nes_hw_cqp_wqe *cqp_wqe, struct nes_device *nesdev)
304 {
305 set_wqe_64bit_value(cqp_wqe->wqe_words, NES_CQP_WQE_COMP_CTX_LOW_IDX,
306 (u64)((unsigned long) &nesdev->cqp));
307 cqp_wqe->wqe_words[NES_CQP_WQE_COMP_SCRATCH_LOW_IDX] = 0;
308 cqp_wqe->wqe_words[NES_CQP_WQE_COMP_SCRATCH_HIGH_IDX] = 0;
309 cqp_wqe->wqe_words[NES_CQP_STAG_WQE_PBL_BLK_COUNT_IDX] = 0;
310 cqp_wqe->wqe_words[NES_CQP_STAG_WQE_PBL_LEN_IDX] = 0;
311 cqp_wqe->wqe_words[NES_CQP_STAG_WQE_LEN_LOW_IDX] = 0;
312 cqp_wqe->wqe_words[NES_CQP_STAG_WQE_PA_LOW_IDX] = 0;
313 cqp_wqe->wqe_words[NES_CQP_STAG_WQE_PA_HIGH_IDX] = 0;
314 }
315
316 static inline void
nes_fill_init_qp_wqe(struct nes_hw_qp_wqe * wqe,struct nes_qp * nesqp,u32 head)317 nes_fill_init_qp_wqe(struct nes_hw_qp_wqe *wqe, struct nes_qp *nesqp, u32 head)
318 {
319 u32 value;
320 value = ((u32)((unsigned long) nesqp)) | head;
321 set_wqe_32bit_value(wqe->wqe_words, NES_IWARP_SQ_WQE_COMP_CTX_HIGH_IDX,
322 (u32)(upper_32_bits((unsigned long)(nesqp))));
323 set_wqe_32bit_value(wqe->wqe_words, NES_IWARP_SQ_WQE_COMP_CTX_LOW_IDX, value);
324 }
325
326 /* Read from memory-mapped device */
nes_read_indexed(struct nes_device * nesdev,u32 reg_index)327 static inline u32 nes_read_indexed(struct nes_device *nesdev, u32 reg_index)
328 {
329 unsigned long flags;
330 void __iomem *addr = nesdev->index_reg;
331 u32 value;
332
333 spin_lock_irqsave(&nesdev->indexed_regs_lock, flags);
334
335 writel(reg_index, addr);
336 value = readl((void __iomem *)addr + 4);
337
338 spin_unlock_irqrestore(&nesdev->indexed_regs_lock, flags);
339 return value;
340 }
341
nes_read32(const void __iomem * addr)342 static inline u32 nes_read32(const void __iomem *addr)
343 {
344 return readl(addr);
345 }
346
nes_read16(const void __iomem * addr)347 static inline u16 nes_read16(const void __iomem *addr)
348 {
349 return readw(addr);
350 }
351
nes_read8(const void __iomem * addr)352 static inline u8 nes_read8(const void __iomem *addr)
353 {
354 return readb(addr);
355 }
356
357 /* Write to memory-mapped device */
nes_write_indexed(struct nes_device * nesdev,u32 reg_index,u32 val)358 static inline void nes_write_indexed(struct nes_device *nesdev, u32 reg_index, u32 val)
359 {
360 unsigned long flags;
361 void __iomem *addr = nesdev->index_reg;
362
363 spin_lock_irqsave(&nesdev->indexed_regs_lock, flags);
364
365 writel(reg_index, addr);
366 writel(val, (void __iomem *)addr + 4);
367
368 spin_unlock_irqrestore(&nesdev->indexed_regs_lock, flags);
369 }
370
nes_write32(void __iomem * addr,u32 val)371 static inline void nes_write32(void __iomem *addr, u32 val)
372 {
373 writel(val, addr);
374 }
375
nes_write16(void __iomem * addr,u16 val)376 static inline void nes_write16(void __iomem *addr, u16 val)
377 {
378 writew(val, addr);
379 }
380
nes_write8(void __iomem * addr,u8 val)381 static inline void nes_write8(void __iomem *addr, u8 val)
382 {
383 writeb(val, addr);
384 }
385
386
387
nes_alloc_resource(struct nes_adapter * nesadapter,unsigned long * resource_array,u32 max_resources,u32 * req_resource_num,u32 * next)388 static inline int nes_alloc_resource(struct nes_adapter *nesadapter,
389 unsigned long *resource_array, u32 max_resources,
390 u32 *req_resource_num, u32 *next)
391 {
392 unsigned long flags;
393 u32 resource_num;
394
395 spin_lock_irqsave(&nesadapter->resource_lock, flags);
396
397 resource_num = find_next_zero_bit(resource_array, max_resources, *next);
398 if (resource_num >= max_resources) {
399 resource_num = find_first_zero_bit(resource_array, max_resources);
400 if (resource_num >= max_resources) {
401 printk(KERN_ERR PFX "%s: No available resourcess.\n", __func__);
402 spin_unlock_irqrestore(&nesadapter->resource_lock, flags);
403 return -EMFILE;
404 }
405 }
406 set_bit(resource_num, resource_array);
407 *next = resource_num+1;
408 if (*next == max_resources) {
409 *next = 0;
410 }
411 spin_unlock_irqrestore(&nesadapter->resource_lock, flags);
412 *req_resource_num = resource_num;
413
414 return 0;
415 }
416
nes_is_resource_allocated(struct nes_adapter * nesadapter,unsigned long * resource_array,u32 resource_num)417 static inline int nes_is_resource_allocated(struct nes_adapter *nesadapter,
418 unsigned long *resource_array, u32 resource_num)
419 {
420 unsigned long flags;
421 int bit_is_set;
422
423 spin_lock_irqsave(&nesadapter->resource_lock, flags);
424
425 bit_is_set = test_bit(resource_num, resource_array);
426 nes_debug(NES_DBG_HW, "resource_num %u is%s allocated.\n",
427 resource_num, (bit_is_set ? "": " not"));
428 spin_unlock_irqrestore(&nesadapter->resource_lock, flags);
429
430 return bit_is_set;
431 }
432
nes_free_resource(struct nes_adapter * nesadapter,unsigned long * resource_array,u32 resource_num)433 static inline void nes_free_resource(struct nes_adapter *nesadapter,
434 unsigned long *resource_array, u32 resource_num)
435 {
436 unsigned long flags;
437
438 spin_lock_irqsave(&nesadapter->resource_lock, flags);
439 clear_bit(resource_num, resource_array);
440 spin_unlock_irqrestore(&nesadapter->resource_lock, flags);
441 }
442
to_nesvnic(struct ib_device * ibdev)443 static inline struct nes_vnic *to_nesvnic(struct ib_device *ibdev)
444 {
445 return container_of(ibdev, struct nes_ib_device, ibdev)->nesvnic;
446 }
447
to_nespd(struct ib_pd * ibpd)448 static inline struct nes_pd *to_nespd(struct ib_pd *ibpd)
449 {
450 return container_of(ibpd, struct nes_pd, ibpd);
451 }
452
to_nesucontext(struct ib_ucontext * ibucontext)453 static inline struct nes_ucontext *to_nesucontext(struct ib_ucontext *ibucontext)
454 {
455 return container_of(ibucontext, struct nes_ucontext, ibucontext);
456 }
457
to_nesmr(struct ib_mr * ibmr)458 static inline struct nes_mr *to_nesmr(struct ib_mr *ibmr)
459 {
460 return container_of(ibmr, struct nes_mr, ibmr);
461 }
462
to_nesmr_from_ibfmr(struct ib_fmr * ibfmr)463 static inline struct nes_mr *to_nesmr_from_ibfmr(struct ib_fmr *ibfmr)
464 {
465 return container_of(ibfmr, struct nes_mr, ibfmr);
466 }
467
to_nesmw(struct ib_mw * ibmw)468 static inline struct nes_mr *to_nesmw(struct ib_mw *ibmw)
469 {
470 return container_of(ibmw, struct nes_mr, ibmw);
471 }
472
to_nesfmr(struct nes_mr * nesmr)473 static inline struct nes_fmr *to_nesfmr(struct nes_mr *nesmr)
474 {
475 return container_of(nesmr, struct nes_fmr, nesmr);
476 }
477
to_nescq(struct ib_cq * ibcq)478 static inline struct nes_cq *to_nescq(struct ib_cq *ibcq)
479 {
480 return container_of(ibcq, struct nes_cq, ibcq);
481 }
482
to_nesqp(struct ib_qp * ibqp)483 static inline struct nes_qp *to_nesqp(struct ib_qp *ibqp)
484 {
485 return container_of(ibqp, struct nes_qp, ibqp);
486 }
487
488
489
490 /* nes.c */
491 void nes_add_ref(struct ib_qp *);
492 void nes_rem_ref(struct ib_qp *);
493 struct ib_qp *nes_get_qp(struct ib_device *, int);
494
495
496 /* nes_hw.c */
497 struct nes_adapter *nes_init_adapter(struct nes_device *, u8);
498 void nes_nic_init_timer_defaults(struct nes_device *, u8);
499 void nes_destroy_adapter(struct nes_adapter *);
500 int nes_init_cqp(struct nes_device *);
501 int nes_init_phy(struct nes_device *);
502 int nes_init_nic_qp(struct nes_device *, struct net_device *);
503 void nes_destroy_nic_qp(struct nes_vnic *);
504 int nes_napi_isr(struct nes_device *);
505 void nes_dpc(unsigned long);
506 void nes_nic_ce_handler(struct nes_device *, struct nes_hw_nic_cq *);
507 void nes_iwarp_ce_handler(struct nes_device *, struct nes_hw_cq *);
508 int nes_destroy_cqp(struct nes_device *);
509 int nes_nic_cm_xmit(struct sk_buff *, struct net_device *);
510
511 /* nes_nic.c */
512 struct net_device *nes_netdev_init(struct nes_device *, void __iomem *);
513 void nes_netdev_destroy(struct net_device *);
514 int nes_nic_cm_xmit(struct sk_buff *, struct net_device *);
515
516 /* nes_cm.c */
517 void *nes_cm_create(struct net_device *);
518 int nes_cm_recv(struct sk_buff *, struct net_device *);
519 void nes_update_arp(unsigned char *, u32, u32, u16, u16);
520 void nes_manage_arp_cache(struct net_device *, unsigned char *, u32, u32);
521 void nes_sock_release(struct nes_qp *, unsigned long *);
522 void flush_wqes(struct nes_device *nesdev, struct nes_qp *, u32, u32);
523 int nes_manage_apbvt(struct nes_vnic *, u32, u32, u32);
524 int nes_cm_disconn(struct nes_qp *);
525 void nes_cm_disconn_worker(void *);
526
527 /* nes_verbs.c */
528 int nes_hw_modify_qp(struct nes_device *, struct nes_qp *, u32, u32);
529 int nes_modify_qp(struct ib_qp *, struct ib_qp_attr *, int, struct ib_udata *);
530 struct nes_ib_device *nes_init_ofa_device(struct net_device *);
531 void nes_destroy_ofa_device(struct nes_ib_device *);
532 int nes_register_ofa_device(struct nes_ib_device *);
533
534 /* nes_util.c */
535 int nes_read_eeprom_values(struct nes_device *, struct nes_adapter *);
536 void nes_write_1G_phy_reg(struct nes_device *, u8, u8, u16);
537 void nes_read_1G_phy_reg(struct nes_device *, u8, u8, u16 *);
538 void nes_write_10G_phy_reg(struct nes_device *, u16, u8, u16, u16);
539 void nes_read_10G_phy_reg(struct nes_device *, u8, u8, u16);
540 struct nes_cqp_request *nes_get_cqp_request(struct nes_device *);
541 void nes_free_cqp_request(struct nes_device *nesdev,
542 struct nes_cqp_request *cqp_request);
543 void nes_put_cqp_request(struct nes_device *nesdev,
544 struct nes_cqp_request *cqp_request);
545 void nes_post_cqp_request(struct nes_device *, struct nes_cqp_request *);
546 int nes_arp_table(struct nes_device *, u32, u8 *, u32);
547 void nes_mh_fix(unsigned long);
548 void nes_clc(unsigned long);
549 void nes_dump_mem(unsigned int, void *, int);
550 u32 nes_crc32(u32, u32, u32, u32, u8 *, u32, u32, u32);
551
552 #endif /* __NES_H */
553