1 /* 2 * arch/arm/mach-orion5x/include/mach/orion5x.h 3 * 4 * Generic definitions of Orion SoC flavors: 5 * Orion-1, Orion-VoIP, Orion-NAS, Orion-2, and Orion-1-90. 6 * 7 * Maintainer: Tzachi Perelstein <tzachi@marvell.com> 8 * 9 * This file is licensed under the terms of the GNU General Public 10 * License version 2. This program is licensed "as is" without any 11 * warranty of any kind, whether express or implied. 12 */ 13 14 #ifndef __ASM_ARCH_ORION5X_H 15 #define __ASM_ARCH_ORION5X_H 16 17 /***************************************************************************** 18 * Orion Address Maps 19 * 20 * phys 21 * e0000000 PCIe MEM space 22 * e8000000 PCI MEM space 23 * f0000000 PCIe WA space (Orion-1/Orion-NAS only) 24 * f1000000 on-chip peripheral registers 25 * f2000000 PCIe I/O space 26 * f2100000 PCI I/O space 27 * f4000000 device bus mappings (boot) 28 * fa000000 device bus mappings (cs0) 29 * fa800000 device bus mappings (cs2) 30 * fc000000 device bus mappings (cs0/cs1) 31 * 32 * virt phys size 33 * fdd00000 f1000000 1M on-chip peripheral registers 34 * fde00000 f2000000 1M PCIe I/O space 35 * fdf00000 f2100000 1M PCI I/O space 36 * fe000000 f0000000 16M PCIe WA space (Orion-1/Orion-NAS only) 37 ****************************************************************************/ 38 #define ORION5X_REGS_PHYS_BASE 0xf1000000 39 #define ORION5X_REGS_VIRT_BASE 0xfdd00000 40 #define ORION5X_REGS_SIZE SZ_1M 41 42 #define ORION5X_PCIE_IO_PHYS_BASE 0xf2000000 43 #define ORION5X_PCIE_IO_VIRT_BASE 0xfde00000 44 #define ORION5X_PCIE_IO_BUS_BASE 0x00000000 45 #define ORION5X_PCIE_IO_SIZE SZ_1M 46 47 #define ORION5X_PCI_IO_PHYS_BASE 0xf2100000 48 #define ORION5X_PCI_IO_VIRT_BASE 0xfdf00000 49 #define ORION5X_PCI_IO_BUS_BASE 0x00100000 50 #define ORION5X_PCI_IO_SIZE SZ_1M 51 52 /* Relevant only for Orion-1/Orion-NAS */ 53 #define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000 54 #define ORION5X_PCIE_WA_VIRT_BASE 0xfe000000 55 #define ORION5X_PCIE_WA_SIZE SZ_16M 56 57 #define ORION5X_PCIE_MEM_PHYS_BASE 0xe0000000 58 #define ORION5X_PCIE_MEM_SIZE SZ_128M 59 60 #define ORION5X_PCI_MEM_PHYS_BASE 0xe8000000 61 #define ORION5X_PCI_MEM_SIZE SZ_128M 62 63 /******************************************************************************* 64 * Supported Devices & Revisions 65 ******************************************************************************/ 66 /* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */ 67 #define MV88F5181_DEV_ID 0x5181 68 #define MV88F5181_REV_B1 3 69 #define MV88F5181L_REV_A0 8 70 #define MV88F5181L_REV_A1 9 71 /* Orion-NAS (88F5182) */ 72 #define MV88F5182_DEV_ID 0x5182 73 #define MV88F5182_REV_A2 2 74 /* Orion-2 (88F5281) */ 75 #define MV88F5281_DEV_ID 0x5281 76 #define MV88F5281_REV_D0 4 77 #define MV88F5281_REV_D1 5 78 #define MV88F5281_REV_D2 6 79 /* Orion-1-90 (88F6183) */ 80 #define MV88F6183_DEV_ID 0x6183 81 #define MV88F6183_REV_B0 3 82 83 /******************************************************************************* 84 * Orion Registers Map 85 ******************************************************************************/ 86 #define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x00000) 87 #define ORION5X_DDR_REG(x) (ORION5X_DDR_VIRT_BASE | (x)) 88 89 #define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x10000) 90 #define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x10000) 91 #define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE | (x)) 92 #define SPI_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x0600) 93 #define I2C_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x1000) 94 #define UART0_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x2000) 95 #define UART0_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE | 0x2000) 96 #define UART1_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x2100) 97 #define UART1_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE | 0x2100) 98 99 #define ORION5X_BRIDGE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x20000) 100 #define ORION5X_BRIDGE_REG(x) (ORION5X_BRIDGE_VIRT_BASE | (x)) 101 #define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE | 0x300) 102 103 #define ORION5X_PCI_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x30000) 104 #define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE | (x)) 105 106 #define ORION5X_PCIE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x40000) 107 #define ORION5X_PCIE_REG(x) (ORION5X_PCIE_VIRT_BASE | (x)) 108 109 #define ORION5X_USB0_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x50000) 110 #define ORION5X_USB0_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x50000) 111 #define ORION5X_USB0_REG(x) (ORION5X_USB0_VIRT_BASE | (x)) 112 113 #define ORION5X_XOR_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x60900) 114 #define ORION5X_XOR_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x60900) 115 #define ORION5X_XOR_REG(x) (ORION5X_XOR_VIRT_BASE | (x)) 116 117 #define ORION5X_ETH_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x70000) 118 #define ORION5X_ETH_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x70000) 119 #define ORION5X_ETH_REG(x) (ORION5X_ETH_VIRT_BASE | (x)) 120 121 #define ORION5X_SATA_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x80000) 122 #define ORION5X_SATA_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x80000) 123 #define ORION5X_SATA_REG(x) (ORION5X_SATA_VIRT_BASE | (x)) 124 125 #define ORION5X_USB1_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0xa0000) 126 #define ORION5X_USB1_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0xa0000) 127 #define ORION5X_USB1_REG(x) (ORION5X_USB1_VIRT_BASE | (x)) 128 129 /******************************************************************************* 130 * Device Bus Registers 131 ******************************************************************************/ 132 #define MPP_0_7_CTRL ORION5X_DEV_BUS_REG(0x000) 133 #define MPP_8_15_CTRL ORION5X_DEV_BUS_REG(0x004) 134 #define MPP_16_19_CTRL ORION5X_DEV_BUS_REG(0x050) 135 #define MPP_DEV_CTRL ORION5X_DEV_BUS_REG(0x008) 136 #define MPP_RESET_SAMPLE ORION5X_DEV_BUS_REG(0x010) 137 #define DEV_BANK_0_PARAM ORION5X_DEV_BUS_REG(0x45c) 138 #define DEV_BANK_1_PARAM ORION5X_DEV_BUS_REG(0x460) 139 #define DEV_BANK_2_PARAM ORION5X_DEV_BUS_REG(0x464) 140 #define DEV_BANK_BOOT_PARAM ORION5X_DEV_BUS_REG(0x46c) 141 #define DEV_BUS_CTRL ORION5X_DEV_BUS_REG(0x4c0) 142 #define DEV_BUS_INT_CAUSE ORION5X_DEV_BUS_REG(0x4d0) 143 #define DEV_BUS_INT_MASK ORION5X_DEV_BUS_REG(0x4d4) 144 145 /*************************************************************************** 146 * Orion CPU Bridge Registers 147 **************************************************************************/ 148 #define CPU_CONF ORION5X_BRIDGE_REG(0x100) 149 #define CPU_CTRL ORION5X_BRIDGE_REG(0x104) 150 #define CPU_RESET_MASK ORION5X_BRIDGE_REG(0x108) 151 #define WDT_RESET 0x0002 152 #define CPU_SOFT_RESET ORION5X_BRIDGE_REG(0x10c) 153 #define POWER_MNG_CTRL_REG ORION5X_BRIDGE_REG(0x11C) 154 #define BRIDGE_CAUSE ORION5X_BRIDGE_REG(0x110) 155 #define WDT_INT_REQ 0x0008 156 #define BRIDGE_MASK ORION5X_BRIDGE_REG(0x114) 157 #define BRIDGE_INT_TIMER0 0x0002 158 #define BRIDGE_INT_TIMER1 0x0004 159 #define BRIDGE_INT_TIMER1_CLR (~0x0004) 160 #define MAIN_IRQ_CAUSE ORION5X_BRIDGE_REG(0x200) 161 #define MAIN_IRQ_MASK ORION5X_BRIDGE_REG(0x204) 162 163 164 #endif 165