1 /* 2 * pnx833x.h: Register mappings for PNX833X. 3 * 4 * Copyright 2008 NXP Semiconductors 5 * Chris Steel <chris.steel@nxp.com> 6 * Daniel Laird <daniel.j.laird@nxp.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 #ifndef __ASM_MIPS_MACH_PNX833X_PNX833X_H 23 #define __ASM_MIPS_MACH_PNX833X_PNX833X_H 24 25 /* All regs are accessed in KSEG1 */ 26 #define PNX833X_BASE (0xa0000000ul + 0x17E00000ul) 27 28 #define PNX833X_REG(offs) (*((volatile unsigned long *)(PNX833X_BASE + offs))) 29 30 /* Registers are named exactly as in PNX833X docs, just with PNX833X_ prefix */ 31 32 /* Read access to multibit fields */ 33 #define PNX833X_BIT(val, reg, field) ((val) & PNX833X_##reg##_##field) 34 #define PNX833X_REGBIT(reg, field) PNX833X_BIT(PNX833X_##reg, reg, field) 35 36 /* Use PNX833X_FIELD to extract a field from val */ 37 #define PNX_FIELD(cpu, val, reg, field) \ 38 (((val) & PNX##cpu##_##reg##_##field##_MASK) >> \ 39 PNX##cpu##_##reg##_##field##_SHIFT) 40 #define PNX833X_FIELD(val, reg, field) PNX_FIELD(833X, val, reg, field) 41 #define PNX8330_FIELD(val, reg, field) PNX_FIELD(8330, val, reg, field) 42 #define PNX8335_FIELD(val, reg, field) PNX_FIELD(8335, val, reg, field) 43 44 /* Use PNX833X_REGFIELD to extract a field from a register */ 45 #define PNX833X_REGFIELD(reg, field) PNX833X_FIELD(PNX833X_##reg, reg, field) 46 #define PNX8330_REGFIELD(reg, field) PNX8330_FIELD(PNX8330_##reg, reg, field) 47 #define PNX8335_REGFIELD(reg, field) PNX8335_FIELD(PNX8335_##reg, reg, field) 48 49 50 #define PNX_WRITEFIELD(cpu, val, reg, field) \ 51 (PNX##cpu##_##reg = (PNX##cpu##_##reg & ~(PNX##cpu##_##reg##_##field##_MASK)) | \ 52 ((val) << PNX##cpu##_##reg##_##field##_SHIFT)) 53 #define PNX833X_WRITEFIELD(val, reg, field) \ 54 PNX_WRITEFIELD(833X, val, reg, field) 55 #define PNX8330_WRITEFIELD(val, reg, field) \ 56 PNX_WRITEFIELD(8330, val, reg, field) 57 #define PNX8335_WRITEFIELD(val, reg, field) \ 58 PNX_WRITEFIELD(8335, val, reg, field) 59 60 61 /* Macros to detect CPU type */ 62 63 #define PNX833X_CONFIG_MODULE_ID PNX833X_REG(0x7FFC) 64 #define PNX833X_CONFIG_MODULE_ID_MAJREV_MASK 0x0000f000 65 #define PNX833X_CONFIG_MODULE_ID_MAJREV_SHIFT 12 66 #define PNX8330_CONFIG_MODULE_MAJREV 4 67 #define PNX8335_CONFIG_MODULE_MAJREV 5 68 #define CPU_IS_PNX8330 (PNX833X_REGFIELD(CONFIG_MODULE_ID, MAJREV) == \ 69 PNX8330_CONFIG_MODULE_MAJREV) 70 #define CPU_IS_PNX8335 (PNX833X_REGFIELD(CONFIG_MODULE_ID, MAJREV) == \ 71 PNX8335_CONFIG_MODULE_MAJREV) 72 73 74 75 #define PNX833X_RESET_CONTROL PNX833X_REG(0x8004) 76 #define PNX833X_RESET_CONTROL_2 PNX833X_REG(0x8014) 77 78 #define PNX833X_PIC_REG(offs) PNX833X_REG(0x01000 + (offs)) 79 #define PNX833X_PIC_INT_PRIORITY PNX833X_PIC_REG(0x0) 80 #define PNX833X_PIC_INT_SRC PNX833X_PIC_REG(0x4) 81 #define PNX833X_PIC_INT_SRC_INT_SRC_MASK 0x00000FF8ul /* bits 11:3 */ 82 #define PNX833X_PIC_INT_SRC_INT_SRC_SHIFT 3 83 #define PNX833X_PIC_INT_REG(irq) PNX833X_PIC_REG(0x10 + 4*(irq)) 84 85 #define PNX833X_CLOCK_CPUCP_CTL PNX833X_REG(0x9228) 86 #define PNX833X_CLOCK_CPUCP_CTL_EXIT_RESET 0x00000002ul /* bit 1 */ 87 #define PNX833X_CLOCK_CPUCP_CTL_DIV_CLOCK_MASK 0x00000018ul /* bits 4:3 */ 88 #define PNX833X_CLOCK_CPUCP_CTL_DIV_CLOCK_SHIFT 3 89 90 #define PNX8335_CLOCK_PLL_CPU_CTL PNX833X_REG(0x9020) 91 #define PNX8335_CLOCK_PLL_CPU_CTL_FREQ_MASK 0x1f 92 #define PNX8335_CLOCK_PLL_CPU_CTL_FREQ_SHIFT 0 93 94 #define PNX833X_CONFIG_MUX PNX833X_REG(0x7004) 95 #define PNX833X_CONFIG_MUX_IDE_MUX 0x00000080 /* bit 7 */ 96 97 #define PNX8330_CONFIG_POLYFUSE_7 PNX833X_REG(0x7040) 98 #define PNX8330_CONFIG_POLYFUSE_7_BOOT_MODE_MASK 0x00180000 99 #define PNX8330_CONFIG_POLYFUSE_7_BOOT_MODE_SHIFT 19 100 101 #define PNX833X_PIO_IN PNX833X_REG(0xF000) 102 #define PNX833X_PIO_OUT PNX833X_REG(0xF004) 103 #define PNX833X_PIO_DIR PNX833X_REG(0xF008) 104 #define PNX833X_PIO_SEL PNX833X_REG(0xF014) 105 #define PNX833X_PIO_INT_EDGE PNX833X_REG(0xF020) 106 #define PNX833X_PIO_INT_HI PNX833X_REG(0xF024) 107 #define PNX833X_PIO_INT_LO PNX833X_REG(0xF028) 108 #define PNX833X_PIO_INT_STATUS PNX833X_REG(0xFFE0) 109 #define PNX833X_PIO_INT_ENABLE PNX833X_REG(0xFFE4) 110 #define PNX833X_PIO_INT_CLEAR PNX833X_REG(0xFFE8) 111 #define PNX833X_PIO_IN2 PNX833X_REG(0xF05C) 112 #define PNX833X_PIO_OUT2 PNX833X_REG(0xF060) 113 #define PNX833X_PIO_DIR2 PNX833X_REG(0xF064) 114 #define PNX833X_PIO_SEL2 PNX833X_REG(0xF068) 115 116 #define PNX833X_UART0_PORTS_START (PNX833X_BASE + 0xB000) 117 #define PNX833X_UART0_PORTS_END (PNX833X_BASE + 0xBFFF) 118 #define PNX833X_UART1_PORTS_START (PNX833X_BASE + 0xC000) 119 #define PNX833X_UART1_PORTS_END (PNX833X_BASE + 0xCFFF) 120 121 #define PNX833X_USB_PORTS_START (PNX833X_BASE + 0x19000) 122 #define PNX833X_USB_PORTS_END (PNX833X_BASE + 0x19FFF) 123 124 #define PNX833X_CONFIG_USB PNX833X_REG(0x7008) 125 126 #define PNX833X_I2C0_PORTS_START (PNX833X_BASE + 0xD000) 127 #define PNX833X_I2C0_PORTS_END (PNX833X_BASE + 0xDFFF) 128 #define PNX833X_I2C1_PORTS_START (PNX833X_BASE + 0xE000) 129 #define PNX833X_I2C1_PORTS_END (PNX833X_BASE + 0xEFFF) 130 131 #define PNX833X_IDE_PORTS_START (PNX833X_BASE + 0x1A000) 132 #define PNX833X_IDE_PORTS_END (PNX833X_BASE + 0x1AFFF) 133 #define PNX833X_IDE_MODULE_ID PNX833X_REG(0x1AFFC) 134 135 #define PNX833X_IDE_MODULE_ID_MODULE_ID_MASK 0xFFFF0000 136 #define PNX833X_IDE_MODULE_ID_MODULE_ID_SHIFT 16 137 #define PNX833X_IDE_MODULE_ID_VALUE 0xA009 138 139 140 #define PNX833X_MIU_SEL0 PNX833X_REG(0x2004) 141 #define PNX833X_MIU_SEL0_TIMING PNX833X_REG(0x2008) 142 #define PNX833X_MIU_SEL1 PNX833X_REG(0x200C) 143 #define PNX833X_MIU_SEL1_TIMING PNX833X_REG(0x2010) 144 #define PNX833X_MIU_SEL2 PNX833X_REG(0x2014) 145 #define PNX833X_MIU_SEL2_TIMING PNX833X_REG(0x2018) 146 #define PNX833X_MIU_SEL3 PNX833X_REG(0x201C) 147 #define PNX833X_MIU_SEL3_TIMING PNX833X_REG(0x2020) 148 149 #define PNX833X_MIU_SEL0_SPI_MODE_ENABLE_MASK (1 << 14) 150 #define PNX833X_MIU_SEL0_SPI_MODE_ENABLE_SHIFT 14 151 152 #define PNX833X_MIU_SEL0_BURST_MODE_ENABLE_MASK (1 << 7) 153 #define PNX833X_MIU_SEL0_BURST_MODE_ENABLE_SHIFT 7 154 155 #define PNX833X_MIU_SEL0_BURST_PAGE_LEN_MASK (0xF << 9) 156 #define PNX833X_MIU_SEL0_BURST_PAGE_LEN_SHIFT 9 157 158 #define PNX833X_MIU_CONFIG_SPI PNX833X_REG(0x2000) 159 160 #define PNX833X_MIU_CONFIG_SPI_OPCODE_MASK (0xFF << 3) 161 #define PNX833X_MIU_CONFIG_SPI_OPCODE_SHIFT 3 162 163 #define PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_MASK (1 << 2) 164 #define PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_SHIFT 2 165 166 #define PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_MASK (1 << 1) 167 #define PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_SHIFT 1 168 169 #define PNX833X_MIU_CONFIG_SPI_SYNC_MASK (1 << 0) 170 #define PNX833X_MIU_CONFIG_SPI_SYNC_SHIFT 0 171 172 #define PNX833X_WRITE_CONFIG_SPI(opcode, data_enable, addr_enable, sync) \ 173 (PNX833X_MIU_CONFIG_SPI = \ 174 ((opcode) << PNX833X_MIU_CONFIG_SPI_OPCODE_SHIFT) | \ 175 ((data_enable) << PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_SHIFT) | \ 176 ((addr_enable) << PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_SHIFT) | \ 177 ((sync) << PNX833X_MIU_CONFIG_SPI_SYNC_SHIFT)) 178 179 #define PNX8335_IP3902_PORTS_START (PNX833X_BASE + 0x2F000) 180 #define PNX8335_IP3902_PORTS_END (PNX833X_BASE + 0x2FFFF) 181 #define PNX8335_IP3902_MODULE_ID PNX833X_REG(0x2FFFC) 182 183 #define PNX8335_IP3902_MODULE_ID_MODULE_ID_MASK 0xFFFF0000 184 #define PNX8335_IP3902_MODULE_ID_MODULE_ID_SHIFT 16 185 #define PNX8335_IP3902_MODULE_ID_VALUE 0x3902 186 187 /* I/O location(gets remapped)*/ 188 #define PNX8335_NAND_BASE 0x18000000 189 /* I/O location with CLE high */ 190 #define PNX8335_NAND_CLE_MASK 0x00100000 191 /* I/O location with ALE high */ 192 #define PNX8335_NAND_ALE_MASK 0x00010000 193 194 #define PNX8335_SATA_PORTS_START (PNX833X_BASE + 0x2E000) 195 #define PNX8335_SATA_PORTS_END (PNX833X_BASE + 0x2EFFF) 196 #define PNX8335_SATA_MODULE_ID PNX833X_REG(0x2EFFC) 197 198 #define PNX8335_SATA_MODULE_ID_MODULE_ID_MASK 0xFFFF0000 199 #define PNX8335_SATA_MODULE_ID_MODULE_ID_SHIFT 16 200 #define PNX8335_SATA_MODULE_ID_VALUE 0xA099 201 202 #endif 203