1 /* 2 * Low-Level PCI Support for SH7751 targets 3 * 4 * Dustin McIntire (dustin@sensoria.com) (c) 2001 5 * Paul Mundt (lethal@linux-sh.org) (c) 2003 6 * 7 * May be copied or modified under the terms of the GNU General Public 8 * License. See linux/COPYING for more information. 9 * 10 */ 11 12 #ifndef _PCI_SH7751_H_ 13 #define _PCI_SH7751_H_ 14 15 /* Platform Specific Values */ 16 #define SH7751_VENDOR_ID 0x1054 17 #define SH7751_DEVICE_ID 0x3505 18 #define SH7751R_DEVICE_ID 0x350e 19 20 /* SH7751 Specific Values */ 21 #define SH7751_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */ 22 #define SH7751_PCI_CONFIG_SIZE 0x1000000 /* Config space size */ 23 #define SH7751_PCI_MEMORY_BASE 0xFD000000 /* Memory space base addr */ 24 #define SH7751_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */ 25 #define SH7751_PCI_IO_BASE 0xFE240000 /* IO space base address */ 26 #define SH7751_PCI_IO_SIZE 0x40000 /* Size of IO window */ 27 28 #define SH7751_PCIREG_BASE 0xFE200000 /* PCI regs base address */ 29 #define PCI_REG(n) (SH7751_PCIREG_BASE+ n) 30 31 #define SH7751_PCICONF0 0x0 /* PCI Config Reg 0 */ 32 #define SH7751_PCICONF0_DEVID 0xFFFF0000 /* Device ID */ 33 #define SH7751_PCICONF0_VNDID 0x0000FFFF /* Vendor ID */ 34 #define SH7751_PCICONF1 0x4 /* PCI Config Reg 1 */ 35 #define SH7751_PCICONF1_DPE 0x80000000 /* Data Parity Error */ 36 #define SH7751_PCICONF1_SSE 0x40000000 /* System Error Status */ 37 #define SH7751_PCICONF1_RMA 0x20000000 /* Master Abort */ 38 #define SH7751_PCICONF1_RTA 0x10000000 /* Target Abort Rx Status */ 39 #define SH7751_PCICONF1_STA 0x08000000 /* Target Abort Exec Status */ 40 #define SH7751_PCICONF1_DEV 0x06000000 /* Timing Status */ 41 #define SH7751_PCICONF1_DPD 0x01000000 /* Data Parity Status */ 42 #define SH7751_PCICONF1_FBBC 0x00800000 /* Back 2 Back Status */ 43 #define SH7751_PCICONF1_UDF 0x00400000 /* User Defined Status */ 44 #define SH7751_PCICONF1_66M 0x00200000 /* 66Mhz Operation Status */ 45 #define SH7751_PCICONF1_PM 0x00100000 /* Power Management Status */ 46 #define SH7751_PCICONF1_PBBE 0x00000200 /* Back 2 Back Control */ 47 #define SH7751_PCICONF1_SER 0x00000100 /* SERR Output Control */ 48 #define SH7751_PCICONF1_WCC 0x00000080 /* Wait Cycle Control */ 49 #define SH7751_PCICONF1_PER 0x00000040 /* Parity Error Response */ 50 #define SH7751_PCICONF1_VPS 0x00000020 /* VGA Pallet Snoop */ 51 #define SH7751_PCICONF1_MWIE 0x00000010 /* Memory Write+Invalidate */ 52 #define SH7751_PCICONF1_SPC 0x00000008 /* Special Cycle Control */ 53 #define SH7751_PCICONF1_BUM 0x00000004 /* Bus Master Control */ 54 #define SH7751_PCICONF1_MES 0x00000002 /* Memory Space Control */ 55 #define SH7751_PCICONF1_IOS 0x00000001 /* I/O Space Control */ 56 #define SH7751_PCICONF2 0x8 /* PCI Config Reg 2 */ 57 #define SH7751_PCICONF2_BCC 0xFF000000 /* Base Class Code */ 58 #define SH7751_PCICONF2_SCC 0x00FF0000 /* Sub-Class Code */ 59 #define SH7751_PCICONF2_RLPI 0x0000FF00 /* Programming Interface */ 60 #define SH7751_PCICONF2_REV 0x000000FF /* Revision ID */ 61 #define SH7751_PCICONF3 0xC /* PCI Config Reg 3 */ 62 #define SH7751_PCICONF3_BIST7 0x80000000 /* Bist Supported */ 63 #define SH7751_PCICONF3_BIST6 0x40000000 /* Bist Executing */ 64 #define SH7751_PCICONF3_BIST3_0 0x0F000000 /* Bist Passed */ 65 #define SH7751_PCICONF3_HD7 0x00800000 /* Single Funtion device */ 66 #define SH7751_PCICONF3_HD6_0 0x007F0000 /* Configuration Layout */ 67 #define SH7751_PCICONF3_LAT 0x0000FF00 /* Latency Timer */ 68 #define SH7751_PCICONF3_CLS 0x000000FF /* Cache Line Size */ 69 #define SH7751_PCICONF4 0x10 /* PCI Config Reg 4 */ 70 #define SH7751_PCICONF4_BASE 0xFFFFFFFC /* I/O Space Base Addr */ 71 #define SH7751_PCICONF4_ASI 0x00000001 /* Address Space Type */ 72 #define SH7751_PCICONF5 0x14 /* PCI Config Reg 5 */ 73 #define SH7751_PCICONF5_BASE 0xFFFFFFF0 /* Mem Space Base Addr */ 74 #define SH7751_PCICONF5_LAP 0x00000008 /* Prefetch Enabled */ 75 #define SH7751_PCICONF5_LAT 0x00000006 /* Local Memory type */ 76 #define SH7751_PCICONF5_ASI 0x00000001 /* Address Space Type */ 77 #define SH7751_PCICONF6 0x18 /* PCI Config Reg 6 */ 78 #define SH7751_PCICONF6_BASE 0xFFFFFFF0 /* Mem Space Base Addr */ 79 #define SH7751_PCICONF6_LAP 0x00000008 /* Prefetch Enabled */ 80 #define SH7751_PCICONF6_LAT 0x00000006 /* Local Memory type */ 81 #define SH7751_PCICONF6_ASI 0x00000001 /* Address Space Type */ 82 /* PCICONF7 - PCICONF10 are undefined */ 83 #define SH7751_PCICONF11 0x2C /* PCI Config Reg 11 */ 84 #define SH7751_PCICONF11_SSID 0xFFFF0000 /* Subsystem ID */ 85 #define SH7751_PCICONF11_SVID 0x0000FFFF /* Subsystem Vendor ID */ 86 /* PCICONF12 is undefined */ 87 #define SH7751_PCICONF13 0x34 /* PCI Config Reg 13 */ 88 #define SH7751_PCICONF13_CPTR 0x000000FF /* PM function pointer */ 89 /* PCICONF14 is undefined */ 90 #define SH7751_PCICONF15 0x3C /* PCI Config Reg 15 */ 91 #define SH7751_PCICONF15_IPIN 0x000000FF /* Interrupt Pin */ 92 #define SH7751_PCICONF16 0x40 /* PCI Config Reg 16 */ 93 #define SH7751_PCICONF16_PMES 0xF8000000 /* PME Support */ 94 #define SH7751_PCICONF16_D2S 0x04000000 /* D2 Support */ 95 #define SH7751_PCICONF16_D1S 0x02000000 /* D1 Support */ 96 #define SH7751_PCICONF16_DSI 0x00200000 /* Bit Device Init. */ 97 #define SH7751_PCICONF16_PMCK 0x00080000 /* Clock for PME req. */ 98 #define SH7751_PCICONF16_VER 0x00070000 /* PM Version */ 99 #define SH7751_PCICONF16_NIP 0x0000FF00 /* Next Item Pointer */ 100 #define SH7751_PCICONF16_CID 0x000000FF /* Capability Identifier */ 101 #define SH7751_PCICONF17 0x44 /* PCI Config Reg 17 */ 102 #define SH7751_PCICONF17_DATA 0xFF000000 /* Data field for PM */ 103 #define SH7751_PCICONF17_PMES 0x00800000 /* PME Status */ 104 #define SH7751_PCICONF17_DSCL 0x00600000 /* Data Scaling Value */ 105 #define SH7751_PCICONF17_DSEL 0x001E0000 /* Data Select */ 106 #define SH7751_PCICONF17_PMEN 0x00010000 /* PME Enable */ 107 #define SH7751_PCICONF17_PWST 0x00000003 /* Power State */ 108 /* SH7715 Internal PCI Registers */ 109 110 /* Memory Control Registers */ 111 #define SH7751_BCR1 0xFF800000 /* Memory BCR1 Register */ 112 #define SH7751_BCR2 0xFF800004 /* Memory BCR2 Register */ 113 #define SH7751_BCR3 0xFF800050 /* Memory BCR3 Register */ 114 #define SH7751_BCR4 0xFE0A00F0 /* Memory BCR4 Register */ 115 #define SH7751_WCR1 0xFF800008 /* Wait Control 1 Register */ 116 #define SH7751_WCR2 0xFF80000C /* Wait Control 2 Register */ 117 #define SH7751_WCR3 0xFF800010 /* Wait Control 3 Register */ 118 #define SH7751_MCR 0xFF800014 /* Memory Control Register */ 119 120 /* General Memory Config Addresses */ 121 #define SH7751_CS0_BASE_ADDR 0x0 122 #define SH7751_MEM_REGION_SIZE 0x04000000 123 #define SH7751_CS1_BASE_ADDR (SH7751_CS0_BASE_ADDR + SH7751_MEM_REGION_SIZE) 124 #define SH7751_CS2_BASE_ADDR (SH7751_CS1_BASE_ADDR + SH7751_MEM_REGION_SIZE) 125 #define SH7751_CS3_BASE_ADDR (SH7751_CS2_BASE_ADDR + SH7751_MEM_REGION_SIZE) 126 #define SH7751_CS4_BASE_ADDR (SH7751_CS3_BASE_ADDR + SH7751_MEM_REGION_SIZE) 127 #define SH7751_CS5_BASE_ADDR (SH7751_CS4_BASE_ADDR + SH7751_MEM_REGION_SIZE) 128 #define SH7751_CS6_BASE_ADDR (SH7751_CS5_BASE_ADDR + SH7751_MEM_REGION_SIZE) 129 130 struct sh4_pci_address_map; 131 132 /* arch/sh/drivers/pci/pci-sh7751.c */ 133 int sh7751_pcic_init(struct sh4_pci_address_map *map); 134 135 #endif /* _PCI_SH7751_H_ */ 136