1 /* 2 * linux/include/asm/traps.h 3 * 4 * Copyright (C) 1993 Hamish Macdonald 5 * 6 * Lineo, Inc Jul 2001 Tony Kou 7 * 8 * This file is subject to the terms and conditions of the GNU General Public 9 * License. See the file COPYING in the main directory of this archive 10 * for more details. 11 */ 12 13 #ifndef _BFIN_TRAPS_H 14 #define _BFIN_TRAPS_H 15 16 #define VEC_SYS (0) 17 #define VEC_EXCPT01 (1) 18 #define VEC_EXCPT02 (2) 19 #define VEC_EXCPT03 (3) 20 #define VEC_EXCPT04 (4) 21 #define VEC_EXCPT05 (5) 22 #define VEC_EXCPT06 (6) 23 #define VEC_EXCPT07 (7) 24 #define VEC_EXCPT08 (8) 25 #define VEC_EXCPT09 (9) 26 #define VEC_EXCPT10 (10) 27 #define VEC_EXCPT11 (11) 28 #define VEC_EXCPT12 (12) 29 #define VEC_EXCPT13 (13) 30 #define VEC_EXCPT14 (14) 31 #define VEC_EXCPT15 (15) 32 #define VEC_STEP (16) 33 #define VEC_OVFLOW (17) 34 #define VEC_UNDEF_I (33) 35 #define VEC_ILGAL_I (34) 36 #define VEC_CPLB_VL (35) 37 #define VEC_MISALI_D (36) 38 #define VEC_UNCOV (37) 39 #define VEC_CPLB_M (38) 40 #define VEC_CPLB_MHIT (39) 41 #define VEC_WATCH (40) 42 #define VEC_ISTRU_VL (41) /*ADSP-BF535 only (MH) */ 43 #define VEC_MISALI_I (42) 44 #define VEC_CPLB_I_VL (43) 45 #define VEC_CPLB_I_M (44) 46 #define VEC_CPLB_I_MHIT (45) 47 #define VEC_ILL_RES (46) /* including unvalid supervisor mode insn */ 48 /* The hardware reserves (63) for future use - we use it to tell our 49 * normal exception handling code we have a hardware error 50 */ 51 #define VEC_HWERR (63) 52 53 #ifndef __ASSEMBLY__ 54 55 #define HWC_x2(level) \ 56 "System MMR Error\n" \ 57 level " - An error occurred due to an invalid access to an System MMR location\n" \ 58 level " Possible reason: a 32-bit register is accessed with a 16-bit instruction\n" \ 59 level " or a 16-bit register is accessed with a 32-bit instruction.\n" 60 #define HWC_x3(level) \ 61 "External Memory Addressing Error\n" 62 #define EXC_0x04(level) \ 63 "Unimplmented exception occured\n" \ 64 level " - Maybe you forgot to install a custom exception handler?\n" 65 #define HWC_x12(level) \ 66 "Performance Monitor Overflow\n" 67 #define HWC_x18(level) \ 68 "RAISE 5 instruction\n" \ 69 level " Software issued a RAISE 5 instruction to invoke the Hardware\n" 70 #define HWC_default(level) \ 71 "Reserved\n" 72 #define EXC_0x03(level) \ 73 "Application stack overflow\n" \ 74 level " - Please increase the stack size of the application using elf2flt -s option,\n" \ 75 level " and/or reduce the stack use of the application.\n" 76 #define EXC_0x10(level) \ 77 "Single step\n" \ 78 level " - When the processor is in single step mode, every instruction\n" \ 79 level " generates an exception. Primarily used for debugging.\n" 80 #define EXC_0x11(level) \ 81 "Exception caused by a trace buffer full condition\n" \ 82 level " - The processor takes this exception when the trace\n" \ 83 level " buffer overflows (only when enabled by the Trace Unit Control register).\n" 84 #define EXC_0x21(level) \ 85 "Undefined instruction\n" \ 86 level " - May be used to emulate instructions that are not defined for\n" \ 87 level " a particular processor implementation.\n" 88 #define EXC_0x22(level) \ 89 "Illegal instruction combination\n" \ 90 level " - See section for multi-issue rules in the Blackfin\n" \ 91 level " Processor Instruction Set Reference.\n" 92 #define EXC_0x23(level) \ 93 "Data access CPLB protection violation\n" \ 94 level " - Attempted read or write to Supervisor resource,\n" \ 95 level " or illegal data memory access. \n" 96 #define EXC_0x24(level) \ 97 "Data access misaligned address violation\n" \ 98 level " - Attempted misaligned data memory or data cache access.\n" 99 #define EXC_0x25(level) \ 100 "Unrecoverable event\n" \ 101 level " - For example, an exception generated while processing a previous exception.\n" 102 #define EXC_0x26(level) \ 103 "Data access CPLB miss\n" \ 104 level " - Used by the MMU to signal a CPLB miss on a data access.\n" 105 #define EXC_0x27(level) \ 106 "Data access multiple CPLB hits\n" \ 107 level " - More than one CPLB entry matches data fetch address.\n" 108 #define EXC_0x28(level) \ 109 "Program Sequencer Exception caused by an emulation watchpoint match\n" \ 110 level " - There is a watchpoint match, and one of the EMUSW\n" \ 111 level " bits in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n" 112 #define EXC_0x2A(level) \ 113 "Instruction fetch misaligned address violation\n" \ 114 level " - Attempted misaligned instruction cache fetch. On a misaligned instruction fetch\n" \ 115 level " exception, the return address provided in RETX is the destination address which is\n" \ 116 level " misaligned, rather than the address of the offending instruction.\n" 117 #define EXC_0x2B(level) \ 118 "CPLB protection violation\n" \ 119 level " - Illegal instruction fetch access (memory protection violation).\n" 120 #define EXC_0x2C(level) \ 121 "Instruction fetch CPLB miss\n" \ 122 level " - CPLB miss on an instruction fetch.\n" 123 #define EXC_0x2D(level) \ 124 "Instruction fetch multiple CPLB hits\n" \ 125 level " - More than one CPLB entry matches instruction fetch address.\n" 126 #define EXC_0x2E(level) \ 127 "Illegal use of supervisor resource\n" \ 128 level " - Attempted to use a Supervisor register or instruction from User mode.\n" \ 129 level " Supervisor resources are registers and instructions that are reserved\n" \ 130 level " for Supervisor use: Supervisor only registers, all MMRs, and Supervisor\n" \ 131 level " only instructions.\n" 132 133 #endif /* __ASSEMBLY__ */ 134 #endif /* _BFIN_TRAPS_H */ 135