1 /* Copyright (C) 1999,2001 2 * 3 * Author: J.E.J.Bottomley@HansenPartnership.com 4 * 5 * Standard include definitions for the NCR Voyager Interrupt Controller */ 6 7 /* The eight CPI vectors. To activate a CPI, you write a bit mask 8 * corresponding to the processor set to be interrupted into the 9 * relevant register. That set of CPUs will then be interrupted with 10 * the CPI */ 11 static const int VIC_CPI_Registers[] = 12 {0xFC00, 0xFC01, 0xFC08, 0xFC09, 13 0xFC10, 0xFC11, 0xFC18, 0xFC19 }; 14 15 #define VIC_PROC_WHO_AM_I 0xfc29 16 # define QUAD_IDENTIFIER 0xC0 17 # define EIGHT_SLOT_IDENTIFIER 0xE0 18 #define QIC_EXTENDED_PROCESSOR_SELECT 0xFC72 19 #define VIC_CPI_BASE_REGISTER 0xFC41 20 #define VIC_PROCESSOR_ID 0xFC21 21 # define VIC_CPU_MASQUERADE_ENABLE 0x8 22 23 #define VIC_CLAIM_REGISTER_0 0xFC38 24 #define VIC_CLAIM_REGISTER_1 0xFC39 25 #define VIC_REDIRECT_REGISTER_0 0xFC60 26 #define VIC_REDIRECT_REGISTER_1 0xFC61 27 #define VIC_PRIORITY_REGISTER 0xFC20 28 29 #define VIC_PRIMARY_MC_BASE 0xFC48 30 #define VIC_SECONDARY_MC_BASE 0xFC49 31 32 #define QIC_PROCESSOR_ID 0xFC71 33 # define QIC_CPUID_ENABLE 0x08 34 35 #define QIC_VIC_CPI_BASE_REGISTER 0xFC79 36 #define QIC_CPI_BASE_REGISTER 0xFC7A 37 38 #define QIC_MASK_REGISTER0 0xFC80 39 /* NOTE: these are masked high, enabled low */ 40 # define QIC_PERF_TIMER 0x01 41 # define QIC_LPE 0x02 42 # define QIC_SYS_INT 0x04 43 # define QIC_CMN_INT 0x08 44 /* at the moment, just enable CMN_INT, disable SYS_INT */ 45 # define QIC_DEFAULT_MASK0 (~(QIC_CMN_INT /* | VIC_SYS_INT */)) 46 #define QIC_MASK_REGISTER1 0xFC81 47 # define QIC_BOOT_CPI_MASK 0xFE 48 /* Enable CPI's 1-6 inclusive */ 49 # define QIC_CPI_ENABLE 0x81 50 51 #define QIC_INTERRUPT_CLEAR0 0xFC8A 52 #define QIC_INTERRUPT_CLEAR1 0xFC8B 53 54 /* this is where we place the CPI vectors */ 55 #define VIC_DEFAULT_CPI_BASE 0xC0 56 /* this is where we place the QIC CPI vectors */ 57 #define QIC_DEFAULT_CPI_BASE 0xD0 58 59 #define VIC_BOOT_INTERRUPT_MASK 0xfe 60 61 extern void smp_vic_timer_interrupt(void); 62