1 /*
2 * Athlon specific Machine Check Exception Reporting
3 * (C) Copyright 2002 Dave Jones <davej@redhat.com>
4 */
5
6 #include <linux/init.h>
7 #include <linux/types.h>
8 #include <linux/kernel.h>
9 #include <linux/interrupt.h>
10 #include <linux/smp.h>
11
12 #include <asm/processor.h>
13 #include <asm/system.h>
14 #include <asm/msr.h>
15
16 #include "mce.h"
17
18 /* Machine Check Handler For AMD Athlon/Duron */
k7_machine_check(struct pt_regs * regs,long error_code)19 static void k7_machine_check(struct pt_regs *regs, long error_code)
20 {
21 int recover = 1;
22 u32 alow, ahigh, high, low;
23 u32 mcgstl, mcgsth;
24 int i;
25
26 rdmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
27 if (mcgstl & (1<<0)) /* Recoverable ? */
28 recover = 0;
29
30 printk(KERN_EMERG "CPU %d: Machine Check Exception: %08x%08x\n",
31 smp_processor_id(), mcgsth, mcgstl);
32
33 for (i = 1; i < nr_mce_banks; i++) {
34 rdmsr(MSR_IA32_MC0_STATUS+i*4, low, high);
35 if (high&(1<<31)) {
36 char misc[20];
37 char addr[24];
38 misc[0] = addr[0] = '\0';
39 if (high & (1<<29))
40 recover |= 1;
41 if (high & (1<<25))
42 recover |= 2;
43 high &= ~(1<<31);
44 if (high & (1<<27)) {
45 rdmsr(MSR_IA32_MC0_MISC+i*4, alow, ahigh);
46 snprintf(misc, 20, "[%08x%08x]", ahigh, alow);
47 }
48 if (high & (1<<26)) {
49 rdmsr(MSR_IA32_MC0_ADDR+i*4, alow, ahigh);
50 snprintf(addr, 24, " at %08x%08x", ahigh, alow);
51 }
52 printk(KERN_EMERG "CPU %d: Bank %d: %08x%08x%s%s\n",
53 smp_processor_id(), i, high, low, misc, addr);
54 /* Clear it */
55 wrmsr(MSR_IA32_MC0_STATUS+i*4, 0UL, 0UL);
56 /* Serialize */
57 wmb();
58 add_taint(TAINT_MACHINE_CHECK);
59 }
60 }
61
62 if (recover&2)
63 panic("CPU context corrupt");
64 if (recover&1)
65 panic("Unable to continue");
66 printk(KERN_EMERG "Attempting to continue.\n");
67 mcgstl &= ~(1<<2);
68 wrmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
69 }
70
71
72 /* AMD K7 machine check is Intel like */
amd_mcheck_init(struct cpuinfo_x86 * c)73 void amd_mcheck_init(struct cpuinfo_x86 *c)
74 {
75 u32 l, h;
76 int i;
77
78 if (!cpu_has(c, X86_FEATURE_MCE))
79 return;
80
81 machine_check_vector = k7_machine_check;
82 wmb();
83
84 printk(KERN_INFO "Intel machine check architecture supported.\n");
85 rdmsr(MSR_IA32_MCG_CAP, l, h);
86 if (l & (1<<8)) /* Control register present ? */
87 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
88 nr_mce_banks = l & 0xff;
89
90 /* Clear status for MC index 0 separately, we don't touch CTL,
91 * as some K7 Athlons cause spurious MCEs when its enabled. */
92 if (boot_cpu_data.x86 == 6) {
93 wrmsr(MSR_IA32_MC0_STATUS, 0x0, 0x0);
94 i = 1;
95 } else
96 i = 0;
97 for (; i < nr_mce_banks; i++) {
98 wrmsr(MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff);
99 wrmsr(MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0);
100 }
101
102 set_in_cr4(X86_CR4_MCE);
103 printk(KERN_INFO "Intel machine check reporting enabled on CPU#%d.\n",
104 smp_processor_id());
105 }
106