1 /**
2 * Airgo MIMO wireless driver
3 *
4 * Copyright (c) 2007 Li YanBo <dreamfly281@gmail.com>
5
6 * Thanks for Jeff Williams <angelbane@gmail.com> do reverse engineer
7 * works and published the SPECS at http://airgo.wdwconsulting.net/mymoin
8
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation;
12 */
13
14 #include <linux/pci.h>
15 #include <linux/delay.h>
16 #include "agnx.h"
17 #include "debug.h"
18 #include "phy.h"
19 #include "table.h"
20
21 /* FIXME! */
spi_write(void __iomem * region,u32 chip_ids,u32 sw,u16 size,u32 control)22 static inline void spi_write(void __iomem *region, u32 chip_ids, u32 sw,
23 u16 size, u32 control)
24 {
25 u32 reg;
26 u32 lsw = sw & 0xffff; /* lower 16 bits of sw*/
27 u32 msw = sw >> 16; /* high 16 bits of sw */
28
29 /* FIXME Write Most Significant Word of the 32bit data to MSW */
30 /* FIXME And Least Significant Word to LSW */
31 iowrite32((lsw), region + AGNX_SPI_WLSW);
32 iowrite32((msw), region + AGNX_SPI_WMSW);
33 reg = chip_ids | size | control;
34 /* Write chip id(s), write size and busy control to Control Register */
35 iowrite32((reg), region + AGNX_SPI_CTL);
36 /* Wait for Busy control to clear */
37 spi_delay();
38 }
39
40 /*
41 * Write to SPI Synth register
42 */
spi_sy_write(void __iomem * region,u32 chip_ids,u32 sw)43 static inline void spi_sy_write(void __iomem *region, u32 chip_ids, u32 sw)
44 {
45 /* FIXME the size 0x15 is a magic value*/
46 spi_write(region, chip_ids, sw, 0x15, SPI_BUSY_CTL);
47 }
48
49 /*
50 * Write to SPI RF register
51 */
spi_rf_write(void __iomem * region,u32 chip_ids,u32 sw)52 static inline void spi_rf_write(void __iomem *region, u32 chip_ids, u32 sw)
53 {
54 /* FIXME the size 0xd is a magic value*/
55 spi_write(region, chip_ids, sw, 0xd, SPI_BUSY_CTL);
56 } /* spi_rf_write */
57
58 /*
59 * Write to SPI with Read Control bit set
60 */
spi_rc_write(void __iomem * region,u32 chip_ids,u32 sw)61 inline void spi_rc_write(void __iomem *region, u32 chip_ids, u32 sw)
62 {
63 /* FIXME the size 0xe5 is a magic value */
64 spi_write(region, chip_ids, sw, 0xe5, SPI_BUSY_CTL|SPI_READ_CTL);
65 }
66
67 /* Get the active chains's count */
get_active_chains(struct agnx_priv * priv)68 static int get_active_chains(struct agnx_priv *priv)
69 {
70 void __iomem *ctl = priv->ctl;
71 int num = 0;
72 u32 reg;
73 AGNX_TRACE;
74
75 spi_rc_write(ctl, RF_CHIP0, 0x21);
76 reg = agnx_read32(ctl, AGNX_SPI_RLSW);
77 if (reg == 1)
78 num++;
79
80 spi_rc_write(ctl, RF_CHIP1, 0x21);
81 reg = agnx_read32(ctl, AGNX_SPI_RLSW);
82 if (reg == 1)
83 num++;
84
85 spi_rc_write(ctl, RF_CHIP2, 0x21);
86 reg = agnx_read32(ctl, AGNX_SPI_RLSW);
87 if (reg == 1)
88 num++;
89
90 spi_rc_write(ctl, RF_CHIP0, 0x26);
91 reg = agnx_read32(ctl, AGNX_SPI_RLSW);
92 if (0x33 != reg)
93 printk(KERN_WARNING PFX "Unmatched rf chips result\n");
94
95 return num;
96 } /* get_active_chains */
97
rf_chips_init(struct agnx_priv * priv)98 void rf_chips_init(struct agnx_priv *priv)
99 {
100 void __iomem *ctl = priv->ctl;
101 u32 reg;
102 int num;
103 AGNX_TRACE;
104
105 if (priv->revid == 1) {
106 reg = agnx_read32(ctl, AGNX_SYSITF_GPIOUT);
107 reg |= 0x8;
108 agnx_write32(ctl, AGNX_SYSITF_GPIOUT, reg);
109 }
110
111 /* Set SPI clock speed to 200NS */
112 reg = agnx_read32(ctl, AGNX_SPI_CFG);
113 reg &= ~0xF;
114 reg |= 0x3;
115 agnx_write32(ctl, AGNX_SPI_CFG, reg);
116
117 /* Set SPI clock speed to 50NS */
118 reg = agnx_read32(ctl, AGNX_SPI_CFG);
119 reg &= ~0xF;
120 reg |= 0x1;
121 agnx_write32(ctl, AGNX_SPI_CFG, reg);
122
123 spi_rf_write(ctl, RF_CHIP0|RF_CHIP1|RF_CHIP2, 0x1101);
124
125 num = get_active_chains(priv);
126 printk(KERN_INFO PFX "Active chains are %d\n", num);
127
128 reg = agnx_read32(ctl, AGNX_SPI_CFG);
129 reg &= ~0xF;
130 agnx_write32(ctl, AGNX_SPI_CFG, reg);
131
132 spi_rf_write(ctl, RF_CHIP0|RF_CHIP1|RF_CHIP2, 0x1908);
133 } /* rf_chips_init */
134
135
136 static u32 channel_tbl[15][9] = {
137 {0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
138 {1, 0x00, 0x00, 0x624, 0x00, 0x1a4, 0x28, 0x00, 0x1e},
139 {2, 0x00, 0x00, 0x615, 0x00, 0x1ae, 0x28, 0x00, 0x1e},
140 {3, 0x00, 0x00, 0x61a, 0x00, 0x1ae, 0x28, 0x00, 0x1e},
141 {4, 0x00, 0x00, 0x61f, 0x00, 0x1ae, 0x28, 0x00, 0x1e},
142 {5, 0x00, 0x00, 0x624, 0x00, 0x1ae, 0x28, 0x00, 0x1e},
143 {6, 0x00, 0x00, 0x61f, 0x00, 0x1b3, 0x28, 0x00, 0x1e},
144 {7, 0x00, 0x00, 0x624, 0x00, 0x1b3, 0x28, 0x00, 0x1e},
145 {8, 0x00, 0x00, 0x629, 0x00, 0x1b3, 0x28, 0x00, 0x1e},
146 {9, 0x00, 0x00, 0x624, 0x00, 0x1b8, 0x28, 0x00, 0x1e},
147 {10, 0x00, 0x00, 0x629, 0x00, 0x1b8, 0x28, 0x00, 0x1e},
148 {11, 0x00, 0x00, 0x62e, 0x00, 0x1b8, 0x28, 0x00, 0x1e},
149 {12, 0x00, 0x00, 0x633, 0x00, 0x1b8, 0x28, 0x00, 0x1e},
150 {13, 0x00, 0x00, 0x628, 0x00, 0x1b8, 0x28, 0x00, 0x1e},
151 {14, 0x00, 0x00, 0x644, 0x00, 0x1b8, 0x28, 0x00, 0x1e},
152 };
153
154
155 static inline void
channel_tbl_write(struct agnx_priv * priv,unsigned int channel,unsigned int reg_num)156 channel_tbl_write(struct agnx_priv *priv, unsigned int channel, unsigned int reg_num)
157 {
158 void __iomem *ctl = priv->ctl;
159 u32 reg;
160
161 reg = channel_tbl[channel][reg_num];
162 reg <<= 4;
163 reg |= reg_num;
164 spi_sy_write(ctl, SYNTH_CHIP, reg);
165 }
166
synth_freq_set(struct agnx_priv * priv,unsigned int channel)167 static void synth_freq_set(struct agnx_priv *priv, unsigned int channel)
168 {
169 void __iomem *ctl = priv->ctl;
170 u32 reg;
171 AGNX_TRACE;
172
173 spi_rf_write(ctl, RF_CHIP0|RF_CHIP1, 0x1201);
174
175 /* Set the Clock bits to 50NS */
176 reg = agnx_read32(ctl, AGNX_SPI_CFG);
177 reg &= ~0xF;
178 reg |= 0x1;
179 agnx_write32(ctl, AGNX_SPI_CFG, reg);
180
181 /* Write 0x00c0 to LSW and 0x3 to MSW of Synth Chip */
182 spi_sy_write(ctl, SYNTH_CHIP, 0x300c0);
183
184 spi_sy_write(ctl, SYNTH_CHIP, 0x32);
185
186 /* # Write to Register 1 on the Synth Chip */
187 channel_tbl_write(priv, channel, 1);
188 /* # Write to Register 3 on the Synth Chip */
189 channel_tbl_write(priv, channel, 3);
190 /* # Write to Register 6 on the Synth Chip */
191 channel_tbl_write(priv, channel, 6);
192 /* # Write to Register 5 on the Synth Chip */
193 channel_tbl_write(priv, channel, 5);
194 /* # Write to register 8 on the Synth Chip */
195 channel_tbl_write(priv, channel, 8);
196
197 /* FIXME Clear the clock bits */
198 reg = agnx_read32(ctl, AGNX_SPI_CFG);
199 reg &= ~0xf;
200 agnx_write32(ctl, AGNX_SPI_CFG, reg);
201 } /* synth_chip_init */
202
203
antenna_init(struct agnx_priv * priv,int num_antenna)204 static void antenna_init(struct agnx_priv *priv, int num_antenna)
205 {
206 void __iomem *ctl = priv->ctl;
207
208 switch (num_antenna) {
209 case 1:
210 agnx_write32(ctl, AGNX_GCR_NLISTANT, 1);
211 agnx_write32(ctl, AGNX_GCR_NMEASANT, 1);
212 agnx_write32(ctl, AGNX_GCR_NACTIANT, 1);
213 agnx_write32(ctl, AGNX_GCR_NCAPTANT, 1);
214
215 agnx_write32(ctl, AGNX_GCR_ANTCFG, 7);
216 agnx_write32(ctl, AGNX_GCR_BOACT, 34);
217 agnx_write32(ctl, AGNX_GCR_BOINACT, 34);
218 agnx_write32(ctl, AGNX_GCR_BODYNA, 30);
219
220 agnx_write32(ctl, AGNX_GCR_THD0A, 125);
221 agnx_write32(ctl, AGNX_GCR_THD0AL, 100);
222 agnx_write32(ctl, AGNX_GCR_THD0B, 90);
223
224 agnx_write32(ctl, AGNX_GCR_THD0BTFEST, 80);
225 agnx_write32(ctl, AGNX_GCR_SIGHTH, 100);
226 agnx_write32(ctl, AGNX_GCR_SIGLTH, 16);
227 break;
228 case 2:
229 agnx_write32(ctl, AGNX_GCR_NLISTANT, 2);
230 agnx_write32(ctl, AGNX_GCR_NMEASANT, 2);
231 agnx_write32(ctl, AGNX_GCR_NACTIANT, 2);
232 agnx_write32(ctl, AGNX_GCR_NCAPTANT, 2);
233 agnx_write32(ctl, AGNX_GCR_ANTCFG, 15);
234 agnx_write32(ctl, AGNX_GCR_BOACT, 36);
235 agnx_write32(ctl, AGNX_GCR_BOINACT, 36);
236 agnx_write32(ctl, AGNX_GCR_BODYNA, 32);
237 agnx_write32(ctl, AGNX_GCR_THD0A, 120);
238 agnx_write32(ctl, AGNX_GCR_THD0AL, 100);
239 agnx_write32(ctl, AGNX_GCR_THD0B, 80);
240 agnx_write32(ctl, AGNX_GCR_THD0BTFEST, 70);
241 agnx_write32(ctl, AGNX_GCR_SIGHTH, 100);
242 agnx_write32(ctl, AGNX_GCR_SIGLTH, 32);
243 break;
244 case 3:
245 agnx_write32(ctl, AGNX_GCR_NLISTANT, 3);
246 agnx_write32(ctl, AGNX_GCR_NMEASANT, 3);
247 agnx_write32(ctl, AGNX_GCR_NACTIANT, 3);
248 agnx_write32(ctl, AGNX_GCR_NCAPTANT, 3);
249 agnx_write32(ctl, AGNX_GCR_ANTCFG, 31);
250 agnx_write32(ctl, AGNX_GCR_BOACT, 36);
251 agnx_write32(ctl, AGNX_GCR_BOINACT, 36);
252 agnx_write32(ctl, AGNX_GCR_BODYNA, 32);
253 agnx_write32(ctl, AGNX_GCR_THD0A, 100);
254 agnx_write32(ctl, AGNX_GCR_THD0AL, 100);
255 agnx_write32(ctl, AGNX_GCR_THD0B, 70);
256 agnx_write32(ctl, AGNX_GCR_THD0BTFEST, 70);
257 agnx_write32(ctl, AGNX_GCR_SIGHTH, 100);
258 agnx_write32(ctl, AGNX_GCR_SIGLTH, 48);
259 // agnx_write32(ctl, AGNX_GCR_SIGLTH, 16);
260 break;
261 default:
262 printk(KERN_WARNING PFX "Unknow antenna number\n");
263 }
264 } /* antenna_init */
265
chain_update(struct agnx_priv * priv,u32 chain)266 static void chain_update(struct agnx_priv *priv, u32 chain)
267 {
268 void __iomem *ctl = priv->ctl;
269 u32 reg;
270 AGNX_TRACE;
271
272 spi_rc_write(ctl, RF_CHIP0, 0x20);
273 reg = agnx_read32(ctl, AGNX_SPI_RLSW);
274
275 if (reg == 0x4)
276 spi_rf_write(ctl, RF_CHIP0|RF_CHIP1, reg|0x1000);
277 else if (reg != 0x0)
278 spi_rf_write(ctl, RF_CHIP0|RF_CHIP1|RF_CHIP2, reg|0x1000);
279 else {
280 if (chain == 3 || chain == 6) {
281 spi_rf_write(ctl, RF_CHIP0|RF_CHIP1|RF_CHIP2, reg|0x1000);
282 agnx_write32(ctl, AGNX_GCR_RXOVERIDE, 0x0);
283 } else if (chain == 2 || chain == 4) {
284 spi_rf_write(ctl, RF_CHIP0|RF_CHIP1, reg|0x1000);
285 spi_rf_write(ctl, RF_CHIP2, 0x1005);
286 agnx_write32(ctl, AGNX_GCR_RXOVERIDE, 0x824);
287 } else if (chain == 1) {
288 spi_rf_write(ctl, RF_CHIP0, reg|0x1000);
289 spi_rf_write(ctl, RF_CHIP1|RF_CHIP2, 0x1004);
290 agnx_write32(ctl, AGNX_GCR_RXOVERIDE, 0xc36);
291 }
292 }
293
294 spi_rc_write(ctl, RF_CHIP0, 0x22);
295 reg = agnx_read32(ctl, AGNX_SPI_RLSW);
296
297 switch (reg) {
298 case 0:
299 spi_rf_write(ctl, RF_CHIP0|RF_CHIP1|RF_CHIP2, 0x1005);
300 break;
301 case 1:
302 spi_rf_write(ctl, RF_CHIP0|RF_CHIP1, 0x1201);
303 break;
304 case 2:
305 if (chain == 6 || chain == 4) {
306 spi_rf_write(ctl, RF_CHIP0|RF_CHIP1, 0x1202);
307 spi_rf_write(ctl, RF_CHIP2, 0x1005);
308 } else if (chain < 3) {
309 spi_rf_write(ctl, RF_CHIP0, 0x1202);
310 spi_rf_write(ctl, RF_CHIP1|RF_CHIP2, 0x1005);
311 }
312 break;
313 default:
314 if (chain == 3) {
315 spi_rf_write(ctl, RF_CHIP0|RF_CHIP1, 0x1203);
316 spi_rf_write(ctl, RF_CHIP2, 0x1201);
317 } else if (chain == 2) {
318 spi_rf_write(ctl, RF_CHIP0, 0x1203);
319 spi_rf_write(ctl, RF_CHIP2, 0x1200);
320 spi_rf_write(ctl, RF_CHIP1, 0x1201);
321 } else if (chain == 1) {
322 spi_rf_write(ctl, RF_CHIP0, 0x1203);
323 spi_rf_write(ctl, RF_CHIP1|RF_CHIP2, 0x1200);
324 } else if (chain == 4) {
325 spi_rf_write(ctl, RF_CHIP0|RF_CHIP1, 0x1203);
326 spi_rf_write(ctl, RF_CHIP2, 0x1201);
327 } else {
328 spi_rf_write(ctl, RF_CHIP0, 0x1203);
329 spi_rf_write(ctl, RF_CHIP1|RF_CHIP2, 0x1201);
330 }
331 }
332 } /* chain_update */
333
antenna_config(struct agnx_priv * priv)334 static void antenna_config(struct agnx_priv *priv)
335 {
336 void __iomem *ctl = priv->ctl;
337 u32 reg;
338 AGNX_TRACE;
339
340 /* Write 0x0 to the TX Management Control Register Enable bit */
341 reg = agnx_read32(ctl, AGNX_TXM_CTL);
342 reg &= ~0x1;
343 agnx_write32(ctl, AGNX_TXM_CTL, reg);
344
345 /* FIXME */
346 /* Set initial value based on number of Antennae */
347 antenna_init(priv, 3);
348
349 /* FIXME Update Power Templates for current valid Stations */
350 /* sta_power_init(priv, 0);*/
351
352 /* FIXME the number of chains should get from eeprom*/
353 chain_update(priv, AGNX_CHAINS_MAX);
354 } /* antenna_config */
355
calibrate_oscillator(struct agnx_priv * priv)356 void calibrate_oscillator(struct agnx_priv *priv)
357 {
358 void __iomem *ctl = priv->ctl;
359 u32 reg;
360 AGNX_TRACE;
361
362 spi_rc_write(ctl, RF_CHIP0|RF_CHIP1, 0x1201);
363 reg = agnx_read32(ctl, AGNX_GCR_GAINSET1);
364 reg |= 0x10;
365 agnx_write32(ctl, AGNX_GCR_GAINSET1, reg);
366
367 agnx_write32(ctl, AGNX_GCR_GAINSETWRITE, 1);
368 agnx_write32(ctl, AGNX_GCR_RSTGCTL, 1);
369
370 agnx_write32(ctl, AGNX_ACI_LEN, 0x3ff);
371
372 agnx_write32(ctl, AGNX_ACI_TIMER1, 0x27);
373 agnx_write32(ctl, AGNX_ACI_TIMER2, 0x27);
374 /* (Residual DC Calibration) to Calibration Mode */
375 agnx_write32(ctl, AGNX_ACI_MODE, 0x2);
376
377 spi_rc_write(ctl, RF_CHIP0|RF_CHIP1, 0x1004);
378 agnx_write32(ctl, AGNX_ACI_LEN, 0x3ff);
379 /* (TX LO Calibration) to Calibration Mode */
380 agnx_write32(ctl, AGNX_ACI_MODE, 0x4);
381
382 do {
383 u32 reg1, reg2, reg3;
384 /* Enable Power Saving Control */
385 enable_power_saving(priv);
386 /* Save the following registers to restore */
387 reg1 = ioread32(ctl + 0x11000);
388 reg2 = ioread32(ctl + 0xec50);
389 reg3 = ioread32(ctl + 0xec54);
390 wmb();
391
392 agnx_write32(ctl, 0x11000, 0xcfdf);
393 agnx_write32(ctl, 0xec50, 0x70);
394 /* Restore the registers */
395 agnx_write32(ctl, 0x11000, reg1);
396 agnx_write32(ctl, 0xec50, reg2);
397 agnx_write32(ctl, 0xec54, reg3);
398 /* Disable Power Saving Control */
399 disable_power_saving(priv);
400 } while (0);
401
402 agnx_write32(ctl, AGNX_GCR_RSTGCTL, 0);
403 } /* calibrate_oscillator */
404
405
radio_channel_set(struct agnx_priv * priv,unsigned int channel)406 static void radio_channel_set(struct agnx_priv *priv, unsigned int channel)
407 {
408 void __iomem *ctl = priv->ctl;
409 unsigned int freq = priv->band.channels[channel - 1].center_freq;
410 u32 reg;
411 AGNX_TRACE;
412
413 spi_rf_write(ctl, RF_CHIP0|RF_CHIP1, 0x1201);
414 /* Set SPI Clock to 50 Ns */
415 reg = agnx_read32(ctl, AGNX_SPI_CFG);
416 reg &= ~0xF;
417 reg |= 0x1;
418 agnx_write32(ctl, AGNX_SPI_CFG, reg);
419
420 /* Clear the Disable Tx interrupt bit in Interrupt Mask */
421 /* reg = agnx_read32(ctl, AGNX_INT_MASK); */
422 /* reg &= ~IRQ_TX_DISABLE; */
423 /* agnx_write32(ctl, AGNX_INT_MASK, reg); */
424
425 /* Band Selection */
426 reg = agnx_read32(ctl, AGNX_SYSITF_GPIOUT);
427 reg |= 0x8;
428 agnx_write32(ctl, AGNX_SYSITF_GPIOUT, reg);
429
430 /* FIXME Set the SiLabs Chip Frequency */
431 synth_freq_set(priv, channel);
432
433 reg = agnx_read32(ctl, AGNX_PM_SOFTRST);
434 reg |= 0x80100030;
435 agnx_write32(ctl, AGNX_PM_SOFTRST, reg);
436 reg = agnx_read32(ctl, AGNX_PM_PLLCTL);
437 reg |= 0x20009;
438 agnx_write32(ctl, AGNX_PM_PLLCTL, reg);
439
440 agnx_write32(ctl, AGNX_SYSITF_GPIOUT, 0x5);
441
442 spi_rf_write(ctl, RF_CHIP0|RF_CHIP1|RF_CHIP2, 0x1100);
443
444 /* Load the MonitorGain Table */
445 monitor_gain_table_init(priv);
446
447 /* Load the TX Fir table */
448 tx_fir_table_init(priv);
449
450 reg = agnx_read32(ctl, AGNX_PM_PMCTL);
451 reg |= 0x8;
452 agnx_write32(ctl, AGNX_PM_PMCTL, reg);
453
454 spi_rc_write(ctl, RF_CHIP0|RF_CHIP1, 0x22);
455 udelay(80);
456 reg = agnx_read32(ctl, AGNX_SPI_RLSW);
457
458
459 agnx_write32(ctl, AGNX_GCR_RXOVERIDE, 0xff);
460 agnx_write32(ctl, AGNX_GCR_DISCOVMOD, 0x3);
461
462 reg = agnx_read32(ctl, 0xec50);
463 reg |= 0x4f;
464 agnx_write32(ctl, 0xec50, reg);
465
466 spi_rf_write(ctl, RF_CHIP0|RF_CHIP1, 0x1201);
467 agnx_write32(ctl, 0x11008, 0x1);
468 agnx_write32(ctl, 0x1100c, 0x0);
469 agnx_write32(ctl, 0x11008, 0x0);
470 agnx_write32(ctl, 0xec50, 0xc);
471
472 agnx_write32(ctl, AGNX_GCR_DISCOVMOD, 0x3);
473 agnx_write32(ctl, AGNX_GCR_RXOVERIDE, 0x0);
474 agnx_write32(ctl, 0x11010, 0x6e);
475 agnx_write32(ctl, 0x11014, 0x6c);
476
477 spi_rf_write(ctl, RF_CHIP0|RF_CHIP1, 0x1201);
478
479 /* Calibrate the Antenna */
480 /* antenna_calibrate(priv); */
481 /* Calibrate the TxLocalOscillator */
482 calibrate_oscillator(priv);
483
484 reg = agnx_read32(ctl, AGNX_PM_PMCTL);
485 reg &= ~0x8;
486 agnx_write32(ctl, AGNX_PM_PMCTL, reg);
487 agnx_write32(ctl, AGNX_GCR_GAININIT, 0xa);
488 agnx_write32(ctl, AGNX_GCR_THCD, 0x0);
489
490 agnx_write32(ctl, 0x11018, 0xb);
491 agnx_write32(ctl, AGNX_GCR_DISCOVMOD, 0x0);
492
493 /* Write Frequency to Gain Control Channel */
494 agnx_write32(ctl, AGNX_GCR_RXCHANEL, freq);
495 /* Write 0x140000/Freq to 0x9c08 */
496 reg = 0x140000/freq;
497 agnx_write32(ctl, 0x9c08, reg);
498
499 reg = agnx_read32(ctl, AGNX_PM_SOFTRST);
500 reg &= ~0x80100030;
501 agnx_write32(ctl, AGNX_PM_SOFTRST, reg);
502
503 reg = agnx_read32(ctl, AGNX_PM_PLLCTL);
504 reg &= ~0x20009;
505 reg |= 0x1;
506 agnx_write32(ctl, AGNX_PM_PLLCTL, reg);
507
508 agnx_write32(ctl, AGNX_ACI_MODE, 0x0);
509
510 /* FIXME According to Number of Chains: */
511
512 /* 1. 1: */
513 /* 1. Write 0x1203 to RF Chip 0 */
514 /* 2. Write 0x1200 to RF Chips 1 +2 */
515 /* 2. 2: */
516 /* 1. Write 0x1203 to RF Chip 0 */
517 /* 2. Write 0x1200 to RF Chip 2 */
518 /* 3. Write 0x1201 to RF Chip 1 */
519 /* 3. 3: */
520 /* 1. Write 0x1203 to RF Chip 0 */
521 /* 2. Write 0x1201 to RF Chip 1 + 2 */
522 /* 4. 4: */
523 /* 1. Write 0x1203 to RF Chip 0 + 1 */
524 /* 2. Write 0x1200 to RF Chip 2 */
525
526 /* 5. 6: */
527 spi_rf_write(ctl, RF_CHIP0|RF_CHIP1, 0x1203);
528 spi_rf_write(ctl, RF_CHIP2, 0x1201);
529
530 spi_rf_write(ctl, RF_CHIP0|RF_CHIP1|RF_CHIP2, 0x1000);
531 agnx_write32(ctl, AGNX_GCR_RXOVERIDE, 0x0);
532
533 /* FIXME Set the Disable Tx interrupt bit in Interrupt Mask
534 (Or 0x20000 to Interrupt Mask) */
535 /* reg = agnx_read32(ctl, AGNX_INT_MASK); */
536 /* reg |= IRQ_TX_DISABLE; */
537 /* agnx_write32(ctl, AGNX_INT_MASK, reg); */
538
539 agnx_write32(ctl, AGNX_GCR_RSTGCTL, 0x1);
540 agnx_write32(ctl, AGNX_GCR_RSTGCTL, 0x0);
541
542 /* Configure the Antenna */
543 antenna_config(priv);
544
545 /* Write 0x0 to Discovery Mode Enable detect G, B, A packet? */
546 agnx_write32(ctl, AGNX_GCR_DISCOVMOD, 0);
547
548 reg = agnx_read32(ctl, AGNX_RXM_REQRATE);
549 reg |= 0x80000000;
550 agnx_write32(ctl, AGNX_RXM_REQRATE, reg);
551 agnx_write32(ctl, AGNX_GCR_RSTGCTL, 0x1);
552 agnx_write32(ctl, AGNX_GCR_RSTGCTL, 0x0);
553
554 /* enable radio on and the power LED */
555 reg = agnx_read32(ctl, AGNX_SYSITF_GPIOUT);
556 reg &= ~0x1;
557 reg |= 0x2;
558 agnx_write32(ctl, AGNX_SYSITF_GPIOUT, reg);
559
560 reg = agnx_read32(ctl, AGNX_TXM_CTL);
561 reg |= 0x1;
562 agnx_write32(ctl, AGNX_TXM_CTL, reg);
563 } /* radio_channel_set */
564
base_band_filter_calibrate(struct agnx_priv * priv)565 static void base_band_filter_calibrate(struct agnx_priv *priv)
566 {
567 void __iomem *ctl = priv->ctl;
568
569 spi_rf_write(ctl, RF_CHIP0|RF_CHIP1|RF_CHIP2, 0x1700);
570 spi_rf_write(ctl, RF_CHIP0|RF_CHIP1|RF_CHIP2, 0x1001);
571 agnx_write32(ctl, AGNX_GCR_FORCECTLCLK, 0x0);
572 spi_rc_write(ctl, RF_CHIP0, 0x27);
573 spi_rc_write(ctl, RF_CHIP1, 0x27);
574 spi_rc_write(ctl, RF_CHIP2, 0x27);
575 agnx_write32(ctl, AGNX_GCR_FORCECTLCLK, 0x1);
576 }
577
print_offset(struct agnx_priv * priv,u32 chain)578 static void print_offset(struct agnx_priv *priv, u32 chain)
579 {
580 void __iomem *ctl = priv->ctl;
581 u32 offset;
582
583 iowrite32((chain), ctl + AGNX_ACI_SELCHAIN);
584 udelay(10);
585 offset = (ioread32(ctl + AGNX_ACI_OFFSET));
586 printk(PFX "Chain is 0x%x, Offset is 0x%x\n", chain, offset);
587 }
588
print_offsets(struct agnx_priv * priv)589 void print_offsets(struct agnx_priv *priv)
590 {
591 print_offset(priv, 0);
592 print_offset(priv, 4);
593 print_offset(priv, 1);
594 print_offset(priv, 5);
595 print_offset(priv, 2);
596 print_offset(priv, 6);
597 }
598
599
600 struct chains {
601 u32 cali; /* calibrate value*/
602
603 #define NEED_CALIBRATE 0
604 #define SUCCESS_CALIBRATE 1
605 int status;
606 };
607
chain_calibrate(struct agnx_priv * priv,struct chains * chains,unsigned int num)608 static void chain_calibrate(struct agnx_priv *priv, struct chains *chains,
609 unsigned int num)
610 {
611 void __iomem *ctl = priv->ctl;
612 u32 calibra = chains[num].cali;
613
614 if (num < 3)
615 calibra |= 0x1400;
616 else
617 calibra |= 0x1500;
618
619 switch (num) {
620 case 0:
621 case 4:
622 spi_rf_write(ctl, RF_CHIP0, calibra);
623 break;
624 case 1:
625 case 5:
626 spi_rf_write(ctl, RF_CHIP1, calibra);
627 break;
628 case 2:
629 case 6:
630 spi_rf_write(ctl, RF_CHIP2, calibra);
631 break;
632 default:
633 BUG();
634 }
635 } /* chain_calibrate */
636
637
get_calibrete_value(struct agnx_priv * priv,struct chains * chains,unsigned int num)638 static void inline get_calibrete_value(struct agnx_priv *priv, struct chains *chains,
639 unsigned int num)
640 {
641 void __iomem *ctl = priv->ctl;
642 u32 offset;
643
644 iowrite32((num), ctl + AGNX_ACI_SELCHAIN);
645 /* FIXME */
646 udelay(10);
647 offset = (ioread32(ctl + AGNX_ACI_OFFSET));
648
649 if (offset < 0xf) {
650 chains[num].status = SUCCESS_CALIBRATE;
651 return;
652 }
653
654 if (num == 0 || num == 1 || num == 2) {
655 if ( 0 == chains[num].cali)
656 chains[num].cali = 0xff;
657 else
658 chains[num].cali--;
659 } else
660 chains[num].cali++;
661
662 chains[num].status = NEED_CALIBRATE;
663 }
664
calibra_delay(struct agnx_priv * priv)665 static inline void calibra_delay(struct agnx_priv *priv)
666 {
667 void __iomem *ctl = priv->ctl;
668 u32 reg;
669 unsigned int i = 100;
670
671 wmb();
672 while (i--) {
673 reg = (ioread32(ctl + AGNX_ACI_STATUS));
674 if (reg == 0x4000)
675 break;
676 udelay(10);
677 }
678 if (!i)
679 printk(PFX "calibration failed\n");
680 }
681
do_calibration(struct agnx_priv * priv)682 void do_calibration(struct agnx_priv *priv)
683 {
684 void __iomem *ctl = priv->ctl;
685 struct chains chains[7];
686 unsigned int i, j;
687 AGNX_TRACE;
688
689 for (i = 0; i < 7; i++) {
690 if (i == 3)
691 continue;
692
693 chains[i].cali = 0x7f;
694 chains[i].status = NEED_CALIBRATE;
695 }
696
697 /* FIXME 0x300 is a magic number */
698 for (j = 0; j < 0x300; j++) {
699 if (chains[0].status == SUCCESS_CALIBRATE &&
700 chains[1].status == SUCCESS_CALIBRATE &&
701 chains[2].status == SUCCESS_CALIBRATE &&
702 chains[4].status == SUCCESS_CALIBRATE &&
703 chains[5].status == SUCCESS_CALIBRATE &&
704 chains[6].status == SUCCESS_CALIBRATE)
705 break;
706
707 /* Attention, there is no chain 3 */
708 for (i = 0; i < 7; i++) {
709 if (i == 3)
710 continue;
711 if (chains[i].status == NEED_CALIBRATE)
712 chain_calibrate(priv, chains, i);
713 }
714 /* Write 0x1 to Calibration Measure */
715 iowrite32((0x1), ctl + AGNX_ACI_MEASURE);
716 calibra_delay(priv);
717
718 for (i = 0; i < 7; i++) {
719 if (i == 3)
720 continue;
721
722 get_calibrete_value(priv, chains, i);
723 }
724 }
725 printk(PFX "Clibrate times is %d\n", j);
726 print_offsets(priv);
727 } /* do_calibration */
728
antenna_calibrate(struct agnx_priv * priv)729 void antenna_calibrate(struct agnx_priv *priv)
730 {
731 void __iomem *ctl = priv->ctl;
732 u32 reg;
733 AGNX_TRACE;
734
735 agnx_write32(ctl, AGNX_GCR_NLISTANT, 0x3);
736 agnx_write32(ctl, AGNX_GCR_NMEASANT, 0x3);
737 agnx_write32(ctl, AGNX_GCR_NACTIANT, 0x3);
738 agnx_write32(ctl, AGNX_GCR_NCAPTANT, 0x3);
739
740 agnx_write32(ctl, AGNX_GCR_ANTCFG, 0x1f);
741 agnx_write32(ctl, AGNX_GCR_BOACT, 0x24);
742 agnx_write32(ctl, AGNX_GCR_BOINACT, 0x24);
743 agnx_write32(ctl, AGNX_GCR_BODYNA, 0x20);
744 agnx_write32(ctl, AGNX_GCR_THD0A, 0x64);
745 agnx_write32(ctl, AGNX_GCR_THD0AL, 0x64);
746 agnx_write32(ctl, AGNX_GCR_THD0B, 0x46);
747 agnx_write32(ctl, AGNX_GCR_THD0BTFEST, 0x3c);
748 agnx_write32(ctl, AGNX_GCR_SIGHTH, 0x64);
749 agnx_write32(ctl, AGNX_GCR_SIGLTH, 0x30);
750
751 spi_rc_write(ctl, RF_CHIP0, 0x20);
752 /* Fixme */
753 udelay(80);
754 /* 1. Should read 0x0 */
755 reg = agnx_read32(ctl, AGNX_SPI_RLSW);
756 if (0x0 != reg)
757 printk(KERN_WARNING PFX "Unmatched rf chips result\n");
758 spi_rf_write(ctl, RF_CHIP0|RF_CHIP1|RF_CHIP2, 0x1000);
759
760 agnx_write32(ctl, AGNX_GCR_RXOVERIDE, 0x0);
761
762 spi_rc_write(ctl, RF_CHIP0, 0x22);
763 udelay(80);
764 reg = agnx_read32(ctl, AGNX_SPI_RLSW);
765 if (0x0 != reg)
766 printk(KERN_WARNING PFX "Unmatched rf chips result\n");
767 spi_rf_write(ctl, RF_CHIP0|RF_CHIP1|RF_CHIP2, 0x1005);
768
769 agnx_write32(ctl, AGNX_GCR_RSTGCTL, 0x1);
770 agnx_write32(ctl, AGNX_GCR_RSTGCTL, 0x0);
771
772 reg = agnx_read32(ctl, AGNX_PM_SOFTRST);
773 reg |= 0x1c000032;
774 agnx_write32(ctl, AGNX_PM_SOFTRST, reg);
775 reg = agnx_read32(ctl, AGNX_PM_PLLCTL);
776 reg |= 0x0003f07;
777 agnx_write32(ctl, AGNX_PM_PLLCTL, reg);
778
779 reg = agnx_read32(ctl, 0xec50);
780 reg |= 0x40;
781 agnx_write32(ctl, 0xec50, reg);
782
783 agnx_write32(ctl, AGNX_GCR_RXOVERIDE, 0xff8);
784 agnx_write32(ctl, AGNX_GCR_DISCOVMOD, 0x3);
785
786 agnx_write32(ctl, AGNX_GCR_CHAINNUM, 0x6);
787 agnx_write32(ctl, 0x19874, 0x0);
788 spi_rf_write(ctl, RF_CHIP0|RF_CHIP1|RF_CHIP2, 0x1700);
789
790 /* Calibrate the BaseBandFilter */
791 base_band_filter_calibrate(priv);
792
793 spi_rf_write(ctl, RF_CHIP0|RF_CHIP1|RF_CHIP2, 0x1002);
794
795 agnx_write32(ctl, AGNX_GCR_GAINSET0, 0x1d);
796 agnx_write32(ctl, AGNX_GCR_GAINSET1, 0x1d);
797 agnx_write32(ctl, AGNX_GCR_GAINSET2, 0x1d);
798 agnx_write32(ctl, AGNX_GCR_GAINSETWRITE, 0x1);
799
800 agnx_write32(ctl, AGNX_ACI_MODE, 0x1);
801 agnx_write32(ctl, AGNX_ACI_LEN, 0x3ff);
802
803 agnx_write32(ctl, AGNX_ACI_TIMER1, 0x27);
804 agnx_write32(ctl, AGNX_ACI_TIMER2, 0x27);
805
806 spi_rf_write(ctl, RF_CHIP0|RF_CHIP1|RF_CHIP2, 0x1400);
807 spi_rf_write(ctl, RF_CHIP0|RF_CHIP1|RF_CHIP2, 0x1500);
808
809 /* Measure Calibration */
810 agnx_write32(ctl, AGNX_ACI_MEASURE, 0x1);
811 calibra_delay(priv);
812
813 /* do calibration */
814 do_calibration(priv);
815
816 agnx_write32(ctl, AGNX_GCR_RXOVERIDE, 0x0);
817 agnx_write32(ctl, AGNX_ACI_TIMER1, 0x21);
818 agnx_write32(ctl, AGNX_ACI_TIMER2, 0x27);
819 agnx_write32(ctl, AGNX_ACI_LEN, 0xf);
820
821 reg = agnx_read32(ctl, AGNX_GCR_GAINSET0);
822 reg &= 0xf;
823 agnx_write32(ctl, AGNX_GCR_GAINSET0, reg);
824 reg = agnx_read32(ctl, AGNX_GCR_GAINSET1);
825 reg &= 0xf;
826 agnx_write32(ctl, AGNX_GCR_GAINSET1, reg);
827 reg = agnx_read32(ctl, AGNX_GCR_GAINSET2);
828 reg &= 0xf;
829 agnx_write32(ctl, AGNX_GCR_GAINSET2, reg);
830
831 agnx_write32(ctl, AGNX_GCR_GAINSETWRITE, 0x0);
832 disable_receiver(priv);
833 } /* antenna_calibrate */
834
__antenna_calibrate(struct agnx_priv * priv)835 void __antenna_calibrate(struct agnx_priv *priv)
836 {
837 void __iomem *ctl = priv->ctl;
838 u32 reg;
839
840 /* Calibrate the BaseBandFilter */
841 /* base_band_filter_calibrate(priv); */
842 spi_rf_write(ctl, RF_CHIP0|RF_CHIP1|RF_CHIP2, 0x1002);
843
844
845 agnx_write32(ctl, AGNX_GCR_GAINSET0, 0x1d);
846 agnx_write32(ctl, AGNX_GCR_GAINSET1, 0x1d);
847 agnx_write32(ctl, AGNX_GCR_GAINSET2, 0x1d);
848
849 agnx_write32(ctl, AGNX_GCR_GAINSETWRITE, 0x1);
850
851 agnx_write32(ctl, AGNX_ACI_MODE, 0x1);
852 agnx_write32(ctl, AGNX_ACI_LEN, 0x3ff);
853
854
855 agnx_write32(ctl, AGNX_ACI_TIMER1, 0x27);
856 agnx_write32(ctl, AGNX_ACI_TIMER2, 0x27);
857 spi_rf_write(ctl, RF_CHIP0|RF_CHIP1|RF_CHIP2, 0x1400);
858 spi_rf_write(ctl, RF_CHIP0|RF_CHIP1|RF_CHIP2, 0x1500);
859 /* Measure Calibration */
860 agnx_write32(ctl, AGNX_ACI_MEASURE, 0x1);
861 calibra_delay(priv);
862 do_calibration(priv);
863 agnx_write32(ctl, AGNX_GCR_RXOVERIDE, 0x0);
864
865 agnx_write32(ctl, AGNX_ACI_TIMER1, 0x21);
866 agnx_write32(ctl, AGNX_ACI_TIMER2, 0x27);
867
868 agnx_write32(ctl, AGNX_ACI_LEN, 0xf);
869
870 reg = agnx_read32(ctl, AGNX_GCR_GAINSET0);
871 reg &= 0xf;
872 agnx_write32(ctl, AGNX_GCR_GAINSET0, reg);
873 reg = agnx_read32(ctl, AGNX_GCR_GAINSET1);
874 reg &= 0xf;
875 agnx_write32(ctl, AGNX_GCR_GAINSET1, reg);
876 reg = agnx_read32(ctl, AGNX_GCR_GAINSET2);
877 reg &= 0xf;
878 agnx_write32(ctl, AGNX_GCR_GAINSET2, reg);
879
880
881 agnx_write32(ctl, AGNX_GCR_GAINSETWRITE, 0x0);
882
883 /* Write 0x3 Gain Control Discovery Mode */
884 enable_receiver(priv);
885 }
886
agnx_set_channel(struct agnx_priv * priv,unsigned int channel)887 int agnx_set_channel(struct agnx_priv *priv, unsigned int channel)
888 {
889 AGNX_TRACE;
890
891 printk(KERN_ERR PFX "Channel is %d %s\n", channel, __func__);
892 radio_channel_set(priv, channel);
893 return 0;
894 }
895