1 /* 2 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved. 3 * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com> 4 * Copyright(c) 2006 - 2008 Jay Cliburn <jcliburn@gmail.com> 5 * 6 * Derived from Intel e1000 driver 7 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the Free 11 * Software Foundation; either version 2 of the License, or (at your option) 12 * any later version. 13 * 14 * This program is distributed in the hope that it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 17 * more details. 18 * 19 * You should have received a copy of the GNU General Public License along with 20 * this program; if not, write to the Free Software Foundation, Inc., 59 21 * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 22 */ 23 24 #ifndef ATL1_H 25 #define ATL1_H 26 27 #include <linux/compiler.h> 28 #include <linux/ethtool.h> 29 #include <linux/if_vlan.h> 30 #include <linux/mii.h> 31 #include <linux/module.h> 32 #include <linux/skbuff.h> 33 #include <linux/spinlock.h> 34 #include <linux/timer.h> 35 #include <linux/types.h> 36 #include <linux/workqueue.h> 37 38 #include "atlx.h" 39 40 #define ATLX_DRIVER_NAME "atl1" 41 42 MODULE_DESCRIPTION("Atheros L1 Gigabit Ethernet Driver"); 43 44 #define atlx_adapter atl1_adapter 45 #define atlx_check_for_link atl1_check_for_link 46 #define atlx_check_link atl1_check_link 47 #define atlx_hash_mc_addr atl1_hash_mc_addr 48 #define atlx_hash_set atl1_hash_set 49 #define atlx_hw atl1_hw 50 #define atlx_mii_ioctl atl1_mii_ioctl 51 #define atlx_read_phy_reg atl1_read_phy_reg 52 #define atlx_set_mac atl1_set_mac 53 #define atlx_set_mac_addr atl1_set_mac_addr 54 55 struct atl1_adapter; 56 struct atl1_hw; 57 58 /* function prototypes needed by multiple files */ 59 u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr); 60 void atl1_hash_set(struct atl1_hw *hw, u32 hash_value); 61 s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data); 62 void atl1_set_mac_addr(struct atl1_hw *hw); 63 static int atl1_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, 64 int cmd); 65 static u32 atl1_check_link(struct atl1_adapter *adapter); 66 67 extern const struct ethtool_ops atl1_ethtool_ops; 68 69 /* hardware definitions specific to L1 */ 70 71 /* Block IDLE Status Register */ 72 #define IDLE_STATUS_RXMAC 0x1 73 #define IDLE_STATUS_TXMAC 0x2 74 #define IDLE_STATUS_RXQ 0x4 75 #define IDLE_STATUS_TXQ 0x8 76 #define IDLE_STATUS_DMAR 0x10 77 #define IDLE_STATUS_DMAW 0x20 78 #define IDLE_STATUS_SMB 0x40 79 #define IDLE_STATUS_CMB 0x80 80 81 /* MDIO Control Register */ 82 #define MDIO_WAIT_TIMES 30 83 84 /* MAC Control Register */ 85 #define MAC_CTRL_TX_PAUSE 0x10000 86 #define MAC_CTRL_SCNT 0x20000 87 #define MAC_CTRL_SRST_TX 0x40000 88 #define MAC_CTRL_TX_SIMURST 0x80000 89 #define MAC_CTRL_SPEED_SHIFT 20 90 #define MAC_CTRL_SPEED_MASK 0x300000 91 #define MAC_CTRL_SPEED_1000 0x2 92 #define MAC_CTRL_SPEED_10_100 0x1 93 #define MAC_CTRL_DBG_TX_BKPRESURE 0x400000 94 #define MAC_CTRL_TX_HUGE 0x800000 95 #define MAC_CTRL_RX_CHKSUM_EN 0x1000000 96 #define MAC_CTRL_DBG 0x8000000 97 98 /* Wake-On-Lan control register */ 99 #define WOL_CLK_SWITCH_EN 0x8000 100 #define WOL_PT5_EN 0x200000 101 #define WOL_PT6_EN 0x400000 102 #define WOL_PT5_MATCH 0x8000000 103 #define WOL_PT6_MATCH 0x10000000 104 105 /* WOL Length ( 2 DWORD ) */ 106 #define REG_WOL_PATTERN_LEN 0x14A4 107 #define WOL_PT_LEN_MASK 0x7F 108 #define WOL_PT0_LEN_SHIFT 0 109 #define WOL_PT1_LEN_SHIFT 8 110 #define WOL_PT2_LEN_SHIFT 16 111 #define WOL_PT3_LEN_SHIFT 24 112 #define WOL_PT4_LEN_SHIFT 0 113 #define WOL_PT5_LEN_SHIFT 8 114 #define WOL_PT6_LEN_SHIFT 16 115 116 /* Internal SRAM Partition Registers, low 32 bits */ 117 #define REG_SRAM_RFD_LEN 0x1504 118 #define REG_SRAM_RRD_ADDR 0x1508 119 #define REG_SRAM_RRD_LEN 0x150C 120 #define REG_SRAM_TPD_ADDR 0x1510 121 #define REG_SRAM_TPD_LEN 0x1514 122 #define REG_SRAM_TRD_ADDR 0x1518 123 #define REG_SRAM_TRD_LEN 0x151C 124 #define REG_SRAM_RXF_ADDR 0x1520 125 #define REG_SRAM_RXF_LEN 0x1524 126 #define REG_SRAM_TXF_ADDR 0x1528 127 #define REG_SRAM_TXF_LEN 0x152C 128 #define REG_SRAM_TCPH_PATH_ADDR 0x1530 129 #define SRAM_TCPH_ADDR_MASK 0xFFF 130 #define SRAM_TCPH_ADDR_SHIFT 0 131 #define SRAM_PATH_ADDR_MASK 0xFFF 132 #define SRAM_PATH_ADDR_SHIFT 16 133 134 /* Load Ptr Register */ 135 #define REG_LOAD_PTR 0x1534 136 137 /* Descriptor Control registers, low 32 bits */ 138 #define REG_DESC_RFD_ADDR_LO 0x1544 139 #define REG_DESC_RRD_ADDR_LO 0x1548 140 #define REG_DESC_TPD_ADDR_LO 0x154C 141 #define REG_DESC_CMB_ADDR_LO 0x1550 142 #define REG_DESC_SMB_ADDR_LO 0x1554 143 #define REG_DESC_RFD_RRD_RING_SIZE 0x1558 144 #define DESC_RFD_RING_SIZE_MASK 0x7FF 145 #define DESC_RFD_RING_SIZE_SHIFT 0 146 #define DESC_RRD_RING_SIZE_MASK 0x7FF 147 #define DESC_RRD_RING_SIZE_SHIFT 16 148 #define REG_DESC_TPD_RING_SIZE 0x155C 149 #define DESC_TPD_RING_SIZE_MASK 0x3FF 150 #define DESC_TPD_RING_SIZE_SHIFT 0 151 152 /* TXQ Control Register */ 153 #define REG_TXQ_CTRL 0x1580 154 #define TXQ_CTRL_TPD_BURST_NUM_SHIFT 0 155 #define TXQ_CTRL_TPD_BURST_NUM_MASK 0x1F 156 #define TXQ_CTRL_EN 0x20 157 #define TXQ_CTRL_ENH_MODE 0x40 158 #define TXQ_CTRL_TPD_FETCH_TH_SHIFT 8 159 #define TXQ_CTRL_TPD_FETCH_TH_MASK 0x3F 160 #define TXQ_CTRL_TXF_BURST_NUM_SHIFT 16 161 #define TXQ_CTRL_TXF_BURST_NUM_MASK 0xFFFF 162 163 /* Jumbo packet Threshold for task offload */ 164 #define REG_TX_JUMBO_TASK_TH_TPD_IPG 0x1584 165 #define TX_JUMBO_TASK_TH_MASK 0x7FF 166 #define TX_JUMBO_TASK_TH_SHIFT 0 167 #define TX_TPD_MIN_IPG_MASK 0x1F 168 #define TX_TPD_MIN_IPG_SHIFT 16 169 170 /* RXQ Control Register */ 171 #define REG_RXQ_CTRL 0x15A0 172 #define RXQ_CTRL_RFD_BURST_NUM_SHIFT 0 173 #define RXQ_CTRL_RFD_BURST_NUM_MASK 0xFF 174 #define RXQ_CTRL_RRD_BURST_THRESH_SHIFT 8 175 #define RXQ_CTRL_RRD_BURST_THRESH_MASK 0xFF 176 #define RXQ_CTRL_RFD_PREF_MIN_IPG_SHIFT 16 177 #define RXQ_CTRL_RFD_PREF_MIN_IPG_MASK 0x1F 178 #define RXQ_CTRL_CUT_THRU_EN 0x40000000 179 #define RXQ_CTRL_EN 0x80000000 180 181 /* Rx jumbo packet threshold and rrd retirement timer */ 182 #define REG_RXQ_JMBOSZ_RRDTIM 0x15A4 183 #define RXQ_JMBOSZ_TH_MASK 0x7FF 184 #define RXQ_JMBOSZ_TH_SHIFT 0 185 #define RXQ_JMBO_LKAH_MASK 0xF 186 #define RXQ_JMBO_LKAH_SHIFT 11 187 #define RXQ_RRD_TIMER_MASK 0xFFFF 188 #define RXQ_RRD_TIMER_SHIFT 16 189 190 /* RFD flow control register */ 191 #define REG_RXQ_RXF_PAUSE_THRESH 0x15A8 192 #define RXQ_RXF_PAUSE_TH_HI_SHIFT 16 193 #define RXQ_RXF_PAUSE_TH_HI_MASK 0xFFF 194 #define RXQ_RXF_PAUSE_TH_LO_SHIFT 0 195 #define RXQ_RXF_PAUSE_TH_LO_MASK 0xFFF 196 197 /* RRD flow control register */ 198 #define REG_RXQ_RRD_PAUSE_THRESH 0x15AC 199 #define RXQ_RRD_PAUSE_TH_HI_SHIFT 0 200 #define RXQ_RRD_PAUSE_TH_HI_MASK 0xFFF 201 #define RXQ_RRD_PAUSE_TH_LO_SHIFT 16 202 #define RXQ_RRD_PAUSE_TH_LO_MASK 0xFFF 203 204 /* DMA Engine Control Register */ 205 #define REG_DMA_CTRL 0x15C0 206 #define DMA_CTRL_DMAR_IN_ORDER 0x1 207 #define DMA_CTRL_DMAR_ENH_ORDER 0x2 208 #define DMA_CTRL_DMAR_OUT_ORDER 0x4 209 #define DMA_CTRL_RCB_VALUE 0x8 210 #define DMA_CTRL_DMAR_BURST_LEN_SHIFT 4 211 #define DMA_CTRL_DMAR_BURST_LEN_MASK 7 212 #define DMA_CTRL_DMAW_BURST_LEN_SHIFT 7 213 #define DMA_CTRL_DMAW_BURST_LEN_MASK 7 214 #define DMA_CTRL_DMAR_EN 0x400 215 #define DMA_CTRL_DMAW_EN 0x800 216 217 /* CMB/SMB Control Register */ 218 #define REG_CSMB_CTRL 0x15D0 219 #define CSMB_CTRL_CMB_NOW 1 220 #define CSMB_CTRL_SMB_NOW 2 221 #define CSMB_CTRL_CMB_EN 4 222 #define CSMB_CTRL_SMB_EN 8 223 224 /* CMB DMA Write Threshold Register */ 225 #define REG_CMB_WRITE_TH 0x15D4 226 #define CMB_RRD_TH_SHIFT 0 227 #define CMB_RRD_TH_MASK 0x7FF 228 #define CMB_TPD_TH_SHIFT 16 229 #define CMB_TPD_TH_MASK 0x7FF 230 231 /* RX/TX count-down timer to trigger CMB-write. 2us resolution. */ 232 #define REG_CMB_WRITE_TIMER 0x15D8 233 #define CMB_RX_TM_SHIFT 0 234 #define CMB_RX_TM_MASK 0xFFFF 235 #define CMB_TX_TM_SHIFT 16 236 #define CMB_TX_TM_MASK 0xFFFF 237 238 /* Number of packet received since last CMB write */ 239 #define REG_CMB_RX_PKT_CNT 0x15DC 240 241 /* Number of packet transmitted since last CMB write */ 242 #define REG_CMB_TX_PKT_CNT 0x15E0 243 244 /* SMB auto DMA timer register */ 245 #define REG_SMB_TIMER 0x15E4 246 247 /* Mailbox Register */ 248 #define REG_MAILBOX 0x15F0 249 #define MB_RFD_PROD_INDX_SHIFT 0 250 #define MB_RFD_PROD_INDX_MASK 0x7FF 251 #define MB_RRD_CONS_INDX_SHIFT 11 252 #define MB_RRD_CONS_INDX_MASK 0x7FF 253 #define MB_TPD_PROD_INDX_SHIFT 22 254 #define MB_TPD_PROD_INDX_MASK 0x3FF 255 256 /* Interrupt Status Register */ 257 #define ISR_SMB 0x1 258 #define ISR_TIMER 0x2 259 #define ISR_MANUAL 0x4 260 #define ISR_RXF_OV 0x8 261 #define ISR_RFD_UNRUN 0x10 262 #define ISR_RRD_OV 0x20 263 #define ISR_TXF_UNRUN 0x40 264 #define ISR_LINK 0x80 265 #define ISR_HOST_RFD_UNRUN 0x100 266 #define ISR_HOST_RRD_OV 0x200 267 #define ISR_DMAR_TO_RST 0x400 268 #define ISR_DMAW_TO_RST 0x800 269 #define ISR_GPHY 0x1000 270 #define ISR_RX_PKT 0x10000 271 #define ISR_TX_PKT 0x20000 272 #define ISR_TX_DMA 0x40000 273 #define ISR_RX_DMA 0x80000 274 #define ISR_CMB_RX 0x100000 275 #define ISR_CMB_TX 0x200000 276 #define ISR_MAC_RX 0x400000 277 #define ISR_MAC_TX 0x800000 278 #define ISR_DIS_SMB 0x20000000 279 #define ISR_DIS_DMA 0x40000000 280 281 /* Normal Interrupt mask */ 282 #define IMR_NORMAL_MASK (\ 283 ISR_SMB |\ 284 ISR_GPHY |\ 285 ISR_PHY_LINKDOWN|\ 286 ISR_DMAR_TO_RST |\ 287 ISR_DMAW_TO_RST |\ 288 ISR_CMB_TX |\ 289 ISR_CMB_RX) 290 291 /* Debug Interrupt Mask (enable all interrupt) */ 292 #define IMR_DEBUG_MASK (\ 293 ISR_SMB |\ 294 ISR_TIMER |\ 295 ISR_MANUAL |\ 296 ISR_RXF_OV |\ 297 ISR_RFD_UNRUN |\ 298 ISR_RRD_OV |\ 299 ISR_TXF_UNRUN |\ 300 ISR_LINK |\ 301 ISR_CMB_TX |\ 302 ISR_CMB_RX |\ 303 ISR_RX_PKT |\ 304 ISR_TX_PKT |\ 305 ISR_MAC_RX |\ 306 ISR_MAC_TX) 307 308 #define MEDIA_TYPE_1000M_FULL 1 309 #define MEDIA_TYPE_100M_FULL 2 310 #define MEDIA_TYPE_100M_HALF 3 311 #define MEDIA_TYPE_10M_FULL 4 312 #define MEDIA_TYPE_10M_HALF 5 313 314 #define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* All but 1000-Half */ 315 316 #define MAX_JUMBO_FRAME_SIZE 10240 317 318 #define ATL1_EEDUMP_LEN 48 319 320 /* Statistics counters collected by the MAC */ 321 struct stats_msg_block { 322 /* rx */ 323 u32 rx_ok; /* good RX packets */ 324 u32 rx_bcast; /* good RX broadcast packets */ 325 u32 rx_mcast; /* good RX multicast packets */ 326 u32 rx_pause; /* RX pause frames */ 327 u32 rx_ctrl; /* RX control packets other than pause frames */ 328 u32 rx_fcs_err; /* RX packets with bad FCS */ 329 u32 rx_len_err; /* RX packets with length != actual size */ 330 u32 rx_byte_cnt; /* good bytes received. FCS is NOT included */ 331 u32 rx_runt; /* RX packets < 64 bytes with good FCS */ 332 u32 rx_frag; /* RX packets < 64 bytes with bad FCS */ 333 u32 rx_sz_64; /* 64 byte RX packets */ 334 u32 rx_sz_65_127; 335 u32 rx_sz_128_255; 336 u32 rx_sz_256_511; 337 u32 rx_sz_512_1023; 338 u32 rx_sz_1024_1518; 339 u32 rx_sz_1519_max; /* 1519 byte to MTU RX packets */ 340 u32 rx_sz_ov; /* truncated RX packets > MTU */ 341 u32 rx_rxf_ov; /* frames dropped due to RX FIFO overflow */ 342 u32 rx_rrd_ov; /* frames dropped due to RRD overflow */ 343 u32 rx_align_err; /* alignment errors */ 344 u32 rx_bcast_byte_cnt; /* RX broadcast bytes, excluding FCS */ 345 u32 rx_mcast_byte_cnt; /* RX multicast bytes, excluding FCS */ 346 u32 rx_err_addr; /* packets dropped due to address filtering */ 347 348 /* tx */ 349 u32 tx_ok; /* good TX packets */ 350 u32 tx_bcast; /* good TX broadcast packets */ 351 u32 tx_mcast; /* good TX multicast packets */ 352 u32 tx_pause; /* TX pause frames */ 353 u32 tx_exc_defer; /* TX packets deferred excessively */ 354 u32 tx_ctrl; /* TX control frames, excluding pause frames */ 355 u32 tx_defer; /* TX packets deferred */ 356 u32 tx_byte_cnt; /* bytes transmitted, FCS is NOT included */ 357 u32 tx_sz_64; /* 64 byte TX packets */ 358 u32 tx_sz_65_127; 359 u32 tx_sz_128_255; 360 u32 tx_sz_256_511; 361 u32 tx_sz_512_1023; 362 u32 tx_sz_1024_1518; 363 u32 tx_sz_1519_max; /* 1519 byte to MTU TX packets */ 364 u32 tx_1_col; /* packets TX after a single collision */ 365 u32 tx_2_col; /* packets TX after multiple collisions */ 366 u32 tx_late_col; /* TX packets with late collisions */ 367 u32 tx_abort_col; /* TX packets aborted w/excessive collisions */ 368 u32 tx_underrun; /* TX packets aborted due to TX FIFO underrun 369 * or TRD FIFO underrun */ 370 u32 tx_rd_eop; /* reads beyond the EOP into the next frame 371 * when TRD was not written timely */ 372 u32 tx_len_err; /* TX packets where length != actual size */ 373 u32 tx_trunc; /* TX packets truncated due to size > MTU */ 374 u32 tx_bcast_byte; /* broadcast bytes transmitted, excluding FCS */ 375 u32 tx_mcast_byte; /* multicast bytes transmitted, excluding FCS */ 376 u32 smb_updated; /* 1: SMB Updated. This is used by software to 377 * indicate the statistics update. Software 378 * should clear this bit after retrieving the 379 * statistics information. */ 380 }; 381 382 /* Coalescing Message Block */ 383 struct coals_msg_block { 384 u32 int_stats; /* interrupt status */ 385 u16 rrd_prod_idx; /* TRD Producer Index. */ 386 u16 rfd_cons_idx; /* RFD Consumer Index. */ 387 u16 update; /* Selene sets this bit every time it DMAs the 388 * CMB to host memory. Software should clear 389 * this bit when CMB info is processed. */ 390 u16 tpd_cons_idx; /* TPD Consumer Index. */ 391 }; 392 393 /* RRD descriptor */ 394 struct rx_return_desc { 395 u8 num_buf; /* Number of RFD buffers used by the received packet */ 396 u8 resved; 397 u16 buf_indx; /* RFD Index of the first buffer */ 398 union { 399 u32 valid; 400 struct { 401 u16 rx_chksum; 402 u16 pkt_size; 403 } xsum_sz; 404 } xsz; 405 406 u16 pkt_flg; /* Packet flags */ 407 u16 err_flg; /* Error flags */ 408 u16 resved2; 409 u16 vlan_tag; /* VLAN TAG */ 410 }; 411 412 #define PACKET_FLAG_ETH_TYPE 0x0080 413 #define PACKET_FLAG_VLAN_INS 0x0100 414 #define PACKET_FLAG_ERR 0x0200 415 #define PACKET_FLAG_IPV4 0x0400 416 #define PACKET_FLAG_UDP 0x0800 417 #define PACKET_FLAG_TCP 0x1000 418 #define PACKET_FLAG_BCAST 0x2000 419 #define PACKET_FLAG_MCAST 0x4000 420 #define PACKET_FLAG_PAUSE 0x8000 421 422 #define ERR_FLAG_CRC 0x0001 423 #define ERR_FLAG_CODE 0x0002 424 #define ERR_FLAG_DRIBBLE 0x0004 425 #define ERR_FLAG_RUNT 0x0008 426 #define ERR_FLAG_OV 0x0010 427 #define ERR_FLAG_TRUNC 0x0020 428 #define ERR_FLAG_IP_CHKSUM 0x0040 429 #define ERR_FLAG_L4_CHKSUM 0x0080 430 #define ERR_FLAG_LEN 0x0100 431 #define ERR_FLAG_DES_ADDR 0x0200 432 433 /* RFD descriptor */ 434 struct rx_free_desc { 435 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 436 __le16 buf_len; /* Size of the receive buffer in host memory */ 437 u16 coalese; /* Update consumer index to host after the 438 * reception of this frame */ 439 /* __attribute__ ((packed)) is required */ 440 } __attribute__ ((packed)); 441 442 /* 443 * The L1 transmit packet descriptor is comprised of four 32-bit words. 444 * 445 * 31 0 446 * +---------------------------------------+ 447 * | Word 0: Buffer addr lo | 448 * +---------------------------------------+ 449 * | Word 1: Buffer addr hi | 450 * +---------------------------------------+ 451 * | Word 2 | 452 * +---------------------------------------+ 453 * | Word 3 | 454 * +---------------------------------------+ 455 * 456 * Words 0 and 1 combine to form a 64-bit buffer address. 457 * 458 * Word 2 is self explanatory in the #define block below. 459 * 460 * Word 3 has two forms, depending upon the state of bits 3 and 4. 461 * If bits 3 and 4 are both zero, then bits 14:31 are unused by the 462 * hardware. Otherwise, if either bit 3 or 4 is set, the definition 463 * of bits 14:31 vary according to the following depiction. 464 * 465 * 0 End of packet 0 End of packet 466 * 1 Coalesce 1 Coalesce 467 * 2 Insert VLAN tag 2 Insert VLAN tag 468 * 3 Custom csum enable = 0 3 Custom csum enable = 1 469 * 4 Segment enable = 1 4 Segment enable = 0 470 * 5 Generate IP checksum 5 Generate IP checksum 471 * 6 Generate TCP checksum 6 Generate TCP checksum 472 * 7 Generate UDP checksum 7 Generate UDP checksum 473 * 8 VLAN tagged 8 VLAN tagged 474 * 9 Ethernet frame type 9 Ethernet frame type 475 * 10-+ 10-+ 476 * 11 | IP hdr length (10:13) 11 | IP hdr length (10:13) 477 * 12 | (num 32-bit words) 12 | (num 32-bit words) 478 * 13-+ 13-+ 479 * 14-+ 14 Unused 480 * 15 | TCP hdr length (14:17) 15 Unused 481 * 16 | (num 32-bit words) 16-+ 482 * 17-+ 17 | 483 * 18 Header TPD flag 18 | 484 * 19-+ 19 | Payload offset 485 * 20 | 20 | (16:23) 486 * 21 | 21 | 487 * 22 | 22 | 488 * 23 | 23-+ 489 * 24 | 24-+ 490 * 25 | MSS (19:31) 25 | 491 * 26 | 26 | 492 * 27 | 27 | Custom csum offset 493 * 28 | 28 | (24:31) 494 * 29 | 29 | 495 * 30 | 30 | 496 * 31-+ 31-+ 497 */ 498 499 /* tpd word 2 */ 500 #define TPD_BUFLEN_MASK 0x3FFF 501 #define TPD_BUFLEN_SHIFT 0 502 #define TPD_DMAINT_MASK 0x0001 503 #define TPD_DMAINT_SHIFT 14 504 #define TPD_PKTNT_MASK 0x0001 505 #define TPD_PKTINT_SHIFT 15 506 #define TPD_VLANTAG_MASK 0xFFFF 507 #define TPD_VLANTAG_SHIFT 16 508 509 /* tpd word 3 bits 0:13 */ 510 #define TPD_EOP_MASK 0x0001 511 #define TPD_EOP_SHIFT 0 512 #define TPD_COALESCE_MASK 0x0001 513 #define TPD_COALESCE_SHIFT 1 514 #define TPD_INS_VL_TAG_MASK 0x0001 515 #define TPD_INS_VL_TAG_SHIFT 2 516 #define TPD_CUST_CSUM_EN_MASK 0x0001 517 #define TPD_CUST_CSUM_EN_SHIFT 3 518 #define TPD_SEGMENT_EN_MASK 0x0001 519 #define TPD_SEGMENT_EN_SHIFT 4 520 #define TPD_IP_CSUM_MASK 0x0001 521 #define TPD_IP_CSUM_SHIFT 5 522 #define TPD_TCP_CSUM_MASK 0x0001 523 #define TPD_TCP_CSUM_SHIFT 6 524 #define TPD_UDP_CSUM_MASK 0x0001 525 #define TPD_UDP_CSUM_SHIFT 7 526 #define TPD_VL_TAGGED_MASK 0x0001 527 #define TPD_VL_TAGGED_SHIFT 8 528 #define TPD_ETHTYPE_MASK 0x0001 529 #define TPD_ETHTYPE_SHIFT 9 530 #define TPD_IPHL_MASK 0x000F 531 #define TPD_IPHL_SHIFT 10 532 533 /* tpd word 3 bits 14:31 if segment enabled */ 534 #define TPD_TCPHDRLEN_MASK 0x000F 535 #define TPD_TCPHDRLEN_SHIFT 14 536 #define TPD_HDRFLAG_MASK 0x0001 537 #define TPD_HDRFLAG_SHIFT 18 538 #define TPD_MSS_MASK 0x1FFF 539 #define TPD_MSS_SHIFT 19 540 541 /* tpd word 3 bits 16:31 if custom csum enabled */ 542 #define TPD_PLOADOFFSET_MASK 0x00FF 543 #define TPD_PLOADOFFSET_SHIFT 16 544 #define TPD_CCSUMOFFSET_MASK 0x00FF 545 #define TPD_CCSUMOFFSET_SHIFT 24 546 547 struct tx_packet_desc { 548 __le64 buffer_addr; 549 __le32 word2; 550 __le32 word3; 551 }; 552 553 /* DMA Order Settings */ 554 enum atl1_dma_order { 555 atl1_dma_ord_in = 1, 556 atl1_dma_ord_enh = 2, 557 atl1_dma_ord_out = 4 558 }; 559 560 enum atl1_dma_rcb { 561 atl1_rcb_64 = 0, 562 atl1_rcb_128 = 1 563 }; 564 565 enum atl1_dma_req_block { 566 atl1_dma_req_128 = 0, 567 atl1_dma_req_256 = 1, 568 atl1_dma_req_512 = 2, 569 atl1_dma_req_1024 = 3, 570 atl1_dma_req_2048 = 4, 571 atl1_dma_req_4096 = 5 572 }; 573 574 #define ATL1_MAX_INTR 3 575 #define ATL1_MAX_TX_BUF_LEN 0x3000 /* 12288 bytes */ 576 577 #define ATL1_DEFAULT_TPD 256 578 #define ATL1_MAX_TPD 1024 579 #define ATL1_MIN_TPD 64 580 #define ATL1_DEFAULT_RFD 512 581 #define ATL1_MIN_RFD 128 582 #define ATL1_MAX_RFD 2048 583 #define ATL1_REG_COUNT 1538 584 585 #define ATL1_GET_DESC(R, i, type) (&(((type *)((R)->desc))[i])) 586 #define ATL1_RFD_DESC(R, i) ATL1_GET_DESC(R, i, struct rx_free_desc) 587 #define ATL1_TPD_DESC(R, i) ATL1_GET_DESC(R, i, struct tx_packet_desc) 588 #define ATL1_RRD_DESC(R, i) ATL1_GET_DESC(R, i, struct rx_return_desc) 589 590 /* 591 * atl1_ring_header represents a single, contiguous block of DMA space 592 * mapped for the three descriptor rings (tpd, rfd, rrd) and the two 593 * message blocks (cmb, smb) described below 594 */ 595 struct atl1_ring_header { 596 void *desc; /* virtual address */ 597 dma_addr_t dma; /* physical address*/ 598 unsigned int size; /* length in bytes */ 599 }; 600 601 /* 602 * atl1_buffer is wrapper around a pointer to a socket buffer 603 * so a DMA handle can be stored along with the skb 604 */ 605 struct atl1_buffer { 606 struct sk_buff *skb; /* socket buffer */ 607 u16 length; /* rx buffer length */ 608 u16 alloced; /* 1 if skb allocated */ 609 dma_addr_t dma; 610 }; 611 612 /* transmit packet descriptor (tpd) ring */ 613 struct atl1_tpd_ring { 614 void *desc; /* descriptor ring virtual address */ 615 dma_addr_t dma; /* descriptor ring physical address */ 616 u16 size; /* descriptor ring length in bytes */ 617 u16 count; /* number of descriptors in the ring */ 618 u16 hw_idx; /* hardware index */ 619 atomic_t next_to_clean; 620 atomic_t next_to_use; 621 struct atl1_buffer *buffer_info; 622 }; 623 624 /* receive free descriptor (rfd) ring */ 625 struct atl1_rfd_ring { 626 void *desc; /* descriptor ring virtual address */ 627 dma_addr_t dma; /* descriptor ring physical address */ 628 u16 size; /* descriptor ring length in bytes */ 629 u16 count; /* number of descriptors in the ring */ 630 atomic_t next_to_use; 631 u16 next_to_clean; 632 struct atl1_buffer *buffer_info; 633 }; 634 635 /* receive return descriptor (rrd) ring */ 636 struct atl1_rrd_ring { 637 void *desc; /* descriptor ring virtual address */ 638 dma_addr_t dma; /* descriptor ring physical address */ 639 unsigned int size; /* descriptor ring length in bytes */ 640 u16 count; /* number of descriptors in the ring */ 641 u16 next_to_use; 642 atomic_t next_to_clean; 643 }; 644 645 /* coalescing message block (cmb) */ 646 struct atl1_cmb { 647 struct coals_msg_block *cmb; 648 dma_addr_t dma; 649 }; 650 651 /* statistics message block (smb) */ 652 struct atl1_smb { 653 struct stats_msg_block *smb; 654 dma_addr_t dma; 655 }; 656 657 /* Statistics counters */ 658 struct atl1_sft_stats { 659 u64 rx_packets; 660 u64 tx_packets; 661 u64 rx_bytes; 662 u64 tx_bytes; 663 u64 multicast; 664 u64 collisions; 665 u64 rx_errors; 666 u64 rx_length_errors; 667 u64 rx_crc_errors; 668 u64 rx_frame_errors; 669 u64 rx_fifo_errors; 670 u64 rx_missed_errors; 671 u64 tx_errors; 672 u64 tx_fifo_errors; 673 u64 tx_aborted_errors; 674 u64 tx_window_errors; 675 u64 tx_carrier_errors; 676 u64 tx_pause; /* TX pause frames */ 677 u64 excecol; /* TX packets w/ excessive collisions */ 678 u64 deffer; /* TX packets deferred */ 679 u64 scc; /* packets TX after a single collision */ 680 u64 mcc; /* packets TX after multiple collisions */ 681 u64 latecol; /* TX packets w/ late collisions */ 682 u64 tx_underun; /* TX packets aborted due to TX FIFO underrun 683 * or TRD FIFO underrun */ 684 u64 tx_trunc; /* TX packets truncated due to size > MTU */ 685 u64 rx_pause; /* num Pause packets received. */ 686 u64 rx_rrd_ov; 687 u64 rx_trunc; 688 }; 689 690 /* hardware structure */ 691 struct atl1_hw { 692 u8 __iomem *hw_addr; 693 struct atl1_adapter *back; 694 enum atl1_dma_order dma_ord; 695 enum atl1_dma_rcb rcb_value; 696 enum atl1_dma_req_block dmar_block; 697 enum atl1_dma_req_block dmaw_block; 698 u8 preamble_len; 699 u8 max_retry; 700 u8 jam_ipg; /* IPG to start JAM for collision based flow 701 * control in half-duplex mode. In units of 702 * 8-bit time */ 703 u8 ipgt; /* Desired back to back inter-packet gap. 704 * The default is 96-bit time */ 705 u8 min_ifg; /* Minimum number of IFG to enforce in between 706 * receive frames. Frame gap below such IFP 707 * is dropped */ 708 u8 ipgr1; /* 64bit Carrier-Sense window */ 709 u8 ipgr2; /* 96-bit IPG window */ 710 u8 tpd_burst; /* Number of TPD to prefetch in cache-aligned 711 * burst. Each TPD is 16 bytes long */ 712 u8 rfd_burst; /* Number of RFD to prefetch in cache-aligned 713 * burst. Each RFD is 12 bytes long */ 714 u8 rfd_fetch_gap; 715 u8 rrd_burst; /* Threshold number of RRDs that can be retired 716 * in a burst. Each RRD is 16 bytes long */ 717 u8 tpd_fetch_th; 718 u8 tpd_fetch_gap; 719 u16 tx_jumbo_task_th; 720 u16 txf_burst; /* Number of data bytes to read in a cache- 721 * aligned burst. Each SRAM entry is 8 bytes */ 722 u16 rx_jumbo_th; /* Jumbo packet size for non-VLAN packet. VLAN 723 * packets should add 4 bytes */ 724 u16 rx_jumbo_lkah; 725 u16 rrd_ret_timer; /* RRD retirement timer. Decrement by 1 after 726 * every 512ns passes. */ 727 u16 lcol; /* Collision Window */ 728 729 u16 cmb_tpd; 730 u16 cmb_rrd; 731 u16 cmb_rx_timer; 732 u16 cmb_tx_timer; 733 u32 smb_timer; 734 u16 media_type; 735 u16 autoneg_advertised; 736 737 u16 mii_autoneg_adv_reg; 738 u16 mii_1000t_ctrl_reg; 739 740 u32 max_frame_size; 741 u32 min_frame_size; 742 743 u16 dev_rev; 744 745 /* spi flash */ 746 u8 flash_vendor; 747 748 u8 mac_addr[ETH_ALEN]; 749 u8 perm_mac_addr[ETH_ALEN]; 750 751 bool phy_configured; 752 }; 753 754 struct atl1_adapter { 755 struct net_device *netdev; 756 struct pci_dev *pdev; 757 758 struct atl1_sft_stats soft_stats; 759 struct vlan_group *vlgrp; 760 u32 rx_buffer_len; 761 u32 wol; 762 u16 link_speed; 763 u16 link_duplex; 764 spinlock_t lock; 765 struct work_struct tx_timeout_task; 766 struct work_struct link_chg_task; 767 struct work_struct pcie_dma_to_rst_task; 768 769 struct timer_list phy_config_timer; 770 bool phy_timer_pending; 771 772 /* all descriptor rings' memory */ 773 struct atl1_ring_header ring_header; 774 775 /* TX */ 776 struct atl1_tpd_ring tpd_ring; 777 spinlock_t mb_lock; 778 779 /* RX */ 780 struct atl1_rfd_ring rfd_ring; 781 struct atl1_rrd_ring rrd_ring; 782 u64 hw_csum_err; 783 u64 hw_csum_good; 784 u32 msg_enable; 785 u16 imt; /* interrupt moderator timer (2us resolution) */ 786 u16 ict; /* interrupt clear timer (2us resolution */ 787 struct mii_if_info mii; /* MII interface info */ 788 789 u32 bd_number; /* board number */ 790 bool pci_using_64; 791 struct atl1_hw hw; 792 struct atl1_smb smb; 793 struct atl1_cmb cmb; 794 }; 795 796 #endif /* ATL1_H */ 797