1 /*
2 * drivers/net/gianfar.h
3 *
4 * Gianfar Ethernet Driver
5 * Driver for FEC on MPC8540 and TSEC on MPC8540/MPC8560
6 * Based on 8260_io/fcc_enet.c
7 *
8 * Author: Andy Fleming
9 * Maintainer: Kumar Gala
10 *
11 * Copyright (c) 2002-2004 Freescale Semiconductor, Inc.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 * Still left to do:
19 * -Add support for module parameters
20 * -Add patch for ethtool phys id
21 */
22 #ifndef __GIANFAR_H
23 #define __GIANFAR_H
24
25 #include <linux/kernel.h>
26 #include <linux/sched.h>
27 #include <linux/string.h>
28 #include <linux/errno.h>
29 #include <linux/slab.h>
30 #include <linux/interrupt.h>
31 #include <linux/init.h>
32 #include <linux/delay.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/skbuff.h>
36 #include <linux/spinlock.h>
37 #include <linux/mm.h>
38 #include <linux/mii.h>
39 #include <linux/phy.h>
40
41 #include <asm/io.h>
42 #include <asm/irq.h>
43 #include <asm/uaccess.h>
44 #include <linux/module.h>
45 #include <linux/crc32.h>
46 #include <linux/workqueue.h>
47 #include <linux/ethtool.h>
48 #include <linux/fsl_devices.h>
49 #include "gianfar_mii.h"
50
51 /* The maximum number of packets to be handled in one call of gfar_poll */
52 #define GFAR_DEV_WEIGHT 64
53
54 /* Length for FCB */
55 #define GMAC_FCB_LEN 8
56
57 /* Default padding amount */
58 #define DEFAULT_PADDING 2
59
60 /* Number of bytes to align the rx bufs to */
61 #define RXBUF_ALIGNMENT 64
62
63 /* The number of bytes which composes a unit for the purpose of
64 * allocating data buffers. ie-for any given MTU, the data buffer
65 * will be the next highest multiple of 512 bytes. */
66 #define INCREMENTAL_BUFFER_SIZE 512
67
68
69 #define MAC_ADDR_LEN 6
70
71 #define PHY_INIT_TIMEOUT 100000
72 #define GFAR_PHY_CHANGE_TIME 2
73
74 #define DEVICE_NAME "%s: Gianfar Ethernet Controller Version 1.2, "
75 #define DRV_NAME "gfar-enet"
76 extern const char gfar_driver_name[];
77 extern const char gfar_driver_version[];
78
79 /* These need to be powers of 2 for this driver */
80 #define DEFAULT_TX_RING_SIZE 256
81 #define DEFAULT_RX_RING_SIZE 256
82
83 #define GFAR_RX_MAX_RING_SIZE 256
84 #define GFAR_TX_MAX_RING_SIZE 256
85
86 #define GFAR_MAX_FIFO_THRESHOLD 511
87 #define GFAR_MAX_FIFO_STARVE 511
88 #define GFAR_MAX_FIFO_STARVE_OFF 511
89
90 #define DEFAULT_RX_BUFFER_SIZE 1536
91 #define TX_RING_MOD_MASK(size) (size-1)
92 #define RX_RING_MOD_MASK(size) (size-1)
93 #define JUMBO_BUFFER_SIZE 9728
94 #define JUMBO_FRAME_SIZE 9600
95
96 #define DEFAULT_FIFO_TX_THR 0x100
97 #define DEFAULT_FIFO_TX_STARVE 0x40
98 #define DEFAULT_FIFO_TX_STARVE_OFF 0x80
99 #define DEFAULT_BD_STASH 1
100 #define DEFAULT_STASH_LENGTH 96
101 #define DEFAULT_STASH_INDEX 0
102
103 /* The number of Exact Match registers */
104 #define GFAR_EM_NUM 15
105
106 /* Latency of interface clock in nanoseconds */
107 /* Interface clock latency , in this case, means the
108 * time described by a value of 1 in the interrupt
109 * coalescing registers' time fields. Since those fields
110 * refer to the time it takes for 64 clocks to pass, the
111 * latencies are as such:
112 * GBIT = 125MHz => 8ns/clock => 8*64 ns / tick
113 * 100 = 25 MHz => 40ns/clock => 40*64 ns / tick
114 * 10 = 2.5 MHz => 400ns/clock => 400*64 ns / tick
115 */
116 #define GFAR_GBIT_TIME 512
117 #define GFAR_100_TIME 2560
118 #define GFAR_10_TIME 25600
119
120 #define DEFAULT_TX_COALESCE 1
121 #define DEFAULT_TXCOUNT 16
122 #define DEFAULT_TXTIME 21
123
124 #define DEFAULT_RXTIME 21
125
126 #define DEFAULT_RX_COALESCE 0
127 #define DEFAULT_RXCOUNT 0
128
129 #define MIIMCFG_INIT_VALUE 0x00000007
130 #define MIIMCFG_RESET 0x80000000
131 #define MIIMIND_BUSY 0x00000001
132
133 /* TBI register addresses */
134 #define MII_TBICON 0x11
135
136 /* TBICON register bit fields */
137 #define TBICON_CLK_SELECT 0x0020
138
139 /* MAC register bits */
140 #define MACCFG1_SOFT_RESET 0x80000000
141 #define MACCFG1_RESET_RX_MC 0x00080000
142 #define MACCFG1_RESET_TX_MC 0x00040000
143 #define MACCFG1_RESET_RX_FUN 0x00020000
144 #define MACCFG1_RESET_TX_FUN 0x00010000
145 #define MACCFG1_LOOPBACK 0x00000100
146 #define MACCFG1_RX_FLOW 0x00000020
147 #define MACCFG1_TX_FLOW 0x00000010
148 #define MACCFG1_SYNCD_RX_EN 0x00000008
149 #define MACCFG1_RX_EN 0x00000004
150 #define MACCFG1_SYNCD_TX_EN 0x00000002
151 #define MACCFG1_TX_EN 0x00000001
152
153 #define MACCFG2_INIT_SETTINGS 0x00007205
154 #define MACCFG2_FULL_DUPLEX 0x00000001
155 #define MACCFG2_IF 0x00000300
156 #define MACCFG2_MII 0x00000100
157 #define MACCFG2_GMII 0x00000200
158 #define MACCFG2_HUGEFRAME 0x00000020
159 #define MACCFG2_LENGTHCHECK 0x00000010
160 #define MACCFG2_MPEN 0x00000008
161
162 #define ECNTRL_INIT_SETTINGS 0x00001000
163 #define ECNTRL_TBI_MODE 0x00000020
164 #define ECNTRL_REDUCED_MODE 0x00000010
165 #define ECNTRL_R100 0x00000008
166 #define ECNTRL_REDUCED_MII_MODE 0x00000004
167 #define ECNTRL_SGMII_MODE 0x00000002
168
169 #define MRBLR_INIT_SETTINGS DEFAULT_RX_BUFFER_SIZE
170
171 #define MINFLR_INIT_SETTINGS 0x00000040
172
173 /* Init to do tx snooping for buffers and descriptors */
174 #define DMACTRL_INIT_SETTINGS 0x000000c3
175 #define DMACTRL_GRS 0x00000010
176 #define DMACTRL_GTS 0x00000008
177
178 #define TSTAT_CLEAR_THALT 0x80000000
179
180 /* Interrupt coalescing macros */
181 #define IC_ICEN 0x80000000
182 #define IC_ICFT_MASK 0x1fe00000
183 #define IC_ICFT_SHIFT 21
184 #define mk_ic_icft(x) \
185 (((unsigned int)x << IC_ICFT_SHIFT)&IC_ICFT_MASK)
186 #define IC_ICTT_MASK 0x0000ffff
187 #define mk_ic_ictt(x) (x&IC_ICTT_MASK)
188
189 #define mk_ic_value(count, time) (IC_ICEN | \
190 mk_ic_icft(count) | \
191 mk_ic_ictt(time))
192 #define get_icft_value(ic) (((unsigned long)ic & IC_ICFT_MASK) >> \
193 IC_ICFT_SHIFT)
194 #define get_ictt_value(ic) ((unsigned long)ic & IC_ICTT_MASK)
195
196 #define DEFAULT_TXIC mk_ic_value(DEFAULT_TXCOUNT, DEFAULT_TXTIME)
197 #define DEFAULT_RXIC mk_ic_value(DEFAULT_RXCOUNT, DEFAULT_RXTIME)
198
199 #define skip_bd(bdp, stride, base, ring_size) ({ \
200 typeof(bdp) new_bd = (bdp) + (stride); \
201 (new_bd >= (base) + (ring_size)) ? (new_bd - (ring_size)) : new_bd; })
202
203 #define next_bd(bdp, base, ring_size) skip_bd(bdp, 1, base, ring_size)
204
205 #define RCTRL_PAL_MASK 0x001f0000
206 #define RCTRL_VLEX 0x00002000
207 #define RCTRL_FILREN 0x00001000
208 #define RCTRL_GHTX 0x00000400
209 #define RCTRL_IPCSEN 0x00000200
210 #define RCTRL_TUCSEN 0x00000100
211 #define RCTRL_PRSDEP_MASK 0x000000c0
212 #define RCTRL_PRSDEP_INIT 0x000000c0
213 #define RCTRL_PROM 0x00000008
214 #define RCTRL_EMEN 0x00000002
215 #define RCTRL_REQ_PARSER (RCTRL_VLEX | RCTRL_IPCSEN | \
216 RCTRL_TUCSEN)
217 #define RCTRL_CHECKSUMMING (RCTRL_IPCSEN | RCTRL_TUCSEN | \
218 RCTRL_PRSDEP_INIT)
219 #define RCTRL_EXTHASH (RCTRL_GHTX)
220 #define RCTRL_VLAN (RCTRL_PRSDEP_INIT)
221 #define RCTRL_PADDING(x) ((x << 16) & RCTRL_PAL_MASK)
222
223
224 #define RSTAT_CLEAR_RHALT 0x00800000
225
226 #define TCTRL_IPCSEN 0x00004000
227 #define TCTRL_TUCSEN 0x00002000
228 #define TCTRL_VLINS 0x00001000
229 #define TCTRL_INIT_CSUM (TCTRL_TUCSEN | TCTRL_IPCSEN)
230
231 #define IEVENT_INIT_CLEAR 0xffffffff
232 #define IEVENT_BABR 0x80000000
233 #define IEVENT_RXC 0x40000000
234 #define IEVENT_BSY 0x20000000
235 #define IEVENT_EBERR 0x10000000
236 #define IEVENT_MSRO 0x04000000
237 #define IEVENT_GTSC 0x02000000
238 #define IEVENT_BABT 0x01000000
239 #define IEVENT_TXC 0x00800000
240 #define IEVENT_TXE 0x00400000
241 #define IEVENT_TXB 0x00200000
242 #define IEVENT_TXF 0x00100000
243 #define IEVENT_LC 0x00040000
244 #define IEVENT_CRL 0x00020000
245 #define IEVENT_XFUN 0x00010000
246 #define IEVENT_RXB0 0x00008000
247 #define IEVENT_MAG 0x00000800
248 #define IEVENT_GRSC 0x00000100
249 #define IEVENT_RXF0 0x00000080
250 #define IEVENT_FIR 0x00000008
251 #define IEVENT_FIQ 0x00000004
252 #define IEVENT_DPE 0x00000002
253 #define IEVENT_PERR 0x00000001
254 #define IEVENT_RX_MASK (IEVENT_RXB0 | IEVENT_RXF0 | IEVENT_BSY)
255 #define IEVENT_TX_MASK (IEVENT_TXB | IEVENT_TXF)
256 #define IEVENT_RTX_MASK (IEVENT_RX_MASK | IEVENT_TX_MASK)
257 #define IEVENT_ERR_MASK \
258 (IEVENT_RXC | IEVENT_BSY | IEVENT_EBERR | IEVENT_MSRO | \
259 IEVENT_BABT | IEVENT_TXC | IEVENT_TXE | IEVENT_LC \
260 | IEVENT_CRL | IEVENT_XFUN | IEVENT_DPE | IEVENT_PERR \
261 | IEVENT_MAG)
262
263 #define IMASK_INIT_CLEAR 0x00000000
264 #define IMASK_BABR 0x80000000
265 #define IMASK_RXC 0x40000000
266 #define IMASK_BSY 0x20000000
267 #define IMASK_EBERR 0x10000000
268 #define IMASK_MSRO 0x04000000
269 #define IMASK_GRSC 0x02000000
270 #define IMASK_BABT 0x01000000
271 #define IMASK_TXC 0x00800000
272 #define IMASK_TXEEN 0x00400000
273 #define IMASK_TXBEN 0x00200000
274 #define IMASK_TXFEN 0x00100000
275 #define IMASK_LC 0x00040000
276 #define IMASK_CRL 0x00020000
277 #define IMASK_XFUN 0x00010000
278 #define IMASK_RXB0 0x00008000
279 #define IMASK_MAG 0x00000800
280 #define IMASK_GTSC 0x00000100
281 #define IMASK_RXFEN0 0x00000080
282 #define IMASK_FIR 0x00000008
283 #define IMASK_FIQ 0x00000004
284 #define IMASK_DPE 0x00000002
285 #define IMASK_PERR 0x00000001
286 #define IMASK_DEFAULT (IMASK_TXEEN | IMASK_TXFEN | IMASK_TXBEN | \
287 IMASK_RXFEN0 | IMASK_BSY | IMASK_EBERR | IMASK_BABR | \
288 IMASK_XFUN | IMASK_RXC | IMASK_BABT | IMASK_DPE \
289 | IMASK_PERR)
290 #define IMASK_RTX_DISABLED ((~(IMASK_RXFEN0 | IMASK_TXFEN | IMASK_BSY)) \
291 & IMASK_DEFAULT)
292
293 /* Fifo management */
294 #define FIFO_TX_THR_MASK 0x01ff
295 #define FIFO_TX_STARVE_MASK 0x01ff
296 #define FIFO_TX_STARVE_OFF_MASK 0x01ff
297
298 /* Attribute fields */
299
300 /* This enables rx snooping for buffers and descriptors */
301 #define ATTR_BDSTASH 0x00000800
302
303 #define ATTR_BUFSTASH 0x00004000
304
305 #define ATTR_SNOOPING 0x000000c0
306 #define ATTR_INIT_SETTINGS ATTR_SNOOPING
307
308 #define ATTRELI_INIT_SETTINGS 0x0
309 #define ATTRELI_EL_MASK 0x3fff0000
310 #define ATTRELI_EL(x) (x << 16)
311 #define ATTRELI_EI_MASK 0x00003fff
312 #define ATTRELI_EI(x) (x)
313
314 #define BD_LFLAG(flags) ((flags) << 16)
315 #define BD_LENGTH_MASK 0x0000ffff
316
317 /* TxBD status field bits */
318 #define TXBD_READY 0x8000
319 #define TXBD_PADCRC 0x4000
320 #define TXBD_WRAP 0x2000
321 #define TXBD_INTERRUPT 0x1000
322 #define TXBD_LAST 0x0800
323 #define TXBD_CRC 0x0400
324 #define TXBD_DEF 0x0200
325 #define TXBD_HUGEFRAME 0x0080
326 #define TXBD_LATECOLLISION 0x0080
327 #define TXBD_RETRYLIMIT 0x0040
328 #define TXBD_RETRYCOUNTMASK 0x003c
329 #define TXBD_UNDERRUN 0x0002
330 #define TXBD_TOE 0x0002
331
332 /* Tx FCB param bits */
333 #define TXFCB_VLN 0x80
334 #define TXFCB_IP 0x40
335 #define TXFCB_IP6 0x20
336 #define TXFCB_TUP 0x10
337 #define TXFCB_UDP 0x08
338 #define TXFCB_CIP 0x04
339 #define TXFCB_CTU 0x02
340 #define TXFCB_NPH 0x01
341 #define TXFCB_DEFAULT (TXFCB_IP|TXFCB_TUP|TXFCB_CTU|TXFCB_NPH)
342
343 /* RxBD status field bits */
344 #define RXBD_EMPTY 0x8000
345 #define RXBD_RO1 0x4000
346 #define RXBD_WRAP 0x2000
347 #define RXBD_INTERRUPT 0x1000
348 #define RXBD_LAST 0x0800
349 #define RXBD_FIRST 0x0400
350 #define RXBD_MISS 0x0100
351 #define RXBD_BROADCAST 0x0080
352 #define RXBD_MULTICAST 0x0040
353 #define RXBD_LARGE 0x0020
354 #define RXBD_NONOCTET 0x0010
355 #define RXBD_SHORT 0x0008
356 #define RXBD_CRCERR 0x0004
357 #define RXBD_OVERRUN 0x0002
358 #define RXBD_TRUNCATED 0x0001
359 #define RXBD_STATS 0x01ff
360 #define RXBD_ERR (RXBD_LARGE | RXBD_SHORT | RXBD_NONOCTET \
361 | RXBD_CRCERR | RXBD_OVERRUN \
362 | RXBD_TRUNCATED)
363
364 /* Rx FCB status field bits */
365 #define RXFCB_VLN 0x8000
366 #define RXFCB_IP 0x4000
367 #define RXFCB_IP6 0x2000
368 #define RXFCB_TUP 0x1000
369 #define RXFCB_CIP 0x0800
370 #define RXFCB_CTU 0x0400
371 #define RXFCB_EIP 0x0200
372 #define RXFCB_ETU 0x0100
373 #define RXFCB_CSUM_MASK 0x0f00
374 #define RXFCB_PERR_MASK 0x000c
375 #define RXFCB_PERR_BADL3 0x0008
376
377 #define GFAR_INT_NAME_MAX IFNAMSIZ + 4
378
379 struct txbd8
380 {
381 union {
382 struct {
383 u16 status; /* Status Fields */
384 u16 length; /* Buffer length */
385 };
386 u32 lstatus;
387 };
388 u32 bufPtr; /* Buffer Pointer */
389 };
390
391 struct txfcb {
392 u8 flags;
393 u8 reserved;
394 u8 l4os; /* Level 4 Header Offset */
395 u8 l3os; /* Level 3 Header Offset */
396 u16 phcs; /* Pseudo-header Checksum */
397 u16 vlctl; /* VLAN control word */
398 };
399
400 struct rxbd8
401 {
402 union {
403 struct {
404 u16 status; /* Status Fields */
405 u16 length; /* Buffer Length */
406 };
407 u32 lstatus;
408 };
409 u32 bufPtr; /* Buffer Pointer */
410 };
411
412 struct rxfcb {
413 u16 flags;
414 u8 rq; /* Receive Queue index */
415 u8 pro; /* Layer 4 Protocol */
416 u16 reserved;
417 u16 vlctl; /* VLAN control word */
418 };
419
420 struct rmon_mib
421 {
422 u32 tr64; /* 0x.680 - Transmit and Receive 64-byte Frame Counter */
423 u32 tr127; /* 0x.684 - Transmit and Receive 65-127 byte Frame Counter */
424 u32 tr255; /* 0x.688 - Transmit and Receive 128-255 byte Frame Counter */
425 u32 tr511; /* 0x.68c - Transmit and Receive 256-511 byte Frame Counter */
426 u32 tr1k; /* 0x.690 - Transmit and Receive 512-1023 byte Frame Counter */
427 u32 trmax; /* 0x.694 - Transmit and Receive 1024-1518 byte Frame Counter */
428 u32 trmgv; /* 0x.698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */
429 u32 rbyt; /* 0x.69c - Receive Byte Counter */
430 u32 rpkt; /* 0x.6a0 - Receive Packet Counter */
431 u32 rfcs; /* 0x.6a4 - Receive FCS Error Counter */
432 u32 rmca; /* 0x.6a8 - Receive Multicast Packet Counter */
433 u32 rbca; /* 0x.6ac - Receive Broadcast Packet Counter */
434 u32 rxcf; /* 0x.6b0 - Receive Control Frame Packet Counter */
435 u32 rxpf; /* 0x.6b4 - Receive Pause Frame Packet Counter */
436 u32 rxuo; /* 0x.6b8 - Receive Unknown OP Code Counter */
437 u32 raln; /* 0x.6bc - Receive Alignment Error Counter */
438 u32 rflr; /* 0x.6c0 - Receive Frame Length Error Counter */
439 u32 rcde; /* 0x.6c4 - Receive Code Error Counter */
440 u32 rcse; /* 0x.6c8 - Receive Carrier Sense Error Counter */
441 u32 rund; /* 0x.6cc - Receive Undersize Packet Counter */
442 u32 rovr; /* 0x.6d0 - Receive Oversize Packet Counter */
443 u32 rfrg; /* 0x.6d4 - Receive Fragments Counter */
444 u32 rjbr; /* 0x.6d8 - Receive Jabber Counter */
445 u32 rdrp; /* 0x.6dc - Receive Drop Counter */
446 u32 tbyt; /* 0x.6e0 - Transmit Byte Counter Counter */
447 u32 tpkt; /* 0x.6e4 - Transmit Packet Counter */
448 u32 tmca; /* 0x.6e8 - Transmit Multicast Packet Counter */
449 u32 tbca; /* 0x.6ec - Transmit Broadcast Packet Counter */
450 u32 txpf; /* 0x.6f0 - Transmit Pause Control Frame Counter */
451 u32 tdfr; /* 0x.6f4 - Transmit Deferral Packet Counter */
452 u32 tedf; /* 0x.6f8 - Transmit Excessive Deferral Packet Counter */
453 u32 tscl; /* 0x.6fc - Transmit Single Collision Packet Counter */
454 u32 tmcl; /* 0x.700 - Transmit Multiple Collision Packet Counter */
455 u32 tlcl; /* 0x.704 - Transmit Late Collision Packet Counter */
456 u32 txcl; /* 0x.708 - Transmit Excessive Collision Packet Counter */
457 u32 tncl; /* 0x.70c - Transmit Total Collision Counter */
458 u8 res1[4];
459 u32 tdrp; /* 0x.714 - Transmit Drop Frame Counter */
460 u32 tjbr; /* 0x.718 - Transmit Jabber Frame Counter */
461 u32 tfcs; /* 0x.71c - Transmit FCS Error Counter */
462 u32 txcf; /* 0x.720 - Transmit Control Frame Counter */
463 u32 tovr; /* 0x.724 - Transmit Oversize Frame Counter */
464 u32 tund; /* 0x.728 - Transmit Undersize Frame Counter */
465 u32 tfrg; /* 0x.72c - Transmit Fragments Frame Counter */
466 u32 car1; /* 0x.730 - Carry Register One */
467 u32 car2; /* 0x.734 - Carry Register Two */
468 u32 cam1; /* 0x.738 - Carry Mask Register One */
469 u32 cam2; /* 0x.73c - Carry Mask Register Two */
470 };
471
472 struct gfar_extra_stats {
473 u64 kernel_dropped;
474 u64 rx_large;
475 u64 rx_short;
476 u64 rx_nonoctet;
477 u64 rx_crcerr;
478 u64 rx_overrun;
479 u64 rx_bsy;
480 u64 rx_babr;
481 u64 rx_trunc;
482 u64 eberr;
483 u64 tx_babt;
484 u64 tx_underrun;
485 u64 rx_skbmissing;
486 u64 tx_timeout;
487 };
488
489 #define GFAR_RMON_LEN ((sizeof(struct rmon_mib) - 16)/sizeof(u32))
490 #define GFAR_EXTRA_STATS_LEN (sizeof(struct gfar_extra_stats)/sizeof(u64))
491
492 /* Number of stats in the stats structure (ignore car and cam regs)*/
493 #define GFAR_STATS_LEN (GFAR_RMON_LEN + GFAR_EXTRA_STATS_LEN)
494
495 #define GFAR_INFOSTR_LEN 32
496
497 struct gfar_stats {
498 u64 extra[GFAR_EXTRA_STATS_LEN];
499 u64 rmon[GFAR_RMON_LEN];
500 };
501
502
503 struct gfar {
504 u32 tsec_id; /* 0x.000 - Controller ID register */
505 u8 res1[12];
506 u32 ievent; /* 0x.010 - Interrupt Event Register */
507 u32 imask; /* 0x.014 - Interrupt Mask Register */
508 u32 edis; /* 0x.018 - Error Disabled Register */
509 u8 res2[4];
510 u32 ecntrl; /* 0x.020 - Ethernet Control Register */
511 u32 minflr; /* 0x.024 - Minimum Frame Length Register */
512 u32 ptv; /* 0x.028 - Pause Time Value Register */
513 u32 dmactrl; /* 0x.02c - DMA Control Register */
514 u32 tbipa; /* 0x.030 - TBI PHY Address Register */
515 u8 res3[88];
516 u32 fifo_tx_thr; /* 0x.08c - FIFO transmit threshold register */
517 u8 res4[8];
518 u32 fifo_tx_starve; /* 0x.098 - FIFO transmit starve register */
519 u32 fifo_tx_starve_shutoff; /* 0x.09c - FIFO transmit starve shutoff register */
520 u8 res5[4];
521 u32 fifo_rx_pause; /* 0x.0a4 - FIFO receive pause threshold register */
522 u32 fifo_rx_alarm; /* 0x.0a8 - FIFO receive alarm threshold register */
523 u8 res6[84];
524 u32 tctrl; /* 0x.100 - Transmit Control Register */
525 u32 tstat; /* 0x.104 - Transmit Status Register */
526 u32 dfvlan; /* 0x.108 - Default VLAN Control word */
527 u32 tbdlen; /* 0x.10c - Transmit Buffer Descriptor Data Length Register */
528 u32 txic; /* 0x.110 - Transmit Interrupt Coalescing Configuration Register */
529 u32 tqueue; /* 0x.114 - Transmit queue control register */
530 u8 res7[40];
531 u32 tr03wt; /* 0x.140 - TxBD Rings 0-3 round-robin weightings */
532 u32 tr47wt; /* 0x.144 - TxBD Rings 4-7 round-robin weightings */
533 u8 res8[52];
534 u32 tbdbph; /* 0x.17c - Tx data buffer pointer high */
535 u8 res9a[4];
536 u32 tbptr0; /* 0x.184 - TxBD Pointer for ring 0 */
537 u8 res9b[4];
538 u32 tbptr1; /* 0x.18c - TxBD Pointer for ring 1 */
539 u8 res9c[4];
540 u32 tbptr2; /* 0x.194 - TxBD Pointer for ring 2 */
541 u8 res9d[4];
542 u32 tbptr3; /* 0x.19c - TxBD Pointer for ring 3 */
543 u8 res9e[4];
544 u32 tbptr4; /* 0x.1a4 - TxBD Pointer for ring 4 */
545 u8 res9f[4];
546 u32 tbptr5; /* 0x.1ac - TxBD Pointer for ring 5 */
547 u8 res9g[4];
548 u32 tbptr6; /* 0x.1b4 - TxBD Pointer for ring 6 */
549 u8 res9h[4];
550 u32 tbptr7; /* 0x.1bc - TxBD Pointer for ring 7 */
551 u8 res9[64];
552 u32 tbaseh; /* 0x.200 - TxBD base address high */
553 u32 tbase0; /* 0x.204 - TxBD Base Address of ring 0 */
554 u8 res10a[4];
555 u32 tbase1; /* 0x.20c - TxBD Base Address of ring 1 */
556 u8 res10b[4];
557 u32 tbase2; /* 0x.214 - TxBD Base Address of ring 2 */
558 u8 res10c[4];
559 u32 tbase3; /* 0x.21c - TxBD Base Address of ring 3 */
560 u8 res10d[4];
561 u32 tbase4; /* 0x.224 - TxBD Base Address of ring 4 */
562 u8 res10e[4];
563 u32 tbase5; /* 0x.22c - TxBD Base Address of ring 5 */
564 u8 res10f[4];
565 u32 tbase6; /* 0x.234 - TxBD Base Address of ring 6 */
566 u8 res10g[4];
567 u32 tbase7; /* 0x.23c - TxBD Base Address of ring 7 */
568 u8 res10[192];
569 u32 rctrl; /* 0x.300 - Receive Control Register */
570 u32 rstat; /* 0x.304 - Receive Status Register */
571 u8 res12[8];
572 u32 rxic; /* 0x.310 - Receive Interrupt Coalescing Configuration Register */
573 u32 rqueue; /* 0x.314 - Receive queue control register */
574 u8 res13[24];
575 u32 rbifx; /* 0x.330 - Receive bit field extract control register */
576 u32 rqfar; /* 0x.334 - Receive queue filing table address register */
577 u32 rqfcr; /* 0x.338 - Receive queue filing table control register */
578 u32 rqfpr; /* 0x.33c - Receive queue filing table property register */
579 u32 mrblr; /* 0x.340 - Maximum Receive Buffer Length Register */
580 u8 res14[56];
581 u32 rbdbph; /* 0x.37c - Rx data buffer pointer high */
582 u8 res15a[4];
583 u32 rbptr0; /* 0x.384 - RxBD pointer for ring 0 */
584 u8 res15b[4];
585 u32 rbptr1; /* 0x.38c - RxBD pointer for ring 1 */
586 u8 res15c[4];
587 u32 rbptr2; /* 0x.394 - RxBD pointer for ring 2 */
588 u8 res15d[4];
589 u32 rbptr3; /* 0x.39c - RxBD pointer for ring 3 */
590 u8 res15e[4];
591 u32 rbptr4; /* 0x.3a4 - RxBD pointer for ring 4 */
592 u8 res15f[4];
593 u32 rbptr5; /* 0x.3ac - RxBD pointer for ring 5 */
594 u8 res15g[4];
595 u32 rbptr6; /* 0x.3b4 - RxBD pointer for ring 6 */
596 u8 res15h[4];
597 u32 rbptr7; /* 0x.3bc - RxBD pointer for ring 7 */
598 u8 res16[64];
599 u32 rbaseh; /* 0x.400 - RxBD base address high */
600 u32 rbase0; /* 0x.404 - RxBD base address of ring 0 */
601 u8 res17a[4];
602 u32 rbase1; /* 0x.40c - RxBD base address of ring 1 */
603 u8 res17b[4];
604 u32 rbase2; /* 0x.414 - RxBD base address of ring 2 */
605 u8 res17c[4];
606 u32 rbase3; /* 0x.41c - RxBD base address of ring 3 */
607 u8 res17d[4];
608 u32 rbase4; /* 0x.424 - RxBD base address of ring 4 */
609 u8 res17e[4];
610 u32 rbase5; /* 0x.42c - RxBD base address of ring 5 */
611 u8 res17f[4];
612 u32 rbase6; /* 0x.434 - RxBD base address of ring 6 */
613 u8 res17g[4];
614 u32 rbase7; /* 0x.43c - RxBD base address of ring 7 */
615 u8 res17[192];
616 u32 maccfg1; /* 0x.500 - MAC Configuration 1 Register */
617 u32 maccfg2; /* 0x.504 - MAC Configuration 2 Register */
618 u32 ipgifg; /* 0x.508 - Inter Packet Gap/Inter Frame Gap Register */
619 u32 hafdup; /* 0x.50c - Half Duplex Register */
620 u32 maxfrm; /* 0x.510 - Maximum Frame Length Register */
621 u8 res18[12];
622 u8 gfar_mii_regs[24]; /* See gianfar_phy.h */
623 u8 res19[4];
624 u32 ifstat; /* 0x.53c - Interface Status Register */
625 u32 macstnaddr1; /* 0x.540 - Station Address Part 1 Register */
626 u32 macstnaddr2; /* 0x.544 - Station Address Part 2 Register */
627 u32 mac01addr1; /* 0x.548 - MAC exact match address 1, part 1 */
628 u32 mac01addr2; /* 0x.54c - MAC exact match address 1, part 2 */
629 u32 mac02addr1; /* 0x.550 - MAC exact match address 2, part 1 */
630 u32 mac02addr2; /* 0x.554 - MAC exact match address 2, part 2 */
631 u32 mac03addr1; /* 0x.558 - MAC exact match address 3, part 1 */
632 u32 mac03addr2; /* 0x.55c - MAC exact match address 3, part 2 */
633 u32 mac04addr1; /* 0x.560 - MAC exact match address 4, part 1 */
634 u32 mac04addr2; /* 0x.564 - MAC exact match address 4, part 2 */
635 u32 mac05addr1; /* 0x.568 - MAC exact match address 5, part 1 */
636 u32 mac05addr2; /* 0x.56c - MAC exact match address 5, part 2 */
637 u32 mac06addr1; /* 0x.570 - MAC exact match address 6, part 1 */
638 u32 mac06addr2; /* 0x.574 - MAC exact match address 6, part 2 */
639 u32 mac07addr1; /* 0x.578 - MAC exact match address 7, part 1 */
640 u32 mac07addr2; /* 0x.57c - MAC exact match address 7, part 2 */
641 u32 mac08addr1; /* 0x.580 - MAC exact match address 8, part 1 */
642 u32 mac08addr2; /* 0x.584 - MAC exact match address 8, part 2 */
643 u32 mac09addr1; /* 0x.588 - MAC exact match address 9, part 1 */
644 u32 mac09addr2; /* 0x.58c - MAC exact match address 9, part 2 */
645 u32 mac10addr1; /* 0x.590 - MAC exact match address 10, part 1*/
646 u32 mac10addr2; /* 0x.594 - MAC exact match address 10, part 2*/
647 u32 mac11addr1; /* 0x.598 - MAC exact match address 11, part 1*/
648 u32 mac11addr2; /* 0x.59c - MAC exact match address 11, part 2*/
649 u32 mac12addr1; /* 0x.5a0 - MAC exact match address 12, part 1*/
650 u32 mac12addr2; /* 0x.5a4 - MAC exact match address 12, part 2*/
651 u32 mac13addr1; /* 0x.5a8 - MAC exact match address 13, part 1*/
652 u32 mac13addr2; /* 0x.5ac - MAC exact match address 13, part 2*/
653 u32 mac14addr1; /* 0x.5b0 - MAC exact match address 14, part 1*/
654 u32 mac14addr2; /* 0x.5b4 - MAC exact match address 14, part 2*/
655 u32 mac15addr1; /* 0x.5b8 - MAC exact match address 15, part 1*/
656 u32 mac15addr2; /* 0x.5bc - MAC exact match address 15, part 2*/
657 u8 res20[192];
658 struct rmon_mib rmon; /* 0x.680-0x.73c */
659 u32 rrej; /* 0x.740 - Receive filer rejected packet counter */
660 u8 res21[188];
661 u32 igaddr0; /* 0x.800 - Indivdual/Group address register 0*/
662 u32 igaddr1; /* 0x.804 - Indivdual/Group address register 1*/
663 u32 igaddr2; /* 0x.808 - Indivdual/Group address register 2*/
664 u32 igaddr3; /* 0x.80c - Indivdual/Group address register 3*/
665 u32 igaddr4; /* 0x.810 - Indivdual/Group address register 4*/
666 u32 igaddr5; /* 0x.814 - Indivdual/Group address register 5*/
667 u32 igaddr6; /* 0x.818 - Indivdual/Group address register 6*/
668 u32 igaddr7; /* 0x.81c - Indivdual/Group address register 7*/
669 u8 res22[96];
670 u32 gaddr0; /* 0x.880 - Group address register 0 */
671 u32 gaddr1; /* 0x.884 - Group address register 1 */
672 u32 gaddr2; /* 0x.888 - Group address register 2 */
673 u32 gaddr3; /* 0x.88c - Group address register 3 */
674 u32 gaddr4; /* 0x.890 - Group address register 4 */
675 u32 gaddr5; /* 0x.894 - Group address register 5 */
676 u32 gaddr6; /* 0x.898 - Group address register 6 */
677 u32 gaddr7; /* 0x.89c - Group address register 7 */
678 u8 res23a[352];
679 u32 fifocfg; /* 0x.a00 - FIFO interface config register */
680 u8 res23b[252];
681 u8 res23c[248];
682 u32 attr; /* 0x.bf8 - Attributes Register */
683 u32 attreli; /* 0x.bfc - Attributes Extract Length and Extract Index Register */
684 u8 res24[1024];
685
686 };
687
688 /* Flags related to gianfar device features */
689 #define FSL_GIANFAR_DEV_HAS_GIGABIT 0x00000001
690 #define FSL_GIANFAR_DEV_HAS_COALESCE 0x00000002
691 #define FSL_GIANFAR_DEV_HAS_RMON 0x00000004
692 #define FSL_GIANFAR_DEV_HAS_MULTI_INTR 0x00000008
693 #define FSL_GIANFAR_DEV_HAS_CSUM 0x00000010
694 #define FSL_GIANFAR_DEV_HAS_VLAN 0x00000020
695 #define FSL_GIANFAR_DEV_HAS_EXTENDED_HASH 0x00000040
696 #define FSL_GIANFAR_DEV_HAS_PADDING 0x00000080
697 #define FSL_GIANFAR_DEV_HAS_MAGIC_PACKET 0x00000100
698 #define FSL_GIANFAR_DEV_HAS_BD_STASHING 0x00000200
699 #define FSL_GIANFAR_DEV_HAS_BUF_STASHING 0x00000400
700
701 /* Struct stolen almost completely (and shamelessly) from the FCC enet source
702 * (Ok, that's not so true anymore, but there is a family resemblence)
703 * The GFAR buffer descriptors track the ring buffers. The rx_bd_base
704 * and tx_bd_base always point to the currently available buffer.
705 * The dirty_tx tracks the current buffer that is being sent by the
706 * controller. The cur_tx and dirty_tx are equal under both completely
707 * empty and completely full conditions. The empty/ready indicator in
708 * the buffer descriptor determines the actual condition.
709 */
710 struct gfar_private {
711 /* Fields controlled by TX lock */
712 spinlock_t txlock;
713
714 /* Pointer to the array of skbuffs */
715 struct sk_buff ** tx_skbuff;
716
717 /* next free skb in the array */
718 u16 skb_curtx;
719
720 /* First skb in line to be transmitted */
721 u16 skb_dirtytx;
722
723 /* Configuration info for the coalescing features */
724 unsigned char txcoalescing;
725 unsigned long txic;
726
727 /* Buffer descriptor pointers */
728 struct txbd8 *tx_bd_base; /* First tx buffer descriptor */
729 struct txbd8 *cur_tx; /* Next free ring entry */
730 struct txbd8 *dirty_tx; /* First buffer in line
731 to be transmitted */
732 unsigned int tx_ring_size;
733 unsigned int num_txbdfree; /* number of TxBDs free */
734
735 /* RX Locked fields */
736 spinlock_t rxlock;
737
738 struct device_node *node;
739 struct net_device *dev;
740 struct napi_struct napi;
741
742 /* skb array and index */
743 struct sk_buff ** rx_skbuff;
744 u16 skb_currx;
745
746 /* RX Coalescing values */
747 unsigned char rxcoalescing;
748 unsigned long rxic;
749
750 struct rxbd8 *rx_bd_base; /* First Rx buffers */
751 struct rxbd8 *cur_rx; /* Next free rx ring entry */
752
753 /* RX parameters */
754 unsigned int rx_ring_size;
755 unsigned int rx_buffer_size;
756 unsigned int rx_stash_size;
757 unsigned int rx_stash_index;
758
759 struct vlan_group *vlgrp;
760
761 /* Unprotected fields */
762 /* Pointer to the GFAR memory mapped Registers */
763 struct gfar __iomem *regs;
764
765 /* Hash registers and their width */
766 u32 __iomem *hash_regs[16];
767 int hash_width;
768
769 /* global parameters */
770 unsigned int fifo_threshold;
771 unsigned int fifo_starve;
772 unsigned int fifo_starve_off;
773
774 /* Bitfield update lock */
775 spinlock_t bflock;
776
777 phy_interface_t interface;
778 char phy_bus_id[BUS_ID_SIZE];
779 u32 device_flags;
780 unsigned char rx_csum_enable:1,
781 extended_hash:1,
782 bd_stash_en:1,
783 wol_en:1; /* Wake-on-LAN enabled */
784 unsigned short padding;
785
786 unsigned int interruptTransmit;
787 unsigned int interruptReceive;
788 unsigned int interruptError;
789
790 /* PHY stuff */
791 struct phy_device *phydev;
792 struct phy_device *tbiphy;
793 struct mii_bus *mii_bus;
794 int oldspeed;
795 int oldduplex;
796 int oldlink;
797
798 uint32_t msg_enable;
799
800 struct work_struct reset_task;
801
802 char int_name_tx[GFAR_INT_NAME_MAX];
803 char int_name_rx[GFAR_INT_NAME_MAX];
804 char int_name_er[GFAR_INT_NAME_MAX];
805
806 /* Network Statistics */
807 struct gfar_extra_stats extra_stats;
808 };
809
gfar_read(volatile unsigned __iomem * addr)810 static inline u32 gfar_read(volatile unsigned __iomem *addr)
811 {
812 u32 val;
813 val = in_be32(addr);
814 return val;
815 }
816
gfar_write(volatile unsigned __iomem * addr,u32 val)817 static inline void gfar_write(volatile unsigned __iomem *addr, u32 val)
818 {
819 out_be32(addr, val);
820 }
821
822 extern irqreturn_t gfar_receive(int irq, void *dev_id);
823 extern int startup_gfar(struct net_device *dev);
824 extern void stop_gfar(struct net_device *dev);
825 extern void gfar_halt(struct net_device *dev);
826 extern void gfar_phy_test(struct mii_bus *bus, struct phy_device *phydev,
827 int enable, u32 regnum, u32 read);
828 void gfar_init_sysfs(struct net_device *dev);
829 int gfar_local_mdio_write(struct gfar_mii __iomem *regs, int mii_id,
830 int regnum, u16 value);
831 int gfar_local_mdio_read(struct gfar_mii __iomem *regs, int mii_id, int regnum);
832
833 #endif /* __GIANFAR_H */
834