1 /*
2 * linux/arch/ia64/kernel/irq_ia64.c
3 *
4 * Copyright (C) 1998-2001 Hewlett-Packard Co
5 * Stephane Eranian <eranian@hpl.hp.com>
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 *
8 * 6/10/99: Updated to bring in sync with x86 version to facilitate
9 * support for SMP and different interrupt controllers.
10 *
11 * 09/15/00 Goutham Rao <goutham.rao@intel.com> Implemented pci_irq_to_vector
12 * PCI to vector allocation routine.
13 * 04/14/2004 Ashok Raj <ashok.raj@intel.com>
14 * Added CPU Hotplug handling for IPF.
15 */
16
17 #include <linux/module.h>
18
19 #include <linux/jiffies.h>
20 #include <linux/errno.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/ioport.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/slab.h>
26 #include <linux/ptrace.h>
27 #include <linux/random.h> /* for rand_initialize_irq() */
28 #include <linux/signal.h>
29 #include <linux/smp.h>
30 #include <linux/threads.h>
31 #include <linux/bitops.h>
32 #include <linux/irq.h>
33
34 #include <asm/delay.h>
35 #include <asm/intrinsics.h>
36 #include <asm/io.h>
37 #include <asm/hw_irq.h>
38 #include <asm/machvec.h>
39 #include <asm/pgtable.h>
40 #include <asm/system.h>
41 #include <asm/tlbflush.h>
42
43 #ifdef CONFIG_PERFMON
44 # include <asm/perfmon.h>
45 #endif
46
47 #define IRQ_DEBUG 0
48
49 #define IRQ_VECTOR_UNASSIGNED (0)
50
51 #define IRQ_UNUSED (0)
52 #define IRQ_USED (1)
53 #define IRQ_RSVD (2)
54
55 /* These can be overridden in platform_irq_init */
56 int ia64_first_device_vector = IA64_DEF_FIRST_DEVICE_VECTOR;
57 int ia64_last_device_vector = IA64_DEF_LAST_DEVICE_VECTOR;
58
59 /* default base addr of IPI table */
60 void __iomem *ipi_base_addr = ((void __iomem *)
61 (__IA64_UNCACHED_OFFSET | IA64_IPI_DEFAULT_BASE_ADDR));
62
63 static cpumask_t vector_allocation_domain(int cpu);
64
65 /*
66 * Legacy IRQ to IA-64 vector translation table.
67 */
68 __u8 isa_irq_to_vector_map[16] = {
69 /* 8259 IRQ translation, first 16 entries */
70 0x2f, 0x20, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29,
71 0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21
72 };
73 EXPORT_SYMBOL(isa_irq_to_vector_map);
74
75 DEFINE_SPINLOCK(vector_lock);
76
77 struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
78 [0 ... NR_IRQS - 1] = {
79 .vector = IRQ_VECTOR_UNASSIGNED,
80 .domain = CPU_MASK_NONE
81 }
82 };
83
84 DEFINE_PER_CPU(int[IA64_NUM_VECTORS], vector_irq) = {
85 [0 ... IA64_NUM_VECTORS - 1] = -1
86 };
87
88 static cpumask_t vector_table[IA64_NUM_VECTORS] = {
89 [0 ... IA64_NUM_VECTORS - 1] = CPU_MASK_NONE
90 };
91
92 static int irq_status[NR_IRQS] = {
93 [0 ... NR_IRQS -1] = IRQ_UNUSED
94 };
95
check_irq_used(int irq)96 int check_irq_used(int irq)
97 {
98 if (irq_status[irq] == IRQ_USED)
99 return 1;
100
101 return -1;
102 }
103
find_unassigned_irq(void)104 static inline int find_unassigned_irq(void)
105 {
106 int irq;
107
108 for (irq = IA64_FIRST_DEVICE_VECTOR; irq < NR_IRQS; irq++)
109 if (irq_status[irq] == IRQ_UNUSED)
110 return irq;
111 return -ENOSPC;
112 }
113
find_unassigned_vector(cpumask_t domain)114 static inline int find_unassigned_vector(cpumask_t domain)
115 {
116 cpumask_t mask;
117 int pos, vector;
118
119 cpus_and(mask, domain, cpu_online_map);
120 if (cpus_empty(mask))
121 return -EINVAL;
122
123 for (pos = 0; pos < IA64_NUM_DEVICE_VECTORS; pos++) {
124 vector = IA64_FIRST_DEVICE_VECTOR + pos;
125 cpus_and(mask, domain, vector_table[vector]);
126 if (!cpus_empty(mask))
127 continue;
128 return vector;
129 }
130 return -ENOSPC;
131 }
132
__bind_irq_vector(int irq,int vector,cpumask_t domain)133 static int __bind_irq_vector(int irq, int vector, cpumask_t domain)
134 {
135 cpumask_t mask;
136 int cpu;
137 struct irq_cfg *cfg = &irq_cfg[irq];
138
139 BUG_ON((unsigned)irq >= NR_IRQS);
140 BUG_ON((unsigned)vector >= IA64_NUM_VECTORS);
141
142 cpus_and(mask, domain, cpu_online_map);
143 if (cpus_empty(mask))
144 return -EINVAL;
145 if ((cfg->vector == vector) && cpus_equal(cfg->domain, domain))
146 return 0;
147 if (cfg->vector != IRQ_VECTOR_UNASSIGNED)
148 return -EBUSY;
149 for_each_cpu_mask(cpu, mask)
150 per_cpu(vector_irq, cpu)[vector] = irq;
151 cfg->vector = vector;
152 cfg->domain = domain;
153 irq_status[irq] = IRQ_USED;
154 cpus_or(vector_table[vector], vector_table[vector], domain);
155 return 0;
156 }
157
bind_irq_vector(int irq,int vector,cpumask_t domain)158 int bind_irq_vector(int irq, int vector, cpumask_t domain)
159 {
160 unsigned long flags;
161 int ret;
162
163 spin_lock_irqsave(&vector_lock, flags);
164 ret = __bind_irq_vector(irq, vector, domain);
165 spin_unlock_irqrestore(&vector_lock, flags);
166 return ret;
167 }
168
__clear_irq_vector(int irq)169 static void __clear_irq_vector(int irq)
170 {
171 int vector, cpu;
172 cpumask_t mask;
173 cpumask_t domain;
174 struct irq_cfg *cfg = &irq_cfg[irq];
175
176 BUG_ON((unsigned)irq >= NR_IRQS);
177 BUG_ON(cfg->vector == IRQ_VECTOR_UNASSIGNED);
178 vector = cfg->vector;
179 domain = cfg->domain;
180 cpus_and(mask, cfg->domain, cpu_online_map);
181 for_each_cpu_mask(cpu, mask)
182 per_cpu(vector_irq, cpu)[vector] = -1;
183 cfg->vector = IRQ_VECTOR_UNASSIGNED;
184 cfg->domain = CPU_MASK_NONE;
185 irq_status[irq] = IRQ_UNUSED;
186 cpus_andnot(vector_table[vector], vector_table[vector], domain);
187 }
188
clear_irq_vector(int irq)189 static void clear_irq_vector(int irq)
190 {
191 unsigned long flags;
192
193 spin_lock_irqsave(&vector_lock, flags);
194 __clear_irq_vector(irq);
195 spin_unlock_irqrestore(&vector_lock, flags);
196 }
197
198 int
ia64_native_assign_irq_vector(int irq)199 ia64_native_assign_irq_vector (int irq)
200 {
201 unsigned long flags;
202 int vector, cpu;
203 cpumask_t domain = CPU_MASK_NONE;
204
205 vector = -ENOSPC;
206
207 spin_lock_irqsave(&vector_lock, flags);
208 for_each_online_cpu(cpu) {
209 domain = vector_allocation_domain(cpu);
210 vector = find_unassigned_vector(domain);
211 if (vector >= 0)
212 break;
213 }
214 if (vector < 0)
215 goto out;
216 if (irq == AUTO_ASSIGN)
217 irq = vector;
218 BUG_ON(__bind_irq_vector(irq, vector, domain));
219 out:
220 spin_unlock_irqrestore(&vector_lock, flags);
221 return vector;
222 }
223
224 void
ia64_native_free_irq_vector(int vector)225 ia64_native_free_irq_vector (int vector)
226 {
227 if (vector < IA64_FIRST_DEVICE_VECTOR ||
228 vector > IA64_LAST_DEVICE_VECTOR)
229 return;
230 clear_irq_vector(vector);
231 }
232
233 int
reserve_irq_vector(int vector)234 reserve_irq_vector (int vector)
235 {
236 if (vector < IA64_FIRST_DEVICE_VECTOR ||
237 vector > IA64_LAST_DEVICE_VECTOR)
238 return -EINVAL;
239 return !!bind_irq_vector(vector, vector, CPU_MASK_ALL);
240 }
241
242 /*
243 * Initialize vector_irq on a new cpu. This function must be called
244 * with vector_lock held.
245 */
__setup_vector_irq(int cpu)246 void __setup_vector_irq(int cpu)
247 {
248 int irq, vector;
249
250 /* Clear vector_irq */
251 for (vector = 0; vector < IA64_NUM_VECTORS; ++vector)
252 per_cpu(vector_irq, cpu)[vector] = -1;
253 /* Mark the inuse vectors */
254 for (irq = 0; irq < NR_IRQS; ++irq) {
255 if (!cpu_isset(cpu, irq_cfg[irq].domain))
256 continue;
257 vector = irq_to_vector(irq);
258 per_cpu(vector_irq, cpu)[vector] = irq;
259 }
260 }
261
262 #if defined(CONFIG_SMP) && (defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_DIG))
263 #define IA64_IRQ_MOVE_VECTOR IA64_DEF_FIRST_DEVICE_VECTOR
264
265 static enum vector_domain_type {
266 VECTOR_DOMAIN_NONE,
267 VECTOR_DOMAIN_PERCPU
268 } vector_domain_type = VECTOR_DOMAIN_NONE;
269
vector_allocation_domain(int cpu)270 static cpumask_t vector_allocation_domain(int cpu)
271 {
272 if (vector_domain_type == VECTOR_DOMAIN_PERCPU)
273 return cpumask_of_cpu(cpu);
274 return CPU_MASK_ALL;
275 }
276
__irq_prepare_move(int irq,int cpu)277 static int __irq_prepare_move(int irq, int cpu)
278 {
279 struct irq_cfg *cfg = &irq_cfg[irq];
280 int vector;
281 cpumask_t domain;
282
283 if (cfg->move_in_progress || cfg->move_cleanup_count)
284 return -EBUSY;
285 if (cfg->vector == IRQ_VECTOR_UNASSIGNED || !cpu_online(cpu))
286 return -EINVAL;
287 if (cpu_isset(cpu, cfg->domain))
288 return 0;
289 domain = vector_allocation_domain(cpu);
290 vector = find_unassigned_vector(domain);
291 if (vector < 0)
292 return -ENOSPC;
293 cfg->move_in_progress = 1;
294 cfg->old_domain = cfg->domain;
295 cfg->vector = IRQ_VECTOR_UNASSIGNED;
296 cfg->domain = CPU_MASK_NONE;
297 BUG_ON(__bind_irq_vector(irq, vector, domain));
298 return 0;
299 }
300
irq_prepare_move(int irq,int cpu)301 int irq_prepare_move(int irq, int cpu)
302 {
303 unsigned long flags;
304 int ret;
305
306 spin_lock_irqsave(&vector_lock, flags);
307 ret = __irq_prepare_move(irq, cpu);
308 spin_unlock_irqrestore(&vector_lock, flags);
309 return ret;
310 }
311
irq_complete_move(unsigned irq)312 void irq_complete_move(unsigned irq)
313 {
314 struct irq_cfg *cfg = &irq_cfg[irq];
315 cpumask_t cleanup_mask;
316 int i;
317
318 if (likely(!cfg->move_in_progress))
319 return;
320
321 if (unlikely(cpu_isset(smp_processor_id(), cfg->old_domain)))
322 return;
323
324 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
325 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
326 for_each_cpu_mask(i, cleanup_mask)
327 platform_send_ipi(i, IA64_IRQ_MOVE_VECTOR, IA64_IPI_DM_INT, 0);
328 cfg->move_in_progress = 0;
329 }
330
smp_irq_move_cleanup_interrupt(int irq,void * dev_id)331 static irqreturn_t smp_irq_move_cleanup_interrupt(int irq, void *dev_id)
332 {
333 int me = smp_processor_id();
334 ia64_vector vector;
335 unsigned long flags;
336
337 for (vector = IA64_FIRST_DEVICE_VECTOR;
338 vector < IA64_LAST_DEVICE_VECTOR; vector++) {
339 int irq;
340 struct irq_desc *desc;
341 struct irq_cfg *cfg;
342 irq = __get_cpu_var(vector_irq)[vector];
343 if (irq < 0)
344 continue;
345
346 desc = irq_desc + irq;
347 cfg = irq_cfg + irq;
348 spin_lock(&desc->lock);
349 if (!cfg->move_cleanup_count)
350 goto unlock;
351
352 if (!cpu_isset(me, cfg->old_domain))
353 goto unlock;
354
355 spin_lock_irqsave(&vector_lock, flags);
356 __get_cpu_var(vector_irq)[vector] = -1;
357 cpu_clear(me, vector_table[vector]);
358 spin_unlock_irqrestore(&vector_lock, flags);
359 cfg->move_cleanup_count--;
360 unlock:
361 spin_unlock(&desc->lock);
362 }
363 return IRQ_HANDLED;
364 }
365
366 static struct irqaction irq_move_irqaction = {
367 .handler = smp_irq_move_cleanup_interrupt,
368 .flags = IRQF_DISABLED,
369 .name = "irq_move"
370 };
371
parse_vector_domain(char * arg)372 static int __init parse_vector_domain(char *arg)
373 {
374 if (!arg)
375 return -EINVAL;
376 if (!strcmp(arg, "percpu")) {
377 vector_domain_type = VECTOR_DOMAIN_PERCPU;
378 no_int_routing = 1;
379 }
380 return 0;
381 }
382 early_param("vector", parse_vector_domain);
383 #else
vector_allocation_domain(int cpu)384 static cpumask_t vector_allocation_domain(int cpu)
385 {
386 return CPU_MASK_ALL;
387 }
388 #endif
389
390
destroy_and_reserve_irq(unsigned int irq)391 void destroy_and_reserve_irq(unsigned int irq)
392 {
393 unsigned long flags;
394
395 dynamic_irq_cleanup(irq);
396
397 spin_lock_irqsave(&vector_lock, flags);
398 __clear_irq_vector(irq);
399 irq_status[irq] = IRQ_RSVD;
400 spin_unlock_irqrestore(&vector_lock, flags);
401 }
402
403 /*
404 * Dynamic irq allocate and deallocation for MSI
405 */
create_irq(void)406 int create_irq(void)
407 {
408 unsigned long flags;
409 int irq, vector, cpu;
410 cpumask_t domain = CPU_MASK_NONE;
411
412 irq = vector = -ENOSPC;
413 spin_lock_irqsave(&vector_lock, flags);
414 for_each_online_cpu(cpu) {
415 domain = vector_allocation_domain(cpu);
416 vector = find_unassigned_vector(domain);
417 if (vector >= 0)
418 break;
419 }
420 if (vector < 0)
421 goto out;
422 irq = find_unassigned_irq();
423 if (irq < 0)
424 goto out;
425 BUG_ON(__bind_irq_vector(irq, vector, domain));
426 out:
427 spin_unlock_irqrestore(&vector_lock, flags);
428 if (irq >= 0)
429 dynamic_irq_init(irq);
430 return irq;
431 }
432
destroy_irq(unsigned int irq)433 void destroy_irq(unsigned int irq)
434 {
435 dynamic_irq_cleanup(irq);
436 clear_irq_vector(irq);
437 }
438
439 #ifdef CONFIG_SMP
440 # define IS_RESCHEDULE(vec) (vec == IA64_IPI_RESCHEDULE)
441 # define IS_LOCAL_TLB_FLUSH(vec) (vec == IA64_IPI_LOCAL_TLB_FLUSH)
442 #else
443 # define IS_RESCHEDULE(vec) (0)
444 # define IS_LOCAL_TLB_FLUSH(vec) (0)
445 #endif
446 /*
447 * That's where the IVT branches when we get an external
448 * interrupt. This branches to the correct hardware IRQ handler via
449 * function ptr.
450 */
451 void
ia64_handle_irq(ia64_vector vector,struct pt_regs * regs)452 ia64_handle_irq (ia64_vector vector, struct pt_regs *regs)
453 {
454 struct pt_regs *old_regs = set_irq_regs(regs);
455 unsigned long saved_tpr;
456
457 #if IRQ_DEBUG
458 {
459 unsigned long bsp, sp;
460
461 /*
462 * Note: if the interrupt happened while executing in
463 * the context switch routine (ia64_switch_to), we may
464 * get a spurious stack overflow here. This is
465 * because the register and the memory stack are not
466 * switched atomically.
467 */
468 bsp = ia64_getreg(_IA64_REG_AR_BSP);
469 sp = ia64_getreg(_IA64_REG_SP);
470
471 if ((sp - bsp) < 1024) {
472 static unsigned char count;
473 static long last_time;
474
475 if (time_after(jiffies, last_time + 5 * HZ))
476 count = 0;
477 if (++count < 5) {
478 last_time = jiffies;
479 printk("ia64_handle_irq: DANGER: less than "
480 "1KB of free stack space!!\n"
481 "(bsp=0x%lx, sp=%lx)\n", bsp, sp);
482 }
483 }
484 }
485 #endif /* IRQ_DEBUG */
486
487 /*
488 * Always set TPR to limit maximum interrupt nesting depth to
489 * 16 (without this, it would be ~240, which could easily lead
490 * to kernel stack overflows).
491 */
492 irq_enter();
493 saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
494 ia64_srlz_d();
495 while (vector != IA64_SPURIOUS_INT_VECTOR) {
496 if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) {
497 smp_local_flush_tlb();
498 kstat_this_cpu.irqs[vector]++;
499 } else if (unlikely(IS_RESCHEDULE(vector)))
500 kstat_this_cpu.irqs[vector]++;
501 else {
502 int irq = local_vector_to_irq(vector);
503
504 ia64_setreg(_IA64_REG_CR_TPR, vector);
505 ia64_srlz_d();
506
507 if (unlikely(irq < 0)) {
508 printk(KERN_ERR "%s: Unexpected interrupt "
509 "vector %d on CPU %d is not mapped "
510 "to any IRQ!\n", __func__, vector,
511 smp_processor_id());
512 } else
513 generic_handle_irq(irq);
514
515 /*
516 * Disable interrupts and send EOI:
517 */
518 local_irq_disable();
519 ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
520 }
521 ia64_eoi();
522 vector = ia64_get_ivr();
523 }
524 /*
525 * This must be done *after* the ia64_eoi(). For example, the keyboard softirq
526 * handler needs to be able to wait for further keyboard interrupts, which can't
527 * come through until ia64_eoi() has been done.
528 */
529 irq_exit();
530 set_irq_regs(old_regs);
531 }
532
533 #ifdef CONFIG_HOTPLUG_CPU
534 /*
535 * This function emulates a interrupt processing when a cpu is about to be
536 * brought down.
537 */
ia64_process_pending_intr(void)538 void ia64_process_pending_intr(void)
539 {
540 ia64_vector vector;
541 unsigned long saved_tpr;
542 extern unsigned int vectors_in_migration[NR_IRQS];
543
544 vector = ia64_get_ivr();
545
546 irq_enter();
547 saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
548 ia64_srlz_d();
549
550 /*
551 * Perform normal interrupt style processing
552 */
553 while (vector != IA64_SPURIOUS_INT_VECTOR) {
554 if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) {
555 smp_local_flush_tlb();
556 kstat_this_cpu.irqs[vector]++;
557 } else if (unlikely(IS_RESCHEDULE(vector)))
558 kstat_this_cpu.irqs[vector]++;
559 else {
560 struct pt_regs *old_regs = set_irq_regs(NULL);
561 int irq = local_vector_to_irq(vector);
562
563 ia64_setreg(_IA64_REG_CR_TPR, vector);
564 ia64_srlz_d();
565
566 /*
567 * Now try calling normal ia64_handle_irq as it would have got called
568 * from a real intr handler. Try passing null for pt_regs, hopefully
569 * it will work. I hope it works!.
570 * Probably could shared code.
571 */
572 if (unlikely(irq < 0)) {
573 printk(KERN_ERR "%s: Unexpected interrupt "
574 "vector %d on CPU %d not being mapped "
575 "to any IRQ!!\n", __func__, vector,
576 smp_processor_id());
577 } else {
578 vectors_in_migration[irq]=0;
579 generic_handle_irq(irq);
580 }
581 set_irq_regs(old_regs);
582
583 /*
584 * Disable interrupts and send EOI
585 */
586 local_irq_disable();
587 ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
588 }
589 ia64_eoi();
590 vector = ia64_get_ivr();
591 }
592 irq_exit();
593 }
594 #endif
595
596
597 #ifdef CONFIG_SMP
598
dummy_handler(int irq,void * dev_id)599 static irqreturn_t dummy_handler (int irq, void *dev_id)
600 {
601 BUG();
602 }
603
604 static struct irqaction ipi_irqaction = {
605 .handler = handle_IPI,
606 .flags = IRQF_DISABLED,
607 .name = "IPI"
608 };
609
610 static struct irqaction resched_irqaction = {
611 .handler = dummy_handler,
612 .flags = IRQF_DISABLED,
613 .name = "resched"
614 };
615
616 static struct irqaction tlb_irqaction = {
617 .handler = dummy_handler,
618 .flags = IRQF_DISABLED,
619 .name = "tlb_flush"
620 };
621
622 #endif
623
624 void
ia64_native_register_percpu_irq(ia64_vector vec,struct irqaction * action)625 ia64_native_register_percpu_irq (ia64_vector vec, struct irqaction *action)
626 {
627 irq_desc_t *desc;
628 unsigned int irq;
629
630 irq = vec;
631 BUG_ON(bind_irq_vector(irq, vec, CPU_MASK_ALL));
632 desc = irq_desc + irq;
633 desc->status |= IRQ_PER_CPU;
634 desc->chip = &irq_type_ia64_lsapic;
635 if (action)
636 setup_irq(irq, action);
637 }
638
639 void __init
ia64_native_register_ipi(void)640 ia64_native_register_ipi(void)
641 {
642 #ifdef CONFIG_SMP
643 register_percpu_irq(IA64_IPI_VECTOR, &ipi_irqaction);
644 register_percpu_irq(IA64_IPI_RESCHEDULE, &resched_irqaction);
645 register_percpu_irq(IA64_IPI_LOCAL_TLB_FLUSH, &tlb_irqaction);
646 #endif
647 }
648
649 void __init
init_IRQ(void)650 init_IRQ (void)
651 {
652 ia64_register_ipi();
653 register_percpu_irq(IA64_SPURIOUS_INT_VECTOR, NULL);
654 #ifdef CONFIG_SMP
655 #if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_DIG)
656 if (vector_domain_type != VECTOR_DOMAIN_NONE) {
657 BUG_ON(IA64_FIRST_DEVICE_VECTOR != IA64_IRQ_MOVE_VECTOR);
658 IA64_FIRST_DEVICE_VECTOR++;
659 register_percpu_irq(IA64_IRQ_MOVE_VECTOR, &irq_move_irqaction);
660 }
661 #endif
662 #endif
663 #ifdef CONFIG_PERFMON
664 pfm_init_percpu();
665 #endif
666 platform_irq_init();
667 }
668
669 void
ia64_send_ipi(int cpu,int vector,int delivery_mode,int redirect)670 ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect)
671 {
672 void __iomem *ipi_addr;
673 unsigned long ipi_data;
674 unsigned long phys_cpu_id;
675
676 phys_cpu_id = cpu_physical_id(cpu);
677
678 /*
679 * cpu number is in 8bit ID and 8bit EID
680 */
681
682 ipi_data = (delivery_mode << 8) | (vector & 0xff);
683 ipi_addr = ipi_base_addr + ((phys_cpu_id << 4) | ((redirect & 1) << 3));
684
685 writeq(ipi_data, ipi_addr);
686 }
687