1 /*
2 * Driver for the Conexant CX23885 PCIe bridge
3 *
4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22 #include <linux/init.h>
23 #include <linux/list.h>
24 #include <linux/module.h>
25 #include <linux/moduleparam.h>
26 #include <linux/kmod.h>
27 #include <linux/kernel.h>
28 #include <linux/slab.h>
29 #include <linux/interrupt.h>
30 #include <linux/delay.h>
31 #include <asm/div64.h>
32
33 #include "cx23885.h"
34
35 MODULE_DESCRIPTION("Driver for cx23885 based TV cards");
36 MODULE_AUTHOR("Steven Toth <stoth@linuxtv.org>");
37 MODULE_LICENSE("GPL");
38
39 static unsigned int debug;
40 module_param(debug, int, 0644);
41 MODULE_PARM_DESC(debug, "enable debug messages");
42
43 static unsigned int card[] = {[0 ... (CX23885_MAXBOARDS - 1)] = UNSET };
44 module_param_array(card, int, NULL, 0444);
45 MODULE_PARM_DESC(card, "card type");
46
47 #define dprintk(level, fmt, arg...)\
48 do { if (debug >= level)\
49 printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
50 } while (0)
51
52 static unsigned int cx23885_devcount;
53
54 static DEFINE_MUTEX(devlist);
55 LIST_HEAD(cx23885_devlist);
56
57 #define NO_SYNC_LINE (-1U)
58
59 /* FIXME, these allocations will change when
60 * analog arrives. The be reviewed.
61 * CX23887 Assumptions
62 * 1 line = 16 bytes of CDT
63 * cmds size = 80
64 * cdt size = 16 * linesize
65 * iqsize = 64
66 * maxlines = 6
67 *
68 * Address Space:
69 * 0x00000000 0x00008fff FIFO clusters
70 * 0x00010000 0x000104af Channel Management Data Structures
71 * 0x000104b0 0x000104ff Free
72 * 0x00010500 0x000108bf 15 channels * iqsize
73 * 0x000108c0 0x000108ff Free
74 * 0x00010900 0x00010e9f IQ's + Cluster Descriptor Tables
75 * 15 channels * (iqsize + (maxlines * linesize))
76 * 0x00010ea0 0x00010xxx Free
77 */
78
79 static struct sram_channel cx23885_sram_channels[] = {
80 [SRAM_CH01] = {
81 .name = "VID A",
82 .cmds_start = 0x10000,
83 .ctrl_start = 0x10380,
84 .cdt = 0x104c0,
85 .fifo_start = 0x40,
86 .fifo_size = 0x2800,
87 .ptr1_reg = DMA1_PTR1,
88 .ptr2_reg = DMA1_PTR2,
89 .cnt1_reg = DMA1_CNT1,
90 .cnt2_reg = DMA1_CNT2,
91 },
92 [SRAM_CH02] = {
93 .name = "ch2",
94 .cmds_start = 0x0,
95 .ctrl_start = 0x0,
96 .cdt = 0x0,
97 .fifo_start = 0x0,
98 .fifo_size = 0x0,
99 .ptr1_reg = DMA2_PTR1,
100 .ptr2_reg = DMA2_PTR2,
101 .cnt1_reg = DMA2_CNT1,
102 .cnt2_reg = DMA2_CNT2,
103 },
104 [SRAM_CH03] = {
105 .name = "TS1 B",
106 .cmds_start = 0x100A0,
107 .ctrl_start = 0x10400,
108 .cdt = 0x10580,
109 .fifo_start = 0x5000,
110 .fifo_size = 0x1000,
111 .ptr1_reg = DMA3_PTR1,
112 .ptr2_reg = DMA3_PTR2,
113 .cnt1_reg = DMA3_CNT1,
114 .cnt2_reg = DMA3_CNT2,
115 },
116 [SRAM_CH04] = {
117 .name = "ch4",
118 .cmds_start = 0x0,
119 .ctrl_start = 0x0,
120 .cdt = 0x0,
121 .fifo_start = 0x0,
122 .fifo_size = 0x0,
123 .ptr1_reg = DMA4_PTR1,
124 .ptr2_reg = DMA4_PTR2,
125 .cnt1_reg = DMA4_CNT1,
126 .cnt2_reg = DMA4_CNT2,
127 },
128 [SRAM_CH05] = {
129 .name = "ch5",
130 .cmds_start = 0x0,
131 .ctrl_start = 0x0,
132 .cdt = 0x0,
133 .fifo_start = 0x0,
134 .fifo_size = 0x0,
135 .ptr1_reg = DMA5_PTR1,
136 .ptr2_reg = DMA5_PTR2,
137 .cnt1_reg = DMA5_CNT1,
138 .cnt2_reg = DMA5_CNT2,
139 },
140 [SRAM_CH06] = {
141 .name = "TS2 C",
142 .cmds_start = 0x10140,
143 .ctrl_start = 0x10440,
144 .cdt = 0x105e0,
145 .fifo_start = 0x6000,
146 .fifo_size = 0x1000,
147 .ptr1_reg = DMA5_PTR1,
148 .ptr2_reg = DMA5_PTR2,
149 .cnt1_reg = DMA5_CNT1,
150 .cnt2_reg = DMA5_CNT2,
151 },
152 [SRAM_CH07] = {
153 .name = "ch7",
154 .cmds_start = 0x0,
155 .ctrl_start = 0x0,
156 .cdt = 0x0,
157 .fifo_start = 0x0,
158 .fifo_size = 0x0,
159 .ptr1_reg = DMA6_PTR1,
160 .ptr2_reg = DMA6_PTR2,
161 .cnt1_reg = DMA6_CNT1,
162 .cnt2_reg = DMA6_CNT2,
163 },
164 [SRAM_CH08] = {
165 .name = "ch8",
166 .cmds_start = 0x0,
167 .ctrl_start = 0x0,
168 .cdt = 0x0,
169 .fifo_start = 0x0,
170 .fifo_size = 0x0,
171 .ptr1_reg = DMA7_PTR1,
172 .ptr2_reg = DMA7_PTR2,
173 .cnt1_reg = DMA7_CNT1,
174 .cnt2_reg = DMA7_CNT2,
175 },
176 [SRAM_CH09] = {
177 .name = "ch9",
178 .cmds_start = 0x0,
179 .ctrl_start = 0x0,
180 .cdt = 0x0,
181 .fifo_start = 0x0,
182 .fifo_size = 0x0,
183 .ptr1_reg = DMA8_PTR1,
184 .ptr2_reg = DMA8_PTR2,
185 .cnt1_reg = DMA8_CNT1,
186 .cnt2_reg = DMA8_CNT2,
187 },
188 };
189
190 static struct sram_channel cx23887_sram_channels[] = {
191 [SRAM_CH01] = {
192 .name = "VID A",
193 .cmds_start = 0x10000,
194 .ctrl_start = 0x105b0,
195 .cdt = 0x107b0,
196 .fifo_start = 0x40,
197 .fifo_size = 0x2800,
198 .ptr1_reg = DMA1_PTR1,
199 .ptr2_reg = DMA1_PTR2,
200 .cnt1_reg = DMA1_CNT1,
201 .cnt2_reg = DMA1_CNT2,
202 },
203 [SRAM_CH02] = {
204 .name = "ch2",
205 .cmds_start = 0x0,
206 .ctrl_start = 0x0,
207 .cdt = 0x0,
208 .fifo_start = 0x0,
209 .fifo_size = 0x0,
210 .ptr1_reg = DMA2_PTR1,
211 .ptr2_reg = DMA2_PTR2,
212 .cnt1_reg = DMA2_CNT1,
213 .cnt2_reg = DMA2_CNT2,
214 },
215 [SRAM_CH03] = {
216 .name = "TS1 B",
217 .cmds_start = 0x100A0,
218 .ctrl_start = 0x10630,
219 .cdt = 0x10870,
220 .fifo_start = 0x5000,
221 .fifo_size = 0x1000,
222 .ptr1_reg = DMA3_PTR1,
223 .ptr2_reg = DMA3_PTR2,
224 .cnt1_reg = DMA3_CNT1,
225 .cnt2_reg = DMA3_CNT2,
226 },
227 [SRAM_CH04] = {
228 .name = "ch4",
229 .cmds_start = 0x0,
230 .ctrl_start = 0x0,
231 .cdt = 0x0,
232 .fifo_start = 0x0,
233 .fifo_size = 0x0,
234 .ptr1_reg = DMA4_PTR1,
235 .ptr2_reg = DMA4_PTR2,
236 .cnt1_reg = DMA4_CNT1,
237 .cnt2_reg = DMA4_CNT2,
238 },
239 [SRAM_CH05] = {
240 .name = "ch5",
241 .cmds_start = 0x0,
242 .ctrl_start = 0x0,
243 .cdt = 0x0,
244 .fifo_start = 0x0,
245 .fifo_size = 0x0,
246 .ptr1_reg = DMA5_PTR1,
247 .ptr2_reg = DMA5_PTR2,
248 .cnt1_reg = DMA5_CNT1,
249 .cnt2_reg = DMA5_CNT2,
250 },
251 [SRAM_CH06] = {
252 .name = "TS2 C",
253 .cmds_start = 0x10140,
254 .ctrl_start = 0x10670,
255 .cdt = 0x108d0,
256 .fifo_start = 0x6000,
257 .fifo_size = 0x1000,
258 .ptr1_reg = DMA5_PTR1,
259 .ptr2_reg = DMA5_PTR2,
260 .cnt1_reg = DMA5_CNT1,
261 .cnt2_reg = DMA5_CNT2,
262 },
263 [SRAM_CH07] = {
264 .name = "ch7",
265 .cmds_start = 0x0,
266 .ctrl_start = 0x0,
267 .cdt = 0x0,
268 .fifo_start = 0x0,
269 .fifo_size = 0x0,
270 .ptr1_reg = DMA6_PTR1,
271 .ptr2_reg = DMA6_PTR2,
272 .cnt1_reg = DMA6_CNT1,
273 .cnt2_reg = DMA6_CNT2,
274 },
275 [SRAM_CH08] = {
276 .name = "ch8",
277 .cmds_start = 0x0,
278 .ctrl_start = 0x0,
279 .cdt = 0x0,
280 .fifo_start = 0x0,
281 .fifo_size = 0x0,
282 .ptr1_reg = DMA7_PTR1,
283 .ptr2_reg = DMA7_PTR2,
284 .cnt1_reg = DMA7_CNT1,
285 .cnt2_reg = DMA7_CNT2,
286 },
287 [SRAM_CH09] = {
288 .name = "ch9",
289 .cmds_start = 0x0,
290 .ctrl_start = 0x0,
291 .cdt = 0x0,
292 .fifo_start = 0x0,
293 .fifo_size = 0x0,
294 .ptr1_reg = DMA8_PTR1,
295 .ptr2_reg = DMA8_PTR2,
296 .cnt1_reg = DMA8_CNT1,
297 .cnt2_reg = DMA8_CNT2,
298 },
299 };
300
cx23885_risc_decode(u32 risc)301 static int cx23885_risc_decode(u32 risc)
302 {
303 static char *instr[16] = {
304 [RISC_SYNC >> 28] = "sync",
305 [RISC_WRITE >> 28] = "write",
306 [RISC_WRITEC >> 28] = "writec",
307 [RISC_READ >> 28] = "read",
308 [RISC_READC >> 28] = "readc",
309 [RISC_JUMP >> 28] = "jump",
310 [RISC_SKIP >> 28] = "skip",
311 [RISC_WRITERM >> 28] = "writerm",
312 [RISC_WRITECM >> 28] = "writecm",
313 [RISC_WRITECR >> 28] = "writecr",
314 };
315 static int incr[16] = {
316 [RISC_WRITE >> 28] = 3,
317 [RISC_JUMP >> 28] = 3,
318 [RISC_SKIP >> 28] = 1,
319 [RISC_SYNC >> 28] = 1,
320 [RISC_WRITERM >> 28] = 3,
321 [RISC_WRITECM >> 28] = 3,
322 [RISC_WRITECR >> 28] = 4,
323 };
324 static char *bits[] = {
325 "12", "13", "14", "resync",
326 "cnt0", "cnt1", "18", "19",
327 "20", "21", "22", "23",
328 "irq1", "irq2", "eol", "sol",
329 };
330 int i;
331
332 printk("0x%08x [ %s", risc,
333 instr[risc >> 28] ? instr[risc >> 28] : "INVALID");
334 for (i = ARRAY_SIZE(bits) - 1; i >= 0; i--)
335 if (risc & (1 << (i + 12)))
336 printk(" %s", bits[i]);
337 printk(" count=%d ]\n", risc & 0xfff);
338 return incr[risc >> 28] ? incr[risc >> 28] : 1;
339 }
340
cx23885_wakeup(struct cx23885_tsport * port,struct cx23885_dmaqueue * q,u32 count)341 void cx23885_wakeup(struct cx23885_tsport *port,
342 struct cx23885_dmaqueue *q, u32 count)
343 {
344 struct cx23885_dev *dev = port->dev;
345 struct cx23885_buffer *buf;
346 int bc;
347
348 for (bc = 0;; bc++) {
349 if (list_empty(&q->active))
350 break;
351 buf = list_entry(q->active.next,
352 struct cx23885_buffer, vb.queue);
353
354 /* count comes from the hw and is is 16bit wide --
355 * this trick handles wrap-arounds correctly for
356 * up to 32767 buffers in flight... */
357 if ((s16) (count - buf->count) < 0)
358 break;
359
360 do_gettimeofday(&buf->vb.ts);
361 dprintk(2, "[%p/%d] wakeup reg=%d buf=%d\n", buf, buf->vb.i,
362 count, buf->count);
363 buf->vb.state = VIDEOBUF_DONE;
364 list_del(&buf->vb.queue);
365 wake_up(&buf->vb.done);
366 }
367 if (list_empty(&q->active))
368 del_timer(&q->timeout);
369 else
370 mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
371 if (bc != 1)
372 printk(KERN_WARNING "%s: %d buffers handled (should be 1)\n",
373 __func__, bc);
374 }
375
cx23885_sram_channel_setup(struct cx23885_dev * dev,struct sram_channel * ch,unsigned int bpl,u32 risc)376 int cx23885_sram_channel_setup(struct cx23885_dev *dev,
377 struct sram_channel *ch,
378 unsigned int bpl, u32 risc)
379 {
380 unsigned int i, lines;
381 u32 cdt;
382
383 if (ch->cmds_start == 0) {
384 dprintk(1, "%s() Erasing channel [%s]\n", __func__,
385 ch->name);
386 cx_write(ch->ptr1_reg, 0);
387 cx_write(ch->ptr2_reg, 0);
388 cx_write(ch->cnt2_reg, 0);
389 cx_write(ch->cnt1_reg, 0);
390 return 0;
391 } else {
392 dprintk(1, "%s() Configuring channel [%s]\n", __func__,
393 ch->name);
394 }
395
396 bpl = (bpl + 7) & ~7; /* alignment */
397 cdt = ch->cdt;
398 lines = ch->fifo_size / bpl;
399 if (lines > 6)
400 lines = 6;
401 BUG_ON(lines < 2);
402
403 cx_write(8 + 0, RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
404 cx_write(8 + 4, 8);
405 cx_write(8 + 8, 0);
406
407 /* write CDT */
408 for (i = 0; i < lines; i++) {
409 dprintk(2, "%s() 0x%08x <- 0x%08x\n", __func__, cdt + 16*i,
410 ch->fifo_start + bpl*i);
411 cx_write(cdt + 16*i, ch->fifo_start + bpl*i);
412 cx_write(cdt + 16*i + 4, 0);
413 cx_write(cdt + 16*i + 8, 0);
414 cx_write(cdt + 16*i + 12, 0);
415 }
416
417 /* write CMDS */
418 if (ch->jumponly)
419 cx_write(ch->cmds_start + 0, 8);
420 else
421 cx_write(ch->cmds_start + 0, risc);
422 cx_write(ch->cmds_start + 4, 0); /* 64 bits 63-32 */
423 cx_write(ch->cmds_start + 8, cdt);
424 cx_write(ch->cmds_start + 12, (lines*16) >> 3);
425 cx_write(ch->cmds_start + 16, ch->ctrl_start);
426 if (ch->jumponly)
427 cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2));
428 else
429 cx_write(ch->cmds_start + 20, 64 >> 2);
430 for (i = 24; i < 80; i += 4)
431 cx_write(ch->cmds_start + i, 0);
432
433 /* fill registers */
434 cx_write(ch->ptr1_reg, ch->fifo_start);
435 cx_write(ch->ptr2_reg, cdt);
436 cx_write(ch->cnt2_reg, (lines*16) >> 3);
437 cx_write(ch->cnt1_reg, (bpl >> 3) - 1);
438
439 dprintk(2, "[bridge %d] sram setup %s: bpl=%d lines=%d\n",
440 dev->bridge,
441 ch->name,
442 bpl,
443 lines);
444
445 return 0;
446 }
447
cx23885_sram_channel_dump(struct cx23885_dev * dev,struct sram_channel * ch)448 void cx23885_sram_channel_dump(struct cx23885_dev *dev,
449 struct sram_channel *ch)
450 {
451 static char *name[] = {
452 "init risc lo",
453 "init risc hi",
454 "cdt base",
455 "cdt size",
456 "iq base",
457 "iq size",
458 "risc pc lo",
459 "risc pc hi",
460 "iq wr ptr",
461 "iq rd ptr",
462 "cdt current",
463 "pci target lo",
464 "pci target hi",
465 "line / byte",
466 };
467 u32 risc;
468 unsigned int i, j, n;
469
470 printk(KERN_WARNING "%s: %s - dma channel status dump\n",
471 dev->name, ch->name);
472 for (i = 0; i < ARRAY_SIZE(name); i++)
473 printk(KERN_WARNING "%s: cmds: %-15s: 0x%08x\n",
474 dev->name, name[i],
475 cx_read(ch->cmds_start + 4*i));
476
477 for (i = 0; i < 4; i++) {
478 risc = cx_read(ch->cmds_start + 4 * (i + 14));
479 printk(KERN_WARNING "%s: risc%d: ", dev->name, i);
480 cx23885_risc_decode(risc);
481 }
482 for (i = 0; i < (64 >> 2); i += n) {
483 risc = cx_read(ch->ctrl_start + 4 * i);
484 /* No consideration for bits 63-32 */
485
486 printk(KERN_WARNING "%s: (0x%08x) iq %x: ", dev->name,
487 ch->ctrl_start + 4 * i, i);
488 n = cx23885_risc_decode(risc);
489 for (j = 1; j < n; j++) {
490 risc = cx_read(ch->ctrl_start + 4 * (i + j));
491 printk(KERN_WARNING "%s: iq %x: 0x%08x [ arg #%d ]\n",
492 dev->name, i+j, risc, j);
493 }
494 }
495
496 printk(KERN_WARNING "%s: fifo: 0x%08x -> 0x%x\n",
497 dev->name, ch->fifo_start, ch->fifo_start+ch->fifo_size);
498 printk(KERN_WARNING "%s: ctrl: 0x%08x -> 0x%x\n",
499 dev->name, ch->ctrl_start, ch->ctrl_start + 6*16);
500 printk(KERN_WARNING "%s: ptr1_reg: 0x%08x\n",
501 dev->name, cx_read(ch->ptr1_reg));
502 printk(KERN_WARNING "%s: ptr2_reg: 0x%08x\n",
503 dev->name, cx_read(ch->ptr2_reg));
504 printk(KERN_WARNING "%s: cnt1_reg: 0x%08x\n",
505 dev->name, cx_read(ch->cnt1_reg));
506 printk(KERN_WARNING "%s: cnt2_reg: 0x%08x\n",
507 dev->name, cx_read(ch->cnt2_reg));
508 }
509
cx23885_risc_disasm(struct cx23885_tsport * port,struct btcx_riscmem * risc)510 static void cx23885_risc_disasm(struct cx23885_tsport *port,
511 struct btcx_riscmem *risc)
512 {
513 struct cx23885_dev *dev = port->dev;
514 unsigned int i, j, n;
515
516 printk(KERN_INFO "%s: risc disasm: %p [dma=0x%08lx]\n",
517 dev->name, risc->cpu, (unsigned long)risc->dma);
518 for (i = 0; i < (risc->size >> 2); i += n) {
519 printk(KERN_INFO "%s: %04d: ", dev->name, i);
520 n = cx23885_risc_decode(le32_to_cpu(risc->cpu[i]));
521 for (j = 1; j < n; j++)
522 printk(KERN_INFO "%s: %04d: 0x%08x [ arg #%d ]\n",
523 dev->name, i + j, risc->cpu[i + j], j);
524 if (risc->cpu[i] == cpu_to_le32(RISC_JUMP))
525 break;
526 }
527 }
528
cx23885_shutdown(struct cx23885_dev * dev)529 static void cx23885_shutdown(struct cx23885_dev *dev)
530 {
531 /* disable RISC controller */
532 cx_write(DEV_CNTRL2, 0);
533
534 /* Disable all IR activity */
535 cx_write(IR_CNTRL_REG, 0);
536
537 /* Disable Video A/B activity */
538 cx_write(VID_A_DMA_CTL, 0);
539 cx_write(VID_B_DMA_CTL, 0);
540 cx_write(VID_C_DMA_CTL, 0);
541
542 /* Disable Audio activity */
543 cx_write(AUD_INT_DMA_CTL, 0);
544 cx_write(AUD_EXT_DMA_CTL, 0);
545
546 /* Disable Serial port */
547 cx_write(UART_CTL, 0);
548
549 /* Disable Interrupts */
550 cx_write(PCI_INT_MSK, 0);
551 cx_write(VID_A_INT_MSK, 0);
552 cx_write(VID_B_INT_MSK, 0);
553 cx_write(VID_C_INT_MSK, 0);
554 cx_write(AUDIO_INT_INT_MSK, 0);
555 cx_write(AUDIO_EXT_INT_MSK, 0);
556
557 }
558
cx23885_reset(struct cx23885_dev * dev)559 static void cx23885_reset(struct cx23885_dev *dev)
560 {
561 dprintk(1, "%s()\n", __func__);
562
563 cx23885_shutdown(dev);
564
565 cx_write(PCI_INT_STAT, 0xffffffff);
566 cx_write(VID_A_INT_STAT, 0xffffffff);
567 cx_write(VID_B_INT_STAT, 0xffffffff);
568 cx_write(VID_C_INT_STAT, 0xffffffff);
569 cx_write(AUDIO_INT_INT_STAT, 0xffffffff);
570 cx_write(AUDIO_EXT_INT_STAT, 0xffffffff);
571 cx_write(CLK_DELAY, cx_read(CLK_DELAY) & 0x80000000);
572 cx_write(PAD_CTRL, 0x00500300);
573
574 mdelay(100);
575
576 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH01],
577 720*4, 0);
578 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH02], 128, 0);
579 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH03],
580 188*4, 0);
581 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH04], 128, 0);
582 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH05], 128, 0);
583 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH06],
584 188*4, 0);
585 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH07], 128, 0);
586 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH08], 128, 0);
587 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH09], 128, 0);
588
589 cx23885_gpio_setup(dev);
590 }
591
592
cx23885_pci_quirks(struct cx23885_dev * dev)593 static int cx23885_pci_quirks(struct cx23885_dev *dev)
594 {
595 dprintk(1, "%s()\n", __func__);
596
597 /* The cx23885 bridge has a weird bug which causes NMI to be asserted
598 * when DMA begins if RDR_TLCTL0 bit4 is not cleared. It does not
599 * occur on the cx23887 bridge.
600 */
601 if (dev->bridge == CX23885_BRIDGE_885)
602 cx_clear(RDR_TLCTL0, 1 << 4);
603
604 return 0;
605 }
606
get_resources(struct cx23885_dev * dev)607 static int get_resources(struct cx23885_dev *dev)
608 {
609 if (request_mem_region(pci_resource_start(dev->pci, 0),
610 pci_resource_len(dev->pci, 0),
611 dev->name))
612 return 0;
613
614 printk(KERN_ERR "%s: can't get MMIO memory @ 0x%llx\n",
615 dev->name, (unsigned long long)pci_resource_start(dev->pci, 0));
616
617 return -EBUSY;
618 }
619
620 static void cx23885_timeout(unsigned long data);
621 int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
622 u32 reg, u32 mask, u32 value);
623
cx23885_init_tsport(struct cx23885_dev * dev,struct cx23885_tsport * port,int portno)624 static int cx23885_init_tsport(struct cx23885_dev *dev,
625 struct cx23885_tsport *port, int portno)
626 {
627 dprintk(1, "%s(portno=%d)\n", __func__, portno);
628
629 /* Transport bus init dma queue - Common settings */
630 port->dma_ctl_val = 0x11; /* Enable RISC controller and Fifo */
631 port->ts_int_msk_val = 0x1111; /* TS port bits for RISC */
632 port->vld_misc_val = 0x0;
633 port->hw_sop_ctrl_val = (0x47 << 16 | 188 << 4);
634
635 spin_lock_init(&port->slock);
636 port->dev = dev;
637 port->nr = portno;
638
639 INIT_LIST_HEAD(&port->mpegq.active);
640 INIT_LIST_HEAD(&port->mpegq.queued);
641 port->mpegq.timeout.function = cx23885_timeout;
642 port->mpegq.timeout.data = (unsigned long)port;
643 init_timer(&port->mpegq.timeout);
644
645 mutex_init(&port->frontends.lock);
646 INIT_LIST_HEAD(&port->frontends.felist);
647 port->frontends.active_fe_id = 0;
648
649 /* This should be hardcoded allow a single frontend
650 * attachment to this tsport, keeping the -dvb.c
651 * code clean and safe.
652 */
653 if (!port->num_frontends)
654 port->num_frontends = 1;
655
656 switch (portno) {
657 case 1:
658 port->reg_gpcnt = VID_B_GPCNT;
659 port->reg_gpcnt_ctl = VID_B_GPCNT_CTL;
660 port->reg_dma_ctl = VID_B_DMA_CTL;
661 port->reg_lngth = VID_B_LNGTH;
662 port->reg_hw_sop_ctrl = VID_B_HW_SOP_CTL;
663 port->reg_gen_ctrl = VID_B_GEN_CTL;
664 port->reg_bd_pkt_status = VID_B_BD_PKT_STATUS;
665 port->reg_sop_status = VID_B_SOP_STATUS;
666 port->reg_fifo_ovfl_stat = VID_B_FIFO_OVFL_STAT;
667 port->reg_vld_misc = VID_B_VLD_MISC;
668 port->reg_ts_clk_en = VID_B_TS_CLK_EN;
669 port->reg_src_sel = VID_B_SRC_SEL;
670 port->reg_ts_int_msk = VID_B_INT_MSK;
671 port->reg_ts_int_stat = VID_B_INT_STAT;
672 port->sram_chno = SRAM_CH03; /* VID_B */
673 port->pci_irqmask = 0x02; /* VID_B bit1 */
674 break;
675 case 2:
676 port->reg_gpcnt = VID_C_GPCNT;
677 port->reg_gpcnt_ctl = VID_C_GPCNT_CTL;
678 port->reg_dma_ctl = VID_C_DMA_CTL;
679 port->reg_lngth = VID_C_LNGTH;
680 port->reg_hw_sop_ctrl = VID_C_HW_SOP_CTL;
681 port->reg_gen_ctrl = VID_C_GEN_CTL;
682 port->reg_bd_pkt_status = VID_C_BD_PKT_STATUS;
683 port->reg_sop_status = VID_C_SOP_STATUS;
684 port->reg_fifo_ovfl_stat = VID_C_FIFO_OVFL_STAT;
685 port->reg_vld_misc = VID_C_VLD_MISC;
686 port->reg_ts_clk_en = VID_C_TS_CLK_EN;
687 port->reg_src_sel = 0;
688 port->reg_ts_int_msk = VID_C_INT_MSK;
689 port->reg_ts_int_stat = VID_C_INT_STAT;
690 port->sram_chno = SRAM_CH06; /* VID_C */
691 port->pci_irqmask = 0x04; /* VID_C bit2 */
692 break;
693 default:
694 BUG();
695 }
696
697 cx23885_risc_stopper(dev->pci, &port->mpegq.stopper,
698 port->reg_dma_ctl, port->dma_ctl_val, 0x00);
699
700 return 0;
701 }
702
cx23885_dev_checkrevision(struct cx23885_dev * dev)703 static void cx23885_dev_checkrevision(struct cx23885_dev *dev)
704 {
705 switch (cx_read(RDR_CFG2) & 0xff) {
706 case 0x00:
707 /* cx23885 */
708 dev->hwrevision = 0xa0;
709 break;
710 case 0x01:
711 /* CX23885-12Z */
712 dev->hwrevision = 0xa1;
713 break;
714 case 0x02:
715 /* CX23885-13Z */
716 dev->hwrevision = 0xb0;
717 break;
718 case 0x03:
719 /* CX23888-22Z */
720 dev->hwrevision = 0xc0;
721 break;
722 case 0x0e:
723 /* CX23887-15Z */
724 dev->hwrevision = 0xc0;
725 case 0x0f:
726 /* CX23887-14Z */
727 dev->hwrevision = 0xb1;
728 break;
729 default:
730 printk(KERN_ERR "%s() New hardware revision found 0x%x\n",
731 __func__, dev->hwrevision);
732 }
733 if (dev->hwrevision)
734 printk(KERN_INFO "%s() Hardware revision = 0x%02x\n",
735 __func__, dev->hwrevision);
736 else
737 printk(KERN_ERR "%s() Hardware revision unknown 0x%x\n",
738 __func__, dev->hwrevision);
739 }
740
cx23885_dev_setup(struct cx23885_dev * dev)741 static int cx23885_dev_setup(struct cx23885_dev *dev)
742 {
743 int i;
744
745 mutex_init(&dev->lock);
746
747 atomic_inc(&dev->refcount);
748
749 dev->nr = cx23885_devcount++;
750 sprintf(dev->name, "cx23885[%d]", dev->nr);
751
752 mutex_lock(&devlist);
753 list_add_tail(&dev->devlist, &cx23885_devlist);
754 mutex_unlock(&devlist);
755
756 /* Configure the internal memory */
757 if (dev->pci->device == 0x8880) {
758 dev->bridge = CX23885_BRIDGE_887;
759 /* Apply a sensible clock frequency for the PCIe bridge */
760 dev->clk_freq = 25000000;
761 dev->sram_channels = cx23887_sram_channels;
762 } else
763 if (dev->pci->device == 0x8852) {
764 dev->bridge = CX23885_BRIDGE_885;
765 /* Apply a sensible clock frequency for the PCIe bridge */
766 dev->clk_freq = 28000000;
767 dev->sram_channels = cx23885_sram_channels;
768 } else
769 BUG();
770
771 dprintk(1, "%s() Memory configured for PCIe bridge type %d\n",
772 __func__, dev->bridge);
773
774 /* board config */
775 dev->board = UNSET;
776 if (card[dev->nr] < cx23885_bcount)
777 dev->board = card[dev->nr];
778 for (i = 0; UNSET == dev->board && i < cx23885_idcount; i++)
779 if (dev->pci->subsystem_vendor == cx23885_subids[i].subvendor &&
780 dev->pci->subsystem_device == cx23885_subids[i].subdevice)
781 dev->board = cx23885_subids[i].card;
782 if (UNSET == dev->board) {
783 dev->board = CX23885_BOARD_UNKNOWN;
784 cx23885_card_list(dev);
785 }
786
787 /* If the user specific a clk freq override, apply it */
788 if (cx23885_boards[dev->board].clk_freq > 0)
789 dev->clk_freq = cx23885_boards[dev->board].clk_freq;
790
791 dev->pci_bus = dev->pci->bus->number;
792 dev->pci_slot = PCI_SLOT(dev->pci->devfn);
793 dev->pci_irqmask = 0x001f00;
794
795 /* External Master 1 Bus */
796 dev->i2c_bus[0].nr = 0;
797 dev->i2c_bus[0].dev = dev;
798 dev->i2c_bus[0].reg_stat = I2C1_STAT;
799 dev->i2c_bus[0].reg_ctrl = I2C1_CTRL;
800 dev->i2c_bus[0].reg_addr = I2C1_ADDR;
801 dev->i2c_bus[0].reg_rdata = I2C1_RDATA;
802 dev->i2c_bus[0].reg_wdata = I2C1_WDATA;
803 dev->i2c_bus[0].i2c_period = (0x9d << 24); /* 100kHz */
804
805 /* External Master 2 Bus */
806 dev->i2c_bus[1].nr = 1;
807 dev->i2c_bus[1].dev = dev;
808 dev->i2c_bus[1].reg_stat = I2C2_STAT;
809 dev->i2c_bus[1].reg_ctrl = I2C2_CTRL;
810 dev->i2c_bus[1].reg_addr = I2C2_ADDR;
811 dev->i2c_bus[1].reg_rdata = I2C2_RDATA;
812 dev->i2c_bus[1].reg_wdata = I2C2_WDATA;
813 dev->i2c_bus[1].i2c_period = (0x9d << 24); /* 100kHz */
814
815 /* Internal Master 3 Bus */
816 dev->i2c_bus[2].nr = 2;
817 dev->i2c_bus[2].dev = dev;
818 dev->i2c_bus[2].reg_stat = I2C3_STAT;
819 dev->i2c_bus[2].reg_ctrl = I2C3_CTRL;
820 dev->i2c_bus[2].reg_addr = I2C3_ADDR;
821 dev->i2c_bus[2].reg_rdata = I2C3_RDATA;
822 dev->i2c_bus[2].reg_wdata = I2C3_WDATA;
823 dev->i2c_bus[2].i2c_period = (0x07 << 24); /* 1.95MHz */
824
825 if ((cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) ||
826 (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER))
827 cx23885_init_tsport(dev, &dev->ts1, 1);
828
829 if ((cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) ||
830 (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER))
831 cx23885_init_tsport(dev, &dev->ts2, 2);
832
833 if (get_resources(dev) < 0) {
834 printk(KERN_ERR "CORE %s No more PCIe resources for "
835 "subsystem: %04x:%04x\n",
836 dev->name, dev->pci->subsystem_vendor,
837 dev->pci->subsystem_device);
838
839 cx23885_devcount--;
840 return -ENODEV;
841 }
842
843 /* PCIe stuff */
844 dev->lmmio = ioremap(pci_resource_start(dev->pci, 0),
845 pci_resource_len(dev->pci, 0));
846
847 dev->bmmio = (u8 __iomem *)dev->lmmio;
848
849 printk(KERN_INFO "CORE %s: subsystem: %04x:%04x, board: %s [card=%d,%s]\n",
850 dev->name, dev->pci->subsystem_vendor,
851 dev->pci->subsystem_device, cx23885_boards[dev->board].name,
852 dev->board, card[dev->nr] == dev->board ?
853 "insmod option" : "autodetected");
854
855 cx23885_pci_quirks(dev);
856
857 /* Assume some sensible defaults */
858 dev->tuner_type = cx23885_boards[dev->board].tuner_type;
859 dev->tuner_addr = cx23885_boards[dev->board].tuner_addr;
860 dev->radio_type = cx23885_boards[dev->board].radio_type;
861 dev->radio_addr = cx23885_boards[dev->board].radio_addr;
862
863 dprintk(1, "%s() tuner_type = 0x%x tuner_addr = 0x%x\n",
864 __func__, dev->tuner_type, dev->tuner_addr);
865 dprintk(1, "%s() radio_type = 0x%x radio_addr = 0x%x\n",
866 __func__, dev->radio_type, dev->radio_addr);
867
868 /* init hardware */
869 cx23885_reset(dev);
870
871 cx23885_i2c_register(&dev->i2c_bus[0]);
872 cx23885_i2c_register(&dev->i2c_bus[1]);
873 cx23885_i2c_register(&dev->i2c_bus[2]);
874 cx23885_card_setup(dev);
875 cx23885_call_i2c_clients(&dev->i2c_bus[0], TUNER_SET_STANDBY, NULL);
876 cx23885_ir_init(dev);
877
878 if (cx23885_boards[dev->board].porta == CX23885_ANALOG_VIDEO) {
879 if (cx23885_video_register(dev) < 0) {
880 printk(KERN_ERR "%s() Failed to register analog "
881 "video adapters on VID_A\n", __func__);
882 }
883 }
884
885 if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) {
886 if (cx23885_dvb_register(&dev->ts1) < 0) {
887 printk(KERN_ERR "%s() Failed to register dvb adapters on VID_B\n",
888 __func__);
889 }
890 } else
891 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) {
892 if (cx23885_417_register(dev) < 0) {
893 printk(KERN_ERR
894 "%s() Failed to register 417 on VID_B\n",
895 __func__);
896 }
897 }
898
899 if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) {
900 if (cx23885_dvb_register(&dev->ts2) < 0) {
901 printk(KERN_ERR
902 "%s() Failed to register dvb on VID_C\n",
903 __func__);
904 }
905 } else
906 if (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER) {
907 if (cx23885_417_register(dev) < 0) {
908 printk(KERN_ERR
909 "%s() Failed to register 417 on VID_C\n",
910 __func__);
911 }
912 }
913
914 cx23885_dev_checkrevision(dev);
915
916 return 0;
917 }
918
cx23885_dev_unregister(struct cx23885_dev * dev)919 static void cx23885_dev_unregister(struct cx23885_dev *dev)
920 {
921 release_mem_region(pci_resource_start(dev->pci, 0),
922 pci_resource_len(dev->pci, 0));
923
924 if (!atomic_dec_and_test(&dev->refcount))
925 return;
926
927 if (cx23885_boards[dev->board].porta == CX23885_ANALOG_VIDEO)
928 cx23885_video_unregister(dev);
929
930 if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB)
931 cx23885_dvb_unregister(&dev->ts1);
932
933 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
934 cx23885_417_unregister(dev);
935
936 if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB)
937 cx23885_dvb_unregister(&dev->ts2);
938
939 if (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER)
940 cx23885_417_unregister(dev);
941
942 cx23885_i2c_unregister(&dev->i2c_bus[2]);
943 cx23885_i2c_unregister(&dev->i2c_bus[1]);
944 cx23885_i2c_unregister(&dev->i2c_bus[0]);
945
946 iounmap(dev->lmmio);
947 }
948
cx23885_risc_field(__le32 * rp,struct scatterlist * sglist,unsigned int offset,u32 sync_line,unsigned int bpl,unsigned int padding,unsigned int lines)949 static __le32 *cx23885_risc_field(__le32 *rp, struct scatterlist *sglist,
950 unsigned int offset, u32 sync_line,
951 unsigned int bpl, unsigned int padding,
952 unsigned int lines)
953 {
954 struct scatterlist *sg;
955 unsigned int line, todo;
956
957 /* sync instruction */
958 if (sync_line != NO_SYNC_LINE)
959 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
960
961 /* scan lines */
962 sg = sglist;
963 for (line = 0; line < lines; line++) {
964 while (offset && offset >= sg_dma_len(sg)) {
965 offset -= sg_dma_len(sg);
966 sg++;
967 }
968 if (bpl <= sg_dma_len(sg)-offset) {
969 /* fits into current chunk */
970 *(rp++) = cpu_to_le32(RISC_WRITE|RISC_SOL|RISC_EOL|bpl);
971 *(rp++) = cpu_to_le32(sg_dma_address(sg)+offset);
972 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
973 offset += bpl;
974 } else {
975 /* scanline needs to be split */
976 todo = bpl;
977 *(rp++) = cpu_to_le32(RISC_WRITE|RISC_SOL|
978 (sg_dma_len(sg)-offset));
979 *(rp++) = cpu_to_le32(sg_dma_address(sg)+offset);
980 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
981 todo -= (sg_dma_len(sg)-offset);
982 offset = 0;
983 sg++;
984 while (todo > sg_dma_len(sg)) {
985 *(rp++) = cpu_to_le32(RISC_WRITE|
986 sg_dma_len(sg));
987 *(rp++) = cpu_to_le32(sg_dma_address(sg));
988 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
989 todo -= sg_dma_len(sg);
990 sg++;
991 }
992 *(rp++) = cpu_to_le32(RISC_WRITE|RISC_EOL|todo);
993 *(rp++) = cpu_to_le32(sg_dma_address(sg));
994 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
995 offset += todo;
996 }
997 offset += padding;
998 }
999
1000 return rp;
1001 }
1002
cx23885_risc_buffer(struct pci_dev * pci,struct btcx_riscmem * risc,struct scatterlist * sglist,unsigned int top_offset,unsigned int bottom_offset,unsigned int bpl,unsigned int padding,unsigned int lines)1003 int cx23885_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc,
1004 struct scatterlist *sglist, unsigned int top_offset,
1005 unsigned int bottom_offset, unsigned int bpl,
1006 unsigned int padding, unsigned int lines)
1007 {
1008 u32 instructions, fields;
1009 __le32 *rp;
1010 int rc;
1011
1012 fields = 0;
1013 if (UNSET != top_offset)
1014 fields++;
1015 if (UNSET != bottom_offset)
1016 fields++;
1017
1018 /* estimate risc mem: worst case is one write per page border +
1019 one write per scan line + syncs + jump (all 2 dwords). Padding
1020 can cause next bpl to start close to a page border. First DMA
1021 region may be smaller than PAGE_SIZE */
1022 /* write and jump need and extra dword */
1023 instructions = fields * (1 + ((bpl + padding) * lines)
1024 / PAGE_SIZE + lines);
1025 instructions += 2;
1026 rc = btcx_riscmem_alloc(pci, risc, instructions*12);
1027 if (rc < 0)
1028 return rc;
1029
1030 /* write risc instructions */
1031 rp = risc->cpu;
1032 if (UNSET != top_offset)
1033 rp = cx23885_risc_field(rp, sglist, top_offset, 0,
1034 bpl, padding, lines);
1035 if (UNSET != bottom_offset)
1036 rp = cx23885_risc_field(rp, sglist, bottom_offset, 0x200,
1037 bpl, padding, lines);
1038
1039 /* save pointer to jmp instruction address */
1040 risc->jmp = rp;
1041 BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size);
1042 return 0;
1043 }
1044
cx23885_risc_databuffer(struct pci_dev * pci,struct btcx_riscmem * risc,struct scatterlist * sglist,unsigned int bpl,unsigned int lines)1045 static int cx23885_risc_databuffer(struct pci_dev *pci,
1046 struct btcx_riscmem *risc,
1047 struct scatterlist *sglist,
1048 unsigned int bpl,
1049 unsigned int lines)
1050 {
1051 u32 instructions;
1052 __le32 *rp;
1053 int rc;
1054
1055 /* estimate risc mem: worst case is one write per page border +
1056 one write per scan line + syncs + jump (all 2 dwords). Here
1057 there is no padding and no sync. First DMA region may be smaller
1058 than PAGE_SIZE */
1059 /* Jump and write need an extra dword */
1060 instructions = 1 + (bpl * lines) / PAGE_SIZE + lines;
1061 instructions += 1;
1062
1063 rc = btcx_riscmem_alloc(pci, risc, instructions*12);
1064 if (rc < 0)
1065 return rc;
1066
1067 /* write risc instructions */
1068 rp = risc->cpu;
1069 rp = cx23885_risc_field(rp, sglist, 0, NO_SYNC_LINE, bpl, 0, lines);
1070
1071 /* save pointer to jmp instruction address */
1072 risc->jmp = rp;
1073 BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size);
1074 return 0;
1075 }
1076
cx23885_risc_stopper(struct pci_dev * pci,struct btcx_riscmem * risc,u32 reg,u32 mask,u32 value)1077 int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
1078 u32 reg, u32 mask, u32 value)
1079 {
1080 __le32 *rp;
1081 int rc;
1082
1083 rc = btcx_riscmem_alloc(pci, risc, 4*16);
1084 if (rc < 0)
1085 return rc;
1086
1087 /* write risc instructions */
1088 rp = risc->cpu;
1089 *(rp++) = cpu_to_le32(RISC_WRITECR | RISC_IRQ2);
1090 *(rp++) = cpu_to_le32(reg);
1091 *(rp++) = cpu_to_le32(value);
1092 *(rp++) = cpu_to_le32(mask);
1093 *(rp++) = cpu_to_le32(RISC_JUMP);
1094 *(rp++) = cpu_to_le32(risc->dma);
1095 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1096 return 0;
1097 }
1098
cx23885_free_buffer(struct videobuf_queue * q,struct cx23885_buffer * buf)1099 void cx23885_free_buffer(struct videobuf_queue *q, struct cx23885_buffer *buf)
1100 {
1101 struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
1102
1103 BUG_ON(in_interrupt());
1104 videobuf_waiton(&buf->vb, 0, 0);
1105 videobuf_dma_unmap(q, dma);
1106 videobuf_dma_free(dma);
1107 btcx_riscmem_free(to_pci_dev(q->dev), &buf->risc);
1108 buf->vb.state = VIDEOBUF_NEEDS_INIT;
1109 }
1110
cx23885_tsport_reg_dump(struct cx23885_tsport * port)1111 static void cx23885_tsport_reg_dump(struct cx23885_tsport *port)
1112 {
1113 struct cx23885_dev *dev = port->dev;
1114
1115 dprintk(1, "%s() Register Dump\n", __func__);
1116 dprintk(1, "%s() DEV_CNTRL2 0x%08X\n", __func__,
1117 cx_read(DEV_CNTRL2));
1118 dprintk(1, "%s() PCI_INT_MSK 0x%08X\n", __func__,
1119 cx_read(PCI_INT_MSK));
1120 dprintk(1, "%s() AUD_INT_INT_MSK 0x%08X\n", __func__,
1121 cx_read(AUDIO_INT_INT_MSK));
1122 dprintk(1, "%s() AUD_INT_DMA_CTL 0x%08X\n", __func__,
1123 cx_read(AUD_INT_DMA_CTL));
1124 dprintk(1, "%s() AUD_EXT_INT_MSK 0x%08X\n", __func__,
1125 cx_read(AUDIO_EXT_INT_MSK));
1126 dprintk(1, "%s() AUD_EXT_DMA_CTL 0x%08X\n", __func__,
1127 cx_read(AUD_EXT_DMA_CTL));
1128 dprintk(1, "%s() PAD_CTRL 0x%08X\n", __func__,
1129 cx_read(PAD_CTRL));
1130 dprintk(1, "%s() ALT_PIN_OUT_SEL 0x%08X\n", __func__,
1131 cx_read(ALT_PIN_OUT_SEL));
1132 dprintk(1, "%s() GPIO2 0x%08X\n", __func__,
1133 cx_read(GPIO2));
1134 dprintk(1, "%s() gpcnt(0x%08X) 0x%08X\n", __func__,
1135 port->reg_gpcnt, cx_read(port->reg_gpcnt));
1136 dprintk(1, "%s() gpcnt_ctl(0x%08X) 0x%08x\n", __func__,
1137 port->reg_gpcnt_ctl, cx_read(port->reg_gpcnt_ctl));
1138 dprintk(1, "%s() dma_ctl(0x%08X) 0x%08x\n", __func__,
1139 port->reg_dma_ctl, cx_read(port->reg_dma_ctl));
1140 if (port->reg_src_sel)
1141 dprintk(1, "%s() src_sel(0x%08X) 0x%08x\n", __func__,
1142 port->reg_src_sel, cx_read(port->reg_src_sel));
1143 dprintk(1, "%s() lngth(0x%08X) 0x%08x\n", __func__,
1144 port->reg_lngth, cx_read(port->reg_lngth));
1145 dprintk(1, "%s() hw_sop_ctrl(0x%08X) 0x%08x\n", __func__,
1146 port->reg_hw_sop_ctrl, cx_read(port->reg_hw_sop_ctrl));
1147 dprintk(1, "%s() gen_ctrl(0x%08X) 0x%08x\n", __func__,
1148 port->reg_gen_ctrl, cx_read(port->reg_gen_ctrl));
1149 dprintk(1, "%s() bd_pkt_status(0x%08X) 0x%08x\n", __func__,
1150 port->reg_bd_pkt_status, cx_read(port->reg_bd_pkt_status));
1151 dprintk(1, "%s() sop_status(0x%08X) 0x%08x\n", __func__,
1152 port->reg_sop_status, cx_read(port->reg_sop_status));
1153 dprintk(1, "%s() fifo_ovfl_stat(0x%08X) 0x%08x\n", __func__,
1154 port->reg_fifo_ovfl_stat, cx_read(port->reg_fifo_ovfl_stat));
1155 dprintk(1, "%s() vld_misc(0x%08X) 0x%08x\n", __func__,
1156 port->reg_vld_misc, cx_read(port->reg_vld_misc));
1157 dprintk(1, "%s() ts_clk_en(0x%08X) 0x%08x\n", __func__,
1158 port->reg_ts_clk_en, cx_read(port->reg_ts_clk_en));
1159 dprintk(1, "%s() ts_int_msk(0x%08X) 0x%08x\n", __func__,
1160 port->reg_ts_int_msk, cx_read(port->reg_ts_int_msk));
1161 }
1162
cx23885_start_dma(struct cx23885_tsport * port,struct cx23885_dmaqueue * q,struct cx23885_buffer * buf)1163 static int cx23885_start_dma(struct cx23885_tsport *port,
1164 struct cx23885_dmaqueue *q,
1165 struct cx23885_buffer *buf)
1166 {
1167 struct cx23885_dev *dev = port->dev;
1168 u32 reg;
1169
1170 dprintk(1, "%s() w: %d, h: %d, f: %d\n", __func__,
1171 buf->vb.width, buf->vb.height, buf->vb.field);
1172
1173 /* Stop the fifo and risc engine for this port */
1174 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1175
1176 /* setup fifo + format */
1177 cx23885_sram_channel_setup(dev,
1178 &dev->sram_channels[port->sram_chno],
1179 port->ts_packet_size, buf->risc.dma);
1180 if (debug > 5) {
1181 cx23885_sram_channel_dump(dev,
1182 &dev->sram_channels[port->sram_chno]);
1183 cx23885_risc_disasm(port, &buf->risc);
1184 }
1185
1186 /* write TS length to chip */
1187 cx_write(port->reg_lngth, buf->vb.width);
1188
1189 if ((!(cx23885_boards[dev->board].portb & CX23885_MPEG_DVB)) &&
1190 (!(cx23885_boards[dev->board].portc & CX23885_MPEG_DVB))) {
1191 printk("%s() Unsupported .portb/c (0x%08x)/(0x%08x)\n",
1192 __func__,
1193 cx23885_boards[dev->board].portb,
1194 cx23885_boards[dev->board].portc);
1195 return -EINVAL;
1196 }
1197
1198 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1199 cx23885_av_clk(dev, 0);
1200
1201 udelay(100);
1202
1203 /* If the port supports SRC SELECT, configure it */
1204 if (port->reg_src_sel)
1205 cx_write(port->reg_src_sel, port->src_sel_val);
1206
1207 cx_write(port->reg_hw_sop_ctrl, port->hw_sop_ctrl_val);
1208 cx_write(port->reg_ts_clk_en, port->ts_clk_en_val);
1209 cx_write(port->reg_vld_misc, port->vld_misc_val);
1210 cx_write(port->reg_gen_ctrl, port->gen_ctrl_val);
1211 udelay(100);
1212
1213 /* NOTE: this is 2 (reserved) for portb, does it matter? */
1214 /* reset counter to zero */
1215 cx_write(port->reg_gpcnt_ctl, 3);
1216 q->count = 1;
1217
1218 /* Set VIDB pins to input */
1219 if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) {
1220 reg = cx_read(PAD_CTRL);
1221 reg &= ~0x3; /* Clear TS1_OE & TS1_SOP_OE */
1222 cx_write(PAD_CTRL, reg);
1223 }
1224
1225 /* Set VIDC pins to input */
1226 if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) {
1227 reg = cx_read(PAD_CTRL);
1228 reg &= ~0x4; /* Clear TS2_SOP_OE */
1229 cx_write(PAD_CTRL, reg);
1230 }
1231
1232 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) {
1233
1234 reg = cx_read(PAD_CTRL);
1235 reg = reg & ~0x1; /* Clear TS1_OE */
1236
1237 /* FIXME, bit 2 writing here is questionable */
1238 /* set TS1_SOP_OE and TS1_OE_HI */
1239 reg = reg | 0xa;
1240 cx_write(PAD_CTRL, reg);
1241
1242 /* FIXME and these two registers should be documented. */
1243 cx_write(CLK_DELAY, cx_read(CLK_DELAY) | 0x80000011);
1244 cx_write(ALT_PIN_OUT_SEL, 0x10100045);
1245 }
1246
1247 switch (dev->bridge) {
1248 case CX23885_BRIDGE_885:
1249 case CX23885_BRIDGE_887:
1250 /* enable irqs */
1251 dprintk(1, "%s() enabling TS int's and DMA\n", __func__);
1252 cx_set(port->reg_ts_int_msk, port->ts_int_msk_val);
1253 cx_set(port->reg_dma_ctl, port->dma_ctl_val);
1254 cx_set(PCI_INT_MSK, dev->pci_irqmask | port->pci_irqmask);
1255 break;
1256 default:
1257 BUG();
1258 }
1259
1260 cx_set(DEV_CNTRL2, (1<<5)); /* Enable RISC controller */
1261
1262 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1263 cx23885_av_clk(dev, 1);
1264
1265 if (debug > 4)
1266 cx23885_tsport_reg_dump(port);
1267
1268 return 0;
1269 }
1270
cx23885_stop_dma(struct cx23885_tsport * port)1271 static int cx23885_stop_dma(struct cx23885_tsport *port)
1272 {
1273 struct cx23885_dev *dev = port->dev;
1274 u32 reg;
1275
1276 dprintk(1, "%s()\n", __func__);
1277
1278 /* Stop interrupts and DMA */
1279 cx_clear(port->reg_ts_int_msk, port->ts_int_msk_val);
1280 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1281
1282 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) {
1283
1284 reg = cx_read(PAD_CTRL);
1285
1286 /* Set TS1_OE */
1287 reg = reg | 0x1;
1288
1289 /* clear TS1_SOP_OE and TS1_OE_HI */
1290 reg = reg & ~0xa;
1291 cx_write(PAD_CTRL, reg);
1292 cx_write(port->reg_src_sel, 0);
1293 cx_write(port->reg_gen_ctrl, 8);
1294
1295 }
1296
1297 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1298 cx23885_av_clk(dev, 0);
1299
1300 return 0;
1301 }
1302
cx23885_restart_queue(struct cx23885_tsport * port,struct cx23885_dmaqueue * q)1303 int cx23885_restart_queue(struct cx23885_tsport *port,
1304 struct cx23885_dmaqueue *q)
1305 {
1306 struct cx23885_dev *dev = port->dev;
1307 struct cx23885_buffer *buf;
1308
1309 dprintk(5, "%s()\n", __func__);
1310 if (list_empty(&q->active)) {
1311 struct cx23885_buffer *prev;
1312 prev = NULL;
1313
1314 dprintk(5, "%s() queue is empty\n", __func__);
1315
1316 for (;;) {
1317 if (list_empty(&q->queued))
1318 return 0;
1319 buf = list_entry(q->queued.next, struct cx23885_buffer,
1320 vb.queue);
1321 if (NULL == prev) {
1322 list_del(&buf->vb.queue);
1323 list_add_tail(&buf->vb.queue, &q->active);
1324 cx23885_start_dma(port, q, buf);
1325 buf->vb.state = VIDEOBUF_ACTIVE;
1326 buf->count = q->count++;
1327 mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT);
1328 dprintk(5, "[%p/%d] restart_queue - f/active\n",
1329 buf, buf->vb.i);
1330
1331 } else if (prev->vb.width == buf->vb.width &&
1332 prev->vb.height == buf->vb.height &&
1333 prev->fmt == buf->fmt) {
1334 list_del(&buf->vb.queue);
1335 list_add_tail(&buf->vb.queue, &q->active);
1336 buf->vb.state = VIDEOBUF_ACTIVE;
1337 buf->count = q->count++;
1338 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
1339 /* 64 bit bits 63-32 */
1340 prev->risc.jmp[2] = cpu_to_le32(0);
1341 dprintk(5, "[%p/%d] restart_queue - m/active\n",
1342 buf, buf->vb.i);
1343 } else {
1344 return 0;
1345 }
1346 prev = buf;
1347 }
1348 return 0;
1349 }
1350
1351 buf = list_entry(q->active.next, struct cx23885_buffer, vb.queue);
1352 dprintk(2, "restart_queue [%p/%d]: restart dma\n",
1353 buf, buf->vb.i);
1354 cx23885_start_dma(port, q, buf);
1355 list_for_each_entry(buf, &q->active, vb.queue)
1356 buf->count = q->count++;
1357 mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
1358 return 0;
1359 }
1360
1361 /* ------------------------------------------------------------------ */
1362
cx23885_buf_prepare(struct videobuf_queue * q,struct cx23885_tsport * port,struct cx23885_buffer * buf,enum v4l2_field field)1363 int cx23885_buf_prepare(struct videobuf_queue *q, struct cx23885_tsport *port,
1364 struct cx23885_buffer *buf, enum v4l2_field field)
1365 {
1366 struct cx23885_dev *dev = port->dev;
1367 int size = port->ts_packet_size * port->ts_packet_count;
1368 int rc;
1369
1370 dprintk(1, "%s: %p\n", __func__, buf);
1371 if (0 != buf->vb.baddr && buf->vb.bsize < size)
1372 return -EINVAL;
1373
1374 if (VIDEOBUF_NEEDS_INIT == buf->vb.state) {
1375 buf->vb.width = port->ts_packet_size;
1376 buf->vb.height = port->ts_packet_count;
1377 buf->vb.size = size;
1378 buf->vb.field = field /*V4L2_FIELD_TOP*/;
1379
1380 rc = videobuf_iolock(q, &buf->vb, NULL);
1381 if (0 != rc)
1382 goto fail;
1383 cx23885_risc_databuffer(dev->pci, &buf->risc,
1384 videobuf_to_dma(&buf->vb)->sglist,
1385 buf->vb.width, buf->vb.height);
1386 }
1387 buf->vb.state = VIDEOBUF_PREPARED;
1388 return 0;
1389
1390 fail:
1391 cx23885_free_buffer(q, buf);
1392 return rc;
1393 }
1394
cx23885_buf_queue(struct cx23885_tsport * port,struct cx23885_buffer * buf)1395 void cx23885_buf_queue(struct cx23885_tsport *port, struct cx23885_buffer *buf)
1396 {
1397 struct cx23885_buffer *prev;
1398 struct cx23885_dev *dev = port->dev;
1399 struct cx23885_dmaqueue *cx88q = &port->mpegq;
1400
1401 /* add jump to stopper */
1402 buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
1403 buf->risc.jmp[1] = cpu_to_le32(cx88q->stopper.dma);
1404 buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */
1405
1406 if (list_empty(&cx88q->active)) {
1407 dprintk(1, "queue is empty - first active\n");
1408 list_add_tail(&buf->vb.queue, &cx88q->active);
1409 cx23885_start_dma(port, cx88q, buf);
1410 buf->vb.state = VIDEOBUF_ACTIVE;
1411 buf->count = cx88q->count++;
1412 mod_timer(&cx88q->timeout, jiffies + BUFFER_TIMEOUT);
1413 dprintk(1, "[%p/%d] %s - first active\n",
1414 buf, buf->vb.i, __func__);
1415 } else {
1416 dprintk(1, "queue is not empty - append to active\n");
1417 prev = list_entry(cx88q->active.prev, struct cx23885_buffer,
1418 vb.queue);
1419 list_add_tail(&buf->vb.queue, &cx88q->active);
1420 buf->vb.state = VIDEOBUF_ACTIVE;
1421 buf->count = cx88q->count++;
1422 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
1423 prev->risc.jmp[2] = cpu_to_le32(0); /* 64 bit bits 63-32 */
1424 dprintk(1, "[%p/%d] %s - append to active\n",
1425 buf, buf->vb.i, __func__);
1426 }
1427 }
1428
1429 /* ----------------------------------------------------------- */
1430
do_cancel_buffers(struct cx23885_tsport * port,char * reason,int restart)1431 static void do_cancel_buffers(struct cx23885_tsport *port, char *reason,
1432 int restart)
1433 {
1434 struct cx23885_dev *dev = port->dev;
1435 struct cx23885_dmaqueue *q = &port->mpegq;
1436 struct cx23885_buffer *buf;
1437 unsigned long flags;
1438
1439 spin_lock_irqsave(&port->slock, flags);
1440 while (!list_empty(&q->active)) {
1441 buf = list_entry(q->active.next, struct cx23885_buffer,
1442 vb.queue);
1443 list_del(&buf->vb.queue);
1444 buf->vb.state = VIDEOBUF_ERROR;
1445 wake_up(&buf->vb.done);
1446 dprintk(1, "[%p/%d] %s - dma=0x%08lx\n",
1447 buf, buf->vb.i, reason, (unsigned long)buf->risc.dma);
1448 }
1449 if (restart) {
1450 dprintk(1, "restarting queue\n");
1451 cx23885_restart_queue(port, q);
1452 }
1453 spin_unlock_irqrestore(&port->slock, flags);
1454 }
1455
cx23885_cancel_buffers(struct cx23885_tsport * port)1456 void cx23885_cancel_buffers(struct cx23885_tsport *port)
1457 {
1458 struct cx23885_dev *dev = port->dev;
1459 struct cx23885_dmaqueue *q = &port->mpegq;
1460
1461 dprintk(1, "%s()\n", __func__);
1462 del_timer_sync(&q->timeout);
1463 cx23885_stop_dma(port);
1464 do_cancel_buffers(port, "cancel", 0);
1465 }
1466
cx23885_timeout(unsigned long data)1467 static void cx23885_timeout(unsigned long data)
1468 {
1469 struct cx23885_tsport *port = (struct cx23885_tsport *)data;
1470 struct cx23885_dev *dev = port->dev;
1471
1472 dprintk(1, "%s()\n", __func__);
1473
1474 if (debug > 5)
1475 cx23885_sram_channel_dump(dev,
1476 &dev->sram_channels[port->sram_chno]);
1477
1478 cx23885_stop_dma(port);
1479 do_cancel_buffers(port, "timeout", 1);
1480 }
1481
cx23885_irq_417(struct cx23885_dev * dev,u32 status)1482 int cx23885_irq_417(struct cx23885_dev *dev, u32 status)
1483 {
1484 /* FIXME: port1 assumption here. */
1485 struct cx23885_tsport *port = &dev->ts1;
1486 int count = 0;
1487 int handled = 0;
1488
1489 if (status == 0)
1490 return handled;
1491
1492 count = cx_read(port->reg_gpcnt);
1493 dprintk(7, "status: 0x%08x mask: 0x%08x count: 0x%x\n",
1494 status, cx_read(port->reg_ts_int_msk), count);
1495
1496 if ((status & VID_B_MSK_BAD_PKT) ||
1497 (status & VID_B_MSK_OPC_ERR) ||
1498 (status & VID_B_MSK_VBI_OPC_ERR) ||
1499 (status & VID_B_MSK_SYNC) ||
1500 (status & VID_B_MSK_VBI_SYNC) ||
1501 (status & VID_B_MSK_OF) ||
1502 (status & VID_B_MSK_VBI_OF)) {
1503 printk(KERN_ERR "%s: V4L mpeg risc op code error, status "
1504 "= 0x%x\n", dev->name, status);
1505 if (status & VID_B_MSK_BAD_PKT)
1506 dprintk(1, " VID_B_MSK_BAD_PKT\n");
1507 if (status & VID_B_MSK_OPC_ERR)
1508 dprintk(1, " VID_B_MSK_OPC_ERR\n");
1509 if (status & VID_B_MSK_VBI_OPC_ERR)
1510 dprintk(1, " VID_B_MSK_VBI_OPC_ERR\n");
1511 if (status & VID_B_MSK_SYNC)
1512 dprintk(1, " VID_B_MSK_SYNC\n");
1513 if (status & VID_B_MSK_VBI_SYNC)
1514 dprintk(1, " VID_B_MSK_VBI_SYNC\n");
1515 if (status & VID_B_MSK_OF)
1516 dprintk(1, " VID_B_MSK_OF\n");
1517 if (status & VID_B_MSK_VBI_OF)
1518 dprintk(1, " VID_B_MSK_VBI_OF\n");
1519
1520 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1521 cx23885_sram_channel_dump(dev,
1522 &dev->sram_channels[port->sram_chno]);
1523 cx23885_417_check_encoder(dev);
1524 } else if (status & VID_B_MSK_RISCI1) {
1525 dprintk(7, " VID_B_MSK_RISCI1\n");
1526 spin_lock(&port->slock);
1527 cx23885_wakeup(port, &port->mpegq, count);
1528 spin_unlock(&port->slock);
1529 } else if (status & VID_B_MSK_RISCI2) {
1530 dprintk(7, " VID_B_MSK_RISCI2\n");
1531 spin_lock(&port->slock);
1532 cx23885_restart_queue(port, &port->mpegq);
1533 spin_unlock(&port->slock);
1534 }
1535 if (status) {
1536 cx_write(port->reg_ts_int_stat, status);
1537 handled = 1;
1538 }
1539
1540 return handled;
1541 }
1542
cx23885_irq_ts(struct cx23885_tsport * port,u32 status)1543 static int cx23885_irq_ts(struct cx23885_tsport *port, u32 status)
1544 {
1545 struct cx23885_dev *dev = port->dev;
1546 int handled = 0;
1547 u32 count;
1548
1549 if ((status & VID_BC_MSK_OPC_ERR) ||
1550 (status & VID_BC_MSK_BAD_PKT) ||
1551 (status & VID_BC_MSK_SYNC) ||
1552 (status & VID_BC_MSK_OF)) {
1553
1554 if (status & VID_BC_MSK_OPC_ERR)
1555 dprintk(7, " (VID_BC_MSK_OPC_ERR 0x%08x)\n",
1556 VID_BC_MSK_OPC_ERR);
1557
1558 if (status & VID_BC_MSK_BAD_PKT)
1559 dprintk(7, " (VID_BC_MSK_BAD_PKT 0x%08x)\n",
1560 VID_BC_MSK_BAD_PKT);
1561
1562 if (status & VID_BC_MSK_SYNC)
1563 dprintk(7, " (VID_BC_MSK_SYNC 0x%08x)\n",
1564 VID_BC_MSK_SYNC);
1565
1566 if (status & VID_BC_MSK_OF)
1567 dprintk(7, " (VID_BC_MSK_OF 0x%08x)\n",
1568 VID_BC_MSK_OF);
1569
1570 printk(KERN_ERR "%s: mpeg risc op code error\n", dev->name);
1571
1572 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1573 cx23885_sram_channel_dump(dev,
1574 &dev->sram_channels[port->sram_chno]);
1575
1576 } else if (status & VID_BC_MSK_RISCI1) {
1577
1578 dprintk(7, " (RISCI1 0x%08x)\n", VID_BC_MSK_RISCI1);
1579
1580 spin_lock(&port->slock);
1581 count = cx_read(port->reg_gpcnt);
1582 cx23885_wakeup(port, &port->mpegq, count);
1583 spin_unlock(&port->slock);
1584
1585 } else if (status & VID_BC_MSK_RISCI2) {
1586
1587 dprintk(7, " (RISCI2 0x%08x)\n", VID_BC_MSK_RISCI2);
1588
1589 spin_lock(&port->slock);
1590 cx23885_restart_queue(port, &port->mpegq);
1591 spin_unlock(&port->slock);
1592
1593 }
1594 if (status) {
1595 cx_write(port->reg_ts_int_stat, status);
1596 handled = 1;
1597 }
1598
1599 return handled;
1600 }
1601
cx23885_irq(int irq,void * dev_id)1602 static irqreturn_t cx23885_irq(int irq, void *dev_id)
1603 {
1604 struct cx23885_dev *dev = dev_id;
1605 struct cx23885_tsport *ts1 = &dev->ts1;
1606 struct cx23885_tsport *ts2 = &dev->ts2;
1607 u32 pci_status, pci_mask;
1608 u32 vida_status, vida_mask;
1609 u32 ts1_status, ts1_mask;
1610 u32 ts2_status, ts2_mask;
1611 int vida_count = 0, ts1_count = 0, ts2_count = 0, handled = 0;
1612
1613 pci_status = cx_read(PCI_INT_STAT);
1614 pci_mask = cx_read(PCI_INT_MSK);
1615 vida_status = cx_read(VID_A_INT_STAT);
1616 vida_mask = cx_read(VID_A_INT_MSK);
1617 ts1_status = cx_read(VID_B_INT_STAT);
1618 ts1_mask = cx_read(VID_B_INT_MSK);
1619 ts2_status = cx_read(VID_C_INT_STAT);
1620 ts2_mask = cx_read(VID_C_INT_MSK);
1621
1622 if ((pci_status == 0) && (ts2_status == 0) && (ts1_status == 0))
1623 goto out;
1624
1625 vida_count = cx_read(VID_A_GPCNT);
1626 ts1_count = cx_read(ts1->reg_gpcnt);
1627 ts2_count = cx_read(ts2->reg_gpcnt);
1628 dprintk(7, "pci_status: 0x%08x pci_mask: 0x%08x\n",
1629 pci_status, pci_mask);
1630 dprintk(7, "vida_status: 0x%08x vida_mask: 0x%08x count: 0x%x\n",
1631 vida_status, vida_mask, vida_count);
1632 dprintk(7, "ts1_status: 0x%08x ts1_mask: 0x%08x count: 0x%x\n",
1633 ts1_status, ts1_mask, ts1_count);
1634 dprintk(7, "ts2_status: 0x%08x ts2_mask: 0x%08x count: 0x%x\n",
1635 ts2_status, ts2_mask, ts2_count);
1636
1637 if ((pci_status & PCI_MSK_RISC_RD) ||
1638 (pci_status & PCI_MSK_RISC_WR) ||
1639 (pci_status & PCI_MSK_AL_RD) ||
1640 (pci_status & PCI_MSK_AL_WR) ||
1641 (pci_status & PCI_MSK_APB_DMA) ||
1642 (pci_status & PCI_MSK_VID_C) ||
1643 (pci_status & PCI_MSK_VID_B) ||
1644 (pci_status & PCI_MSK_VID_A) ||
1645 (pci_status & PCI_MSK_AUD_INT) ||
1646 (pci_status & PCI_MSK_AUD_EXT)) {
1647
1648 if (pci_status & PCI_MSK_RISC_RD)
1649 dprintk(7, " (PCI_MSK_RISC_RD 0x%08x)\n",
1650 PCI_MSK_RISC_RD);
1651
1652 if (pci_status & PCI_MSK_RISC_WR)
1653 dprintk(7, " (PCI_MSK_RISC_WR 0x%08x)\n",
1654 PCI_MSK_RISC_WR);
1655
1656 if (pci_status & PCI_MSK_AL_RD)
1657 dprintk(7, " (PCI_MSK_AL_RD 0x%08x)\n",
1658 PCI_MSK_AL_RD);
1659
1660 if (pci_status & PCI_MSK_AL_WR)
1661 dprintk(7, " (PCI_MSK_AL_WR 0x%08x)\n",
1662 PCI_MSK_AL_WR);
1663
1664 if (pci_status & PCI_MSK_APB_DMA)
1665 dprintk(7, " (PCI_MSK_APB_DMA 0x%08x)\n",
1666 PCI_MSK_APB_DMA);
1667
1668 if (pci_status & PCI_MSK_VID_C)
1669 dprintk(7, " (PCI_MSK_VID_C 0x%08x)\n",
1670 PCI_MSK_VID_C);
1671
1672 if (pci_status & PCI_MSK_VID_B)
1673 dprintk(7, " (PCI_MSK_VID_B 0x%08x)\n",
1674 PCI_MSK_VID_B);
1675
1676 if (pci_status & PCI_MSK_VID_A)
1677 dprintk(7, " (PCI_MSK_VID_A 0x%08x)\n",
1678 PCI_MSK_VID_A);
1679
1680 if (pci_status & PCI_MSK_AUD_INT)
1681 dprintk(7, " (PCI_MSK_AUD_INT 0x%08x)\n",
1682 PCI_MSK_AUD_INT);
1683
1684 if (pci_status & PCI_MSK_AUD_EXT)
1685 dprintk(7, " (PCI_MSK_AUD_EXT 0x%08x)\n",
1686 PCI_MSK_AUD_EXT);
1687
1688 }
1689
1690 if (ts1_status) {
1691 if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB)
1692 handled += cx23885_irq_ts(ts1, ts1_status);
1693 else
1694 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1695 handled += cx23885_irq_417(dev, ts1_status);
1696 }
1697
1698 if (ts2_status) {
1699 if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB)
1700 handled += cx23885_irq_ts(ts2, ts2_status);
1701 else
1702 if (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER)
1703 handled += cx23885_irq_417(dev, ts2_status);
1704 }
1705
1706 if (vida_status)
1707 handled += cx23885_video_irq(dev, vida_status);
1708
1709 if (handled)
1710 cx_write(PCI_INT_STAT, pci_status);
1711 out:
1712 return IRQ_RETVAL(handled);
1713 }
1714
cx23885_initdev(struct pci_dev * pci_dev,const struct pci_device_id * pci_id)1715 static int __devinit cx23885_initdev(struct pci_dev *pci_dev,
1716 const struct pci_device_id *pci_id)
1717 {
1718 struct cx23885_dev *dev;
1719 int err;
1720
1721 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1722 if (NULL == dev)
1723 return -ENOMEM;
1724
1725 /* pci init */
1726 dev->pci = pci_dev;
1727 if (pci_enable_device(pci_dev)) {
1728 err = -EIO;
1729 goto fail_free;
1730 }
1731
1732 if (cx23885_dev_setup(dev) < 0) {
1733 err = -EINVAL;
1734 goto fail_free;
1735 }
1736
1737 /* print pci info */
1738 pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev);
1739 pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat);
1740 printk(KERN_INFO "%s/0: found at %s, rev: %d, irq: %d, "
1741 "latency: %d, mmio: 0x%llx\n", dev->name,
1742 pci_name(pci_dev), dev->pci_rev, pci_dev->irq,
1743 dev->pci_lat,
1744 (unsigned long long)pci_resource_start(pci_dev, 0));
1745
1746 pci_set_master(pci_dev);
1747 if (!pci_dma_supported(pci_dev, 0xffffffff)) {
1748 printk("%s/0: Oops: no 32bit PCI DMA ???\n", dev->name);
1749 err = -EIO;
1750 goto fail_irq;
1751 }
1752
1753 err = request_irq(pci_dev->irq, cx23885_irq,
1754 IRQF_SHARED | IRQF_DISABLED, dev->name, dev);
1755 if (err < 0) {
1756 printk(KERN_ERR "%s: can't get IRQ %d\n",
1757 dev->name, pci_dev->irq);
1758 goto fail_irq;
1759 }
1760
1761 pci_set_drvdata(pci_dev, dev);
1762 return 0;
1763
1764 fail_irq:
1765 cx23885_dev_unregister(dev);
1766 fail_free:
1767 kfree(dev);
1768 return err;
1769 }
1770
cx23885_finidev(struct pci_dev * pci_dev)1771 static void __devexit cx23885_finidev(struct pci_dev *pci_dev)
1772 {
1773 struct cx23885_dev *dev = pci_get_drvdata(pci_dev);
1774
1775 cx23885_shutdown(dev);
1776
1777 pci_disable_device(pci_dev);
1778
1779 /* unregister stuff */
1780 free_irq(pci_dev->irq, dev);
1781 pci_set_drvdata(pci_dev, NULL);
1782
1783 mutex_lock(&devlist);
1784 list_del(&dev->devlist);
1785 mutex_unlock(&devlist);
1786
1787 cx23885_dev_unregister(dev);
1788 kfree(dev);
1789 }
1790
1791 static struct pci_device_id cx23885_pci_tbl[] = {
1792 {
1793 /* CX23885 */
1794 .vendor = 0x14f1,
1795 .device = 0x8852,
1796 .subvendor = PCI_ANY_ID,
1797 .subdevice = PCI_ANY_ID,
1798 }, {
1799 /* CX23887 Rev 2 */
1800 .vendor = 0x14f1,
1801 .device = 0x8880,
1802 .subvendor = PCI_ANY_ID,
1803 .subdevice = PCI_ANY_ID,
1804 }, {
1805 /* --- end of list --- */
1806 }
1807 };
1808 MODULE_DEVICE_TABLE(pci, cx23885_pci_tbl);
1809
1810 static struct pci_driver cx23885_pci_driver = {
1811 .name = "cx23885",
1812 .id_table = cx23885_pci_tbl,
1813 .probe = cx23885_initdev,
1814 .remove = __devexit_p(cx23885_finidev),
1815 /* TODO */
1816 .suspend = NULL,
1817 .resume = NULL,
1818 };
1819
cx23885_init(void)1820 static int cx23885_init(void)
1821 {
1822 printk(KERN_INFO "cx23885 driver version %d.%d.%d loaded\n",
1823 (CX23885_VERSION_CODE >> 16) & 0xff,
1824 (CX23885_VERSION_CODE >> 8) & 0xff,
1825 CX23885_VERSION_CODE & 0xff);
1826 #ifdef SNAPSHOT
1827 printk(KERN_INFO "cx23885: snapshot date %04d-%02d-%02d\n",
1828 SNAPSHOT/10000, (SNAPSHOT/100)%100, SNAPSHOT%100);
1829 #endif
1830 return pci_register_driver(&cx23885_pci_driver);
1831 }
1832
cx23885_fini(void)1833 static void cx23885_fini(void)
1834 {
1835 pci_unregister_driver(&cx23885_pci_driver);
1836 }
1837
1838 module_init(cx23885_init);
1839 module_exit(cx23885_fini);
1840
1841 /* ----------------------------------------------------------- */
1842