1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle
7 * Copyright (C) 1995, 96, 97, 98, 99, 2000, 01, 02, 03 by Ralf Baechle
8 */
9 #ifndef _ASM_IRQ_H
10 #define _ASM_IRQ_H
11
12 #include <linux/linkage.h>
13
14 #include <asm/mipsmtregs.h>
15
16 #include <irq.h>
17
18 #ifdef CONFIG_I8259
irq_canonicalize(int irq)19 static inline int irq_canonicalize(int irq)
20 {
21 return ((irq == I8259A_IRQ_BASE + 2) ? I8259A_IRQ_BASE + 9 : irq);
22 }
23 #else
24 #define irq_canonicalize(irq) (irq) /* Sane hardware, sane code ... */
25 #endif
26
27 #ifdef CONFIG_MIPS_MT_SMTC
28
29 struct irqaction;
30
31 extern unsigned long irq_hwmask[];
32 extern int setup_irq_smtc(unsigned int irq, struct irqaction * new,
33 unsigned long hwmask);
34
smtc_im_ack_irq(unsigned int irq)35 static inline void smtc_im_ack_irq(unsigned int irq)
36 {
37 if (irq_hwmask[irq] & ST0_IM)
38 set_c0_status(irq_hwmask[irq] & ST0_IM);
39 }
40
41 #else
42
smtc_im_ack_irq(unsigned int irq)43 static inline void smtc_im_ack_irq(unsigned int irq)
44 {
45 }
46
47 #endif /* CONFIG_MIPS_MT_SMTC */
48
49 #ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
50 #include <linux/cpumask.h>
51
52 extern void plat_set_irq_affinity(unsigned int irq,
53 const struct cpumask *affinity);
54 extern void smtc_forward_irq(unsigned int irq);
55
56 /*
57 * IRQ affinity hook invoked at the beginning of interrupt dispatch
58 * if option is enabled.
59 *
60 * Up through Linux 2.6.22 (at least) cpumask operations are very
61 * inefficient on MIPS. Initial prototypes of SMTC IRQ affinity
62 * used a "fast path" per-IRQ-descriptor cache of affinity information
63 * to reduce latency. As there is a project afoot to optimize the
64 * cpumask implementations, this version is optimistically assuming
65 * that cpumask.h macro overhead is reasonable during interrupt dispatch.
66 */
67 #define IRQ_AFFINITY_HOOK(irq) \
68 do { \
69 if (!cpu_isset(smp_processor_id(), irq_desc[irq].affinity)) { \
70 smtc_forward_irq(irq); \
71 irq_exit(); \
72 return; \
73 } \
74 } while (0)
75
76 #else /* Not doing SMTC affinity */
77
78 #define IRQ_AFFINITY_HOOK(irq) do { } while (0)
79
80 #endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
81
82 #ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP
83
84 /*
85 * Clear interrupt mask handling "backstop" if irq_hwmask
86 * entry so indicates. This implies that the ack() or end()
87 * functions will take over re-enabling the low-level mask.
88 * Otherwise it will be done on return from exception.
89 */
90 #define __DO_IRQ_SMTC_HOOK(irq) \
91 do { \
92 IRQ_AFFINITY_HOOK(irq); \
93 if (irq_hwmask[irq] & 0x0000ff00) \
94 write_c0_tccontext(read_c0_tccontext() & \
95 ~(irq_hwmask[irq] & 0x0000ff00)); \
96 } while (0)
97
98 #define __NO_AFFINITY_IRQ_SMTC_HOOK(irq) \
99 do { \
100 if (irq_hwmask[irq] & 0x0000ff00) \
101 write_c0_tccontext(read_c0_tccontext() & \
102 ~(irq_hwmask[irq] & 0x0000ff00)); \
103 } while (0)
104
105 #else
106
107 #define __DO_IRQ_SMTC_HOOK(irq) \
108 do { \
109 IRQ_AFFINITY_HOOK(irq); \
110 } while (0)
111 #define __NO_AFFINITY_IRQ_SMTC_HOOK(irq) do { } while (0)
112
113 #endif
114
115 /*
116 * do_IRQ handles all normal device IRQ's (the special
117 * SMP cross-CPU interrupts have their own specific
118 * handlers).
119 *
120 * Ideally there should be away to get this into kernel/irq/handle.c to
121 * avoid the overhead of a call for just a tiny function ...
122 */
123 #define do_IRQ(irq) \
124 do { \
125 irq_enter(); \
126 __DO_IRQ_SMTC_HOOK(irq); \
127 generic_handle_irq(irq); \
128 irq_exit(); \
129 } while (0)
130
131 #ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
132 /*
133 * To avoid inefficient and in some cases pathological re-checking of
134 * IRQ affinity, we have this variant that skips the affinity check.
135 */
136
137
138 #define do_IRQ_no_affinity(irq) \
139 do { \
140 irq_enter(); \
141 __NO_AFFINITY_IRQ_SMTC_HOOK(irq); \
142 generic_handle_irq(irq); \
143 irq_exit(); \
144 } while (0)
145
146 #endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
147
148 extern void arch_init_irq(void);
149 extern void spurious_interrupt(void);
150
151 extern int allocate_irqno(void);
152 extern void alloc_legacy_irqno(void);
153 extern void free_irqno(unsigned int irq);
154
155 /*
156 * Before R2 the timer and performance counter interrupts were both fixed to
157 * IE7. Since R2 their number has to be read from the c0_intctl register.
158 */
159 #define CP0_LEGACY_COMPARE_IRQ 7
160
161 extern int cp0_compare_irq;
162 extern int cp0_perfcount_irq;
163
164 #endif /* _ASM_IRQ_H */
165