1 /** 2 * \file drm.h 3 * Header for the Direct Rendering Manager 4 * 5 * \author Rickard E. (Rik) Faith <faith@valinux.com> 6 * 7 * \par Acknowledgments: 8 * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic \c cmpxchg. 9 */ 10 11 /* 12 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 13 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 14 * All rights reserved. 15 * 16 * Permission is hereby granted, free of charge, to any person obtaining a 17 * copy of this software and associated documentation files (the "Software"), 18 * to deal in the Software without restriction, including without limitation 19 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 20 * and/or sell copies of the Software, and to permit persons to whom the 21 * Software is furnished to do so, subject to the following conditions: 22 * 23 * The above copyright notice and this permission notice (including the next 24 * paragraph) shall be included in all copies or substantial portions of the 25 * Software. 26 * 27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 28 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 29 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 30 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 31 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 32 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 33 * OTHER DEALINGS IN THE SOFTWARE. 34 */ 35 36 #ifndef _DRM_H_ 37 #define _DRM_H_ 38 39 #if defined(__KERNEL__) 40 #endif 41 #include <asm/ioctl.h> /* For _IO* macros */ 42 #define DRM_IOCTL_NR(n) _IOC_NR(n) 43 #define DRM_IOC_VOID _IOC_NONE 44 #define DRM_IOC_READ _IOC_READ 45 #define DRM_IOC_WRITE _IOC_WRITE 46 #define DRM_IOC_READWRITE _IOC_READ|_IOC_WRITE 47 #define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size) 48 49 #define DRM_MAJOR 226 50 #define DRM_MAX_MINOR 15 51 52 #define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */ 53 #define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */ 54 #define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */ 55 #define DRM_RAM_PERCENT 10 /**< How much system ram can we lock? */ 56 57 #define _DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */ 58 #define _DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */ 59 #define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD) 60 #define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT) 61 #define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT)) 62 63 typedef unsigned int drm_handle_t; 64 typedef unsigned int drm_context_t; 65 typedef unsigned int drm_drawable_t; 66 typedef unsigned int drm_magic_t; 67 68 /** 69 * Cliprect. 70 * 71 * \warning: If you change this structure, make sure you change 72 * XF86DRIClipRectRec in the server as well 73 * 74 * \note KW: Actually it's illegal to change either for 75 * backwards-compatibility reasons. 76 */ 77 struct drm_clip_rect { 78 unsigned short x1; 79 unsigned short y1; 80 unsigned short x2; 81 unsigned short y2; 82 }; 83 84 /** 85 * Drawable information. 86 */ 87 struct drm_drawable_info { 88 unsigned int num_rects; 89 struct drm_clip_rect *rects; 90 }; 91 92 /** 93 * Texture region, 94 */ 95 struct drm_tex_region { 96 unsigned char next; 97 unsigned char prev; 98 unsigned char in_use; 99 unsigned char padding; 100 unsigned int age; 101 }; 102 103 /** 104 * Hardware lock. 105 * 106 * The lock structure is a simple cache-line aligned integer. To avoid 107 * processor bus contention on a multiprocessor system, there should not be any 108 * other data stored in the same cache line. 109 */ 110 struct drm_hw_lock { 111 __volatile__ unsigned int lock; /**< lock variable */ 112 char padding[60]; /**< Pad to cache line */ 113 }; 114 115 /** 116 * DRM_IOCTL_VERSION ioctl argument type. 117 * 118 * \sa drmGetVersion(). 119 */ 120 struct drm_version { 121 int version_major; /**< Major version */ 122 int version_minor; /**< Minor version */ 123 int version_patchlevel; /**< Patch level */ 124 size_t name_len; /**< Length of name buffer */ 125 char __user *name; /**< Name of driver */ 126 size_t date_len; /**< Length of date buffer */ 127 char __user *date; /**< User-space buffer to hold date */ 128 size_t desc_len; /**< Length of desc buffer */ 129 char __user *desc; /**< User-space buffer to hold desc */ 130 }; 131 132 /** 133 * DRM_IOCTL_GET_UNIQUE ioctl argument type. 134 * 135 * \sa drmGetBusid() and drmSetBusId(). 136 */ 137 struct drm_unique { 138 size_t unique_len; /**< Length of unique */ 139 char __user *unique; /**< Unique name for driver instantiation */ 140 }; 141 142 struct drm_list { 143 int count; /**< Length of user-space structures */ 144 struct drm_version __user *version; 145 }; 146 147 struct drm_block { 148 int unused; 149 }; 150 151 /** 152 * DRM_IOCTL_CONTROL ioctl argument type. 153 * 154 * \sa drmCtlInstHandler() and drmCtlUninstHandler(). 155 */ 156 struct drm_control { 157 enum { 158 DRM_ADD_COMMAND, 159 DRM_RM_COMMAND, 160 DRM_INST_HANDLER, 161 DRM_UNINST_HANDLER 162 } func; 163 int irq; 164 }; 165 166 /** 167 * Type of memory to map. 168 */ 169 enum drm_map_type { 170 _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */ 171 _DRM_REGISTERS = 1, /**< no caching, no core dump */ 172 _DRM_SHM = 2, /**< shared, cached */ 173 _DRM_AGP = 3, /**< AGP/GART */ 174 _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */ 175 _DRM_CONSISTENT = 5, /**< Consistent memory for PCI DMA */ 176 _DRM_GEM = 6, /**< GEM object */ 177 }; 178 179 /** 180 * Memory mapping flags. 181 */ 182 enum drm_map_flags { 183 _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */ 184 _DRM_READ_ONLY = 0x02, 185 _DRM_LOCKED = 0x04, /**< shared, cached, locked */ 186 _DRM_KERNEL = 0x08, /**< kernel requires access */ 187 _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */ 188 _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */ 189 _DRM_REMOVABLE = 0x40, /**< Removable mapping */ 190 _DRM_DRIVER = 0x80 /**< Managed by driver */ 191 }; 192 193 struct drm_ctx_priv_map { 194 unsigned int ctx_id; /**< Context requesting private mapping */ 195 void *handle; /**< Handle of map */ 196 }; 197 198 /** 199 * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls 200 * argument type. 201 * 202 * \sa drmAddMap(). 203 */ 204 struct drm_map { 205 unsigned long offset; /**< Requested physical address (0 for SAREA)*/ 206 unsigned long size; /**< Requested physical size (bytes) */ 207 enum drm_map_type type; /**< Type of memory to map */ 208 enum drm_map_flags flags; /**< Flags */ 209 void *handle; /**< User-space: "Handle" to pass to mmap() */ 210 /**< Kernel-space: kernel-virtual address */ 211 int mtrr; /**< MTRR slot used */ 212 /* Private data */ 213 }; 214 215 /** 216 * DRM_IOCTL_GET_CLIENT ioctl argument type. 217 */ 218 struct drm_client { 219 int idx; /**< Which client desired? */ 220 int auth; /**< Is client authenticated? */ 221 unsigned long pid; /**< Process ID */ 222 unsigned long uid; /**< User ID */ 223 unsigned long magic; /**< Magic */ 224 unsigned long iocs; /**< Ioctl count */ 225 }; 226 227 enum drm_stat_type { 228 _DRM_STAT_LOCK, 229 _DRM_STAT_OPENS, 230 _DRM_STAT_CLOSES, 231 _DRM_STAT_IOCTLS, 232 _DRM_STAT_LOCKS, 233 _DRM_STAT_UNLOCKS, 234 _DRM_STAT_VALUE, /**< Generic value */ 235 _DRM_STAT_BYTE, /**< Generic byte counter (1024bytes/K) */ 236 _DRM_STAT_COUNT, /**< Generic non-byte counter (1000/k) */ 237 238 _DRM_STAT_IRQ, /**< IRQ */ 239 _DRM_STAT_PRIMARY, /**< Primary DMA bytes */ 240 _DRM_STAT_SECONDARY, /**< Secondary DMA bytes */ 241 _DRM_STAT_DMA, /**< DMA */ 242 _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */ 243 _DRM_STAT_MISSED /**< Missed DMA opportunity */ 244 /* Add to the *END* of the list */ 245 }; 246 247 /** 248 * DRM_IOCTL_GET_STATS ioctl argument type. 249 */ 250 struct drm_stats { 251 unsigned long count; 252 struct { 253 unsigned long value; 254 enum drm_stat_type type; 255 } data[15]; 256 }; 257 258 /** 259 * Hardware locking flags. 260 */ 261 enum drm_lock_flags { 262 _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */ 263 _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */ 264 _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */ 265 _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */ 266 /* These *HALT* flags aren't supported yet 267 -- they will be used to support the 268 full-screen DGA-like mode. */ 269 _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */ 270 _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */ 271 }; 272 273 /** 274 * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type. 275 * 276 * \sa drmGetLock() and drmUnlock(). 277 */ 278 struct drm_lock { 279 int context; 280 enum drm_lock_flags flags; 281 }; 282 283 /** 284 * DMA flags 285 * 286 * \warning 287 * These values \e must match xf86drm.h. 288 * 289 * \sa drm_dma. 290 */ 291 enum drm_dma_flags { 292 /* Flags for DMA buffer dispatch */ 293 _DRM_DMA_BLOCK = 0x01, /**< 294 * Block until buffer dispatched. 295 * 296 * \note The buffer may not yet have 297 * been processed by the hardware -- 298 * getting a hardware lock with the 299 * hardware quiescent will ensure 300 * that the buffer has been 301 * processed. 302 */ 303 _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */ 304 _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */ 305 306 /* Flags for DMA buffer request */ 307 _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */ 308 _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */ 309 _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */ 310 }; 311 312 /** 313 * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type. 314 * 315 * \sa drmAddBufs(). 316 */ 317 struct drm_buf_desc { 318 int count; /**< Number of buffers of this size */ 319 int size; /**< Size in bytes */ 320 int low_mark; /**< Low water mark */ 321 int high_mark; /**< High water mark */ 322 enum { 323 _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */ 324 _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */ 325 _DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */ 326 _DRM_FB_BUFFER = 0x08, /**< Buffer is in frame buffer */ 327 _DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */ 328 } flags; 329 unsigned long agp_start; /**< 330 * Start address of where the AGP buffers are 331 * in the AGP aperture 332 */ 333 }; 334 335 /** 336 * DRM_IOCTL_INFO_BUFS ioctl argument type. 337 */ 338 struct drm_buf_info { 339 int count; /**< Entries in list */ 340 struct drm_buf_desc __user *list; 341 }; 342 343 /** 344 * DRM_IOCTL_FREE_BUFS ioctl argument type. 345 */ 346 struct drm_buf_free { 347 int count; 348 int __user *list; 349 }; 350 351 /** 352 * Buffer information 353 * 354 * \sa drm_buf_map. 355 */ 356 struct drm_buf_pub { 357 int idx; /**< Index into the master buffer list */ 358 int total; /**< Buffer size */ 359 int used; /**< Amount of buffer in use (for DMA) */ 360 void __user *address; /**< Address of buffer */ 361 }; 362 363 /** 364 * DRM_IOCTL_MAP_BUFS ioctl argument type. 365 */ 366 struct drm_buf_map { 367 int count; /**< Length of the buffer list */ 368 void __user *virtual; /**< Mmap'd area in user-virtual */ 369 struct drm_buf_pub __user *list; /**< Buffer information */ 370 }; 371 372 /** 373 * DRM_IOCTL_DMA ioctl argument type. 374 * 375 * Indices here refer to the offset into the buffer list in drm_buf_get. 376 * 377 * \sa drmDMA(). 378 */ 379 struct drm_dma { 380 int context; /**< Context handle */ 381 int send_count; /**< Number of buffers to send */ 382 int __user *send_indices; /**< List of handles to buffers */ 383 int __user *send_sizes; /**< Lengths of data to send */ 384 enum drm_dma_flags flags; /**< Flags */ 385 int request_count; /**< Number of buffers requested */ 386 int request_size; /**< Desired size for buffers */ 387 int __user *request_indices; /**< Buffer information */ 388 int __user *request_sizes; 389 int granted_count; /**< Number of buffers granted */ 390 }; 391 392 enum drm_ctx_flags { 393 _DRM_CONTEXT_PRESERVED = 0x01, 394 _DRM_CONTEXT_2DONLY = 0x02 395 }; 396 397 /** 398 * DRM_IOCTL_ADD_CTX ioctl argument type. 399 * 400 * \sa drmCreateContext() and drmDestroyContext(). 401 */ 402 struct drm_ctx { 403 drm_context_t handle; 404 enum drm_ctx_flags flags; 405 }; 406 407 /** 408 * DRM_IOCTL_RES_CTX ioctl argument type. 409 */ 410 struct drm_ctx_res { 411 int count; 412 struct drm_ctx __user *contexts; 413 }; 414 415 /** 416 * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type. 417 */ 418 struct drm_draw { 419 drm_drawable_t handle; 420 }; 421 422 /** 423 * DRM_IOCTL_UPDATE_DRAW ioctl argument type. 424 */ 425 typedef enum { 426 DRM_DRAWABLE_CLIPRECTS, 427 } drm_drawable_info_type_t; 428 429 struct drm_update_draw { 430 drm_drawable_t handle; 431 unsigned int type; 432 unsigned int num; 433 unsigned long long data; 434 }; 435 436 /** 437 * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type. 438 */ 439 struct drm_auth { 440 drm_magic_t magic; 441 }; 442 443 /** 444 * DRM_IOCTL_IRQ_BUSID ioctl argument type. 445 * 446 * \sa drmGetInterruptFromBusID(). 447 */ 448 struct drm_irq_busid { 449 int irq; /**< IRQ number */ 450 int busnum; /**< bus number */ 451 int devnum; /**< device number */ 452 int funcnum; /**< function number */ 453 }; 454 455 enum drm_vblank_seq_type { 456 _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */ 457 _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */ 458 _DRM_VBLANK_FLIP = 0x8000000, /**< Scheduled buffer swap should flip */ 459 _DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */ 460 _DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */ 461 _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking, unsupported */ 462 }; 463 464 #define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE) 465 #define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_SIGNAL | _DRM_VBLANK_SECONDARY | \ 466 _DRM_VBLANK_NEXTONMISS) 467 468 struct drm_wait_vblank_request { 469 enum drm_vblank_seq_type type; 470 unsigned int sequence; 471 unsigned long signal; 472 }; 473 474 struct drm_wait_vblank_reply { 475 enum drm_vblank_seq_type type; 476 unsigned int sequence; 477 long tval_sec; 478 long tval_usec; 479 }; 480 481 /** 482 * DRM_IOCTL_WAIT_VBLANK ioctl argument type. 483 * 484 * \sa drmWaitVBlank(). 485 */ 486 union drm_wait_vblank { 487 struct drm_wait_vblank_request request; 488 struct drm_wait_vblank_reply reply; 489 }; 490 491 #define _DRM_PRE_MODESET 1 492 #define _DRM_POST_MODESET 2 493 494 /** 495 * DRM_IOCTL_MODESET_CTL ioctl argument type 496 * 497 * \sa drmModesetCtl(). 498 */ 499 struct drm_modeset_ctl { 500 uint32_t crtc; 501 uint32_t cmd; 502 }; 503 504 /** 505 * DRM_IOCTL_AGP_ENABLE ioctl argument type. 506 * 507 * \sa drmAgpEnable(). 508 */ 509 struct drm_agp_mode { 510 unsigned long mode; /**< AGP mode */ 511 }; 512 513 /** 514 * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type. 515 * 516 * \sa drmAgpAlloc() and drmAgpFree(). 517 */ 518 struct drm_agp_buffer { 519 unsigned long size; /**< In bytes -- will round to page boundary */ 520 unsigned long handle; /**< Used for binding / unbinding */ 521 unsigned long type; /**< Type of memory to allocate */ 522 unsigned long physical; /**< Physical used by i810 */ 523 }; 524 525 /** 526 * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type. 527 * 528 * \sa drmAgpBind() and drmAgpUnbind(). 529 */ 530 struct drm_agp_binding { 531 unsigned long handle; /**< From drm_agp_buffer */ 532 unsigned long offset; /**< In bytes -- will round to page boundary */ 533 }; 534 535 /** 536 * DRM_IOCTL_AGP_INFO ioctl argument type. 537 * 538 * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(), 539 * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(), 540 * drmAgpVendorId() and drmAgpDeviceId(). 541 */ 542 struct drm_agp_info { 543 int agp_version_major; 544 int agp_version_minor; 545 unsigned long mode; 546 unsigned long aperture_base; /* physical address */ 547 unsigned long aperture_size; /* bytes */ 548 unsigned long memory_allowed; /* bytes */ 549 unsigned long memory_used; 550 551 /* PCI information */ 552 unsigned short id_vendor; 553 unsigned short id_device; 554 }; 555 556 /** 557 * DRM_IOCTL_SG_ALLOC ioctl argument type. 558 */ 559 struct drm_scatter_gather { 560 unsigned long size; /**< In bytes -- will round to page boundary */ 561 unsigned long handle; /**< Used for mapping / unmapping */ 562 }; 563 564 /** 565 * DRM_IOCTL_SET_VERSION ioctl argument type. 566 */ 567 struct drm_set_version { 568 int drm_di_major; 569 int drm_di_minor; 570 int drm_dd_major; 571 int drm_dd_minor; 572 }; 573 574 /** DRM_IOCTL_GEM_CLOSE ioctl argument type */ 575 struct drm_gem_close { 576 /** Handle of the object to be closed. */ 577 uint32_t handle; 578 uint32_t pad; 579 }; 580 581 /** DRM_IOCTL_GEM_FLINK ioctl argument type */ 582 struct drm_gem_flink { 583 /** Handle for the object being named */ 584 uint32_t handle; 585 586 /** Returned global name */ 587 uint32_t name; 588 }; 589 590 /** DRM_IOCTL_GEM_OPEN ioctl argument type */ 591 struct drm_gem_open { 592 /** Name of object being opened */ 593 uint32_t name; 594 595 /** Returned handle for the object */ 596 uint32_t handle; 597 598 /** Returned size of the object */ 599 uint64_t size; 600 }; 601 602 #include "drm_mode.h" 603 604 #define DRM_IOCTL_BASE 'd' 605 #define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr) 606 #define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type) 607 #define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type) 608 #define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type) 609 610 #define DRM_IOCTL_VERSION DRM_IOWR(0x00, struct drm_version) 611 #define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, struct drm_unique) 612 #define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, struct drm_auth) 613 #define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, struct drm_irq_busid) 614 #define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, struct drm_map) 615 #define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, struct drm_client) 616 #define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, struct drm_stats) 617 #define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, struct drm_set_version) 618 #define DRM_IOCTL_MODESET_CTL DRM_IOW(0x08, struct drm_modeset_ctl) 619 #define DRM_IOCTL_GEM_CLOSE DRM_IOW (0x09, struct drm_gem_close) 620 #define DRM_IOCTL_GEM_FLINK DRM_IOWR(0x0a, struct drm_gem_flink) 621 #define DRM_IOCTL_GEM_OPEN DRM_IOWR(0x0b, struct drm_gem_open) 622 623 #define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, struct drm_unique) 624 #define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, struct drm_auth) 625 #define DRM_IOCTL_BLOCK DRM_IOWR(0x12, struct drm_block) 626 #define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, struct drm_block) 627 #define DRM_IOCTL_CONTROL DRM_IOW( 0x14, struct drm_control) 628 #define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, struct drm_map) 629 #define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, struct drm_buf_desc) 630 #define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, struct drm_buf_desc) 631 #define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, struct drm_buf_info) 632 #define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, struct drm_buf_map) 633 #define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, struct drm_buf_free) 634 635 #define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, struct drm_map) 636 637 #define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, struct drm_ctx_priv_map) 638 #define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, struct drm_ctx_priv_map) 639 640 #define DRM_IOCTL_SET_MASTER DRM_IO(0x1e) 641 #define DRM_IOCTL_DROP_MASTER DRM_IO(0x1f) 642 643 #define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, struct drm_ctx) 644 #define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, struct drm_ctx) 645 #define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, struct drm_ctx) 646 #define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, struct drm_ctx) 647 #define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, struct drm_ctx) 648 #define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, struct drm_ctx) 649 #define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, struct drm_ctx_res) 650 #define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, struct drm_draw) 651 #define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, struct drm_draw) 652 #define DRM_IOCTL_DMA DRM_IOWR(0x29, struct drm_dma) 653 #define DRM_IOCTL_LOCK DRM_IOW( 0x2a, struct drm_lock) 654 #define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, struct drm_lock) 655 #define DRM_IOCTL_FINISH DRM_IOW( 0x2c, struct drm_lock) 656 657 #define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30) 658 #define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31) 659 #define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, struct drm_agp_mode) 660 #define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, struct drm_agp_info) 661 #define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, struct drm_agp_buffer) 662 #define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, struct drm_agp_buffer) 663 #define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding) 664 #define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding) 665 666 #define DRM_IOCTL_SG_ALLOC DRM_IOWR(0x38, struct drm_scatter_gather) 667 #define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather) 668 669 #define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank) 670 671 #define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw) 672 673 #define DRM_IOCTL_MODE_GETRESOURCES DRM_IOWR(0xA0, struct drm_mode_card_res) 674 #define DRM_IOCTL_MODE_GETCRTC DRM_IOWR(0xA1, struct drm_mode_crtc) 675 #define DRM_IOCTL_MODE_SETCRTC DRM_IOWR(0xA2, struct drm_mode_crtc) 676 #define DRM_IOCTL_MODE_CURSOR DRM_IOWR(0xA3, struct drm_mode_cursor) 677 #define DRM_IOCTL_MODE_GETGAMMA DRM_IOWR(0xA4, struct drm_mode_crtc_lut) 678 #define DRM_IOCTL_MODE_SETGAMMA DRM_IOWR(0xA5, struct drm_mode_crtc_lut) 679 #define DRM_IOCTL_MODE_GETENCODER DRM_IOWR(0xA6, struct drm_mode_get_encoder) 680 #define DRM_IOCTL_MODE_GETCONNECTOR DRM_IOWR(0xA7, struct drm_mode_get_connector) 681 #define DRM_IOCTL_MODE_ATTACHMODE DRM_IOWR(0xA8, struct drm_mode_mode_cmd) 682 #define DRM_IOCTL_MODE_DETACHMODE DRM_IOWR(0xA9, struct drm_mode_mode_cmd) 683 684 #define DRM_IOCTL_MODE_GETPROPERTY DRM_IOWR(0xAA, struct drm_mode_get_property) 685 #define DRM_IOCTL_MODE_SETPROPERTY DRM_IOWR(0xAB, struct drm_mode_connector_set_property) 686 #define DRM_IOCTL_MODE_GETPROPBLOB DRM_IOWR(0xAC, struct drm_mode_get_blob) 687 #define DRM_IOCTL_MODE_GETFB DRM_IOWR(0xAD, struct drm_mode_fb_cmd) 688 #define DRM_IOCTL_MODE_ADDFB DRM_IOWR(0xAE, struct drm_mode_fb_cmd) 689 #define DRM_IOCTL_MODE_RMFB DRM_IOWR(0xAF, unsigned int) 690 691 /** 692 * Device specific ioctls should only be in their respective headers 693 * The device specific ioctl range is from 0x40 to 0x99. 694 * Generic IOCTLS restart at 0xA0. 695 * 696 * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and 697 * drmCommandReadWrite(). 698 */ 699 #define DRM_COMMAND_BASE 0x40 700 #define DRM_COMMAND_END 0xA0 701 702 /* typedef area */ 703 #ifndef __KERNEL__ 704 typedef struct drm_clip_rect drm_clip_rect_t; 705 typedef struct drm_drawable_info drm_drawable_info_t; 706 typedef struct drm_tex_region drm_tex_region_t; 707 typedef struct drm_hw_lock drm_hw_lock_t; 708 typedef struct drm_version drm_version_t; 709 typedef struct drm_unique drm_unique_t; 710 typedef struct drm_list drm_list_t; 711 typedef struct drm_block drm_block_t; 712 typedef struct drm_control drm_control_t; 713 typedef enum drm_map_type drm_map_type_t; 714 typedef enum drm_map_flags drm_map_flags_t; 715 typedef struct drm_ctx_priv_map drm_ctx_priv_map_t; 716 typedef struct drm_map drm_map_t; 717 typedef struct drm_client drm_client_t; 718 typedef enum drm_stat_type drm_stat_type_t; 719 typedef struct drm_stats drm_stats_t; 720 typedef enum drm_lock_flags drm_lock_flags_t; 721 typedef struct drm_lock drm_lock_t; 722 typedef enum drm_dma_flags drm_dma_flags_t; 723 typedef struct drm_buf_desc drm_buf_desc_t; 724 typedef struct drm_buf_info drm_buf_info_t; 725 typedef struct drm_buf_free drm_buf_free_t; 726 typedef struct drm_buf_pub drm_buf_pub_t; 727 typedef struct drm_buf_map drm_buf_map_t; 728 typedef struct drm_dma drm_dma_t; 729 typedef union drm_wait_vblank drm_wait_vblank_t; 730 typedef struct drm_agp_mode drm_agp_mode_t; 731 typedef enum drm_ctx_flags drm_ctx_flags_t; 732 typedef struct drm_ctx drm_ctx_t; 733 typedef struct drm_ctx_res drm_ctx_res_t; 734 typedef struct drm_draw drm_draw_t; 735 typedef struct drm_update_draw drm_update_draw_t; 736 typedef struct drm_auth drm_auth_t; 737 typedef struct drm_irq_busid drm_irq_busid_t; 738 typedef enum drm_vblank_seq_type drm_vblank_seq_type_t; 739 740 typedef struct drm_agp_buffer drm_agp_buffer_t; 741 typedef struct drm_agp_binding drm_agp_binding_t; 742 typedef struct drm_agp_info drm_agp_info_t; 743 typedef struct drm_scatter_gather drm_scatter_gather_t; 744 typedef struct drm_set_version drm_set_version_t; 745 #endif 746 747 #endif 748