1 /*
2 * Defines, structures, APIs for edac_core module
3 *
4 * (C) 2007 Linux Networx (http://lnxi.com)
5 * This file may be distributed under the terms of the
6 * GNU General Public License.
7 *
8 * Written by Thayne Harbaugh
9 * Based on work by Dan Hollis <goemon at anime dot net> and others.
10 * http://www.anime.net/~goemon/linux-ecc/
11 *
12 * NMI handling support added by
13 * Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com>
14 *
15 * Refactored for multi-source files:
16 * Doug Thompson <norsk5@xmission.com>
17 *
18 */
19
20 #ifndef _EDAC_CORE_H_
21 #define _EDAC_CORE_H_
22
23 #include <linux/kernel.h>
24 #include <linux/types.h>
25 #include <linux/module.h>
26 #include <linux/spinlock.h>
27 #include <linux/smp.h>
28 #include <linux/pci.h>
29 #include <linux/time.h>
30 #include <linux/nmi.h>
31 #include <linux/rcupdate.h>
32 #include <linux/completion.h>
33 #include <linux/kobject.h>
34 #include <linux/platform_device.h>
35 #include <linux/sysdev.h>
36 #include <linux/workqueue.h>
37
38 #define EDAC_MC_LABEL_LEN 31
39 #define EDAC_DEVICE_NAME_LEN 31
40 #define EDAC_ATTRIB_VALUE_LEN 15
41 #define MC_PROC_NAME_MAX_LEN 7
42
43 #if PAGE_SHIFT < 20
44 #define PAGES_TO_MiB( pages ) ( ( pages ) >> ( 20 - PAGE_SHIFT ) )
45 #else /* PAGE_SHIFT > 20 */
46 #define PAGES_TO_MiB( pages ) ( ( pages ) << ( PAGE_SHIFT - 20 ) )
47 #endif
48
49 #define edac_printk(level, prefix, fmt, arg...) \
50 printk(level "EDAC " prefix ": " fmt, ##arg)
51
52 #define edac_mc_printk(mci, level, fmt, arg...) \
53 printk(level "EDAC MC%d: " fmt, mci->mc_idx, ##arg)
54
55 #define edac_mc_chipset_printk(mci, level, prefix, fmt, arg...) \
56 printk(level "EDAC " prefix " MC%d: " fmt, mci->mc_idx, ##arg)
57
58 /* edac_device printk */
59 #define edac_device_printk(ctl, level, fmt, arg...) \
60 printk(level "EDAC DEVICE%d: " fmt, ctl->dev_idx, ##arg)
61
62 /* edac_pci printk */
63 #define edac_pci_printk(ctl, level, fmt, arg...) \
64 printk(level "EDAC PCI%d: " fmt, ctl->pci_idx, ##arg)
65
66 /* prefixes for edac_printk() and edac_mc_printk() */
67 #define EDAC_MC "MC"
68 #define EDAC_PCI "PCI"
69 #define EDAC_DEBUG "DEBUG"
70
71 #ifdef CONFIG_EDAC_DEBUG
72 extern int edac_debug_level;
73
74 #define edac_debug_printk(level, fmt, arg...) \
75 do { \
76 if (level <= edac_debug_level) \
77 edac_printk(KERN_DEBUG, EDAC_DEBUG, fmt, ##arg); \
78 } while(0)
79
80 #define debugf0( ... ) edac_debug_printk(0, __VA_ARGS__ )
81 #define debugf1( ... ) edac_debug_printk(1, __VA_ARGS__ )
82 #define debugf2( ... ) edac_debug_printk(2, __VA_ARGS__ )
83 #define debugf3( ... ) edac_debug_printk(3, __VA_ARGS__ )
84 #define debugf4( ... ) edac_debug_printk(4, __VA_ARGS__ )
85
86 #else /* !CONFIG_EDAC_DEBUG */
87
88 #define debugf0( ... )
89 #define debugf1( ... )
90 #define debugf2( ... )
91 #define debugf3( ... )
92 #define debugf4( ... )
93
94 #endif /* !CONFIG_EDAC_DEBUG */
95
96 #define PCI_VEND_DEV(vend, dev) PCI_VENDOR_ID_ ## vend, \
97 PCI_DEVICE_ID_ ## vend ## _ ## dev
98
99 #define edac_dev_name(dev) (dev)->dev_name
100
101 /* memory devices */
102 enum dev_type {
103 DEV_UNKNOWN = 0,
104 DEV_X1,
105 DEV_X2,
106 DEV_X4,
107 DEV_X8,
108 DEV_X16,
109 DEV_X32, /* Do these parts exist? */
110 DEV_X64 /* Do these parts exist? */
111 };
112
113 #define DEV_FLAG_UNKNOWN BIT(DEV_UNKNOWN)
114 #define DEV_FLAG_X1 BIT(DEV_X1)
115 #define DEV_FLAG_X2 BIT(DEV_X2)
116 #define DEV_FLAG_X4 BIT(DEV_X4)
117 #define DEV_FLAG_X8 BIT(DEV_X8)
118 #define DEV_FLAG_X16 BIT(DEV_X16)
119 #define DEV_FLAG_X32 BIT(DEV_X32)
120 #define DEV_FLAG_X64 BIT(DEV_X64)
121
122 /* memory types */
123 enum mem_type {
124 MEM_EMPTY = 0, /* Empty csrow */
125 MEM_RESERVED, /* Reserved csrow type */
126 MEM_UNKNOWN, /* Unknown csrow type */
127 MEM_FPM, /* Fast page mode */
128 MEM_EDO, /* Extended data out */
129 MEM_BEDO, /* Burst Extended data out */
130 MEM_SDR, /* Single data rate SDRAM */
131 MEM_RDR, /* Registered single data rate SDRAM */
132 MEM_DDR, /* Double data rate SDRAM */
133 MEM_RDDR, /* Registered Double data rate SDRAM */
134 MEM_RMBS, /* Rambus DRAM */
135 MEM_DDR2, /* DDR2 RAM */
136 MEM_FB_DDR2, /* fully buffered DDR2 */
137 MEM_RDDR2, /* Registered DDR2 RAM */
138 MEM_XDR, /* Rambus XDR */
139 };
140
141 #define MEM_FLAG_EMPTY BIT(MEM_EMPTY)
142 #define MEM_FLAG_RESERVED BIT(MEM_RESERVED)
143 #define MEM_FLAG_UNKNOWN BIT(MEM_UNKNOWN)
144 #define MEM_FLAG_FPM BIT(MEM_FPM)
145 #define MEM_FLAG_EDO BIT(MEM_EDO)
146 #define MEM_FLAG_BEDO BIT(MEM_BEDO)
147 #define MEM_FLAG_SDR BIT(MEM_SDR)
148 #define MEM_FLAG_RDR BIT(MEM_RDR)
149 #define MEM_FLAG_DDR BIT(MEM_DDR)
150 #define MEM_FLAG_RDDR BIT(MEM_RDDR)
151 #define MEM_FLAG_RMBS BIT(MEM_RMBS)
152 #define MEM_FLAG_DDR2 BIT(MEM_DDR2)
153 #define MEM_FLAG_FB_DDR2 BIT(MEM_FB_DDR2)
154 #define MEM_FLAG_RDDR2 BIT(MEM_RDDR2)
155 #define MEM_FLAG_XDR BIT(MEM_XDR)
156
157 /* chipset Error Detection and Correction capabilities and mode */
158 enum edac_type {
159 EDAC_UNKNOWN = 0, /* Unknown if ECC is available */
160 EDAC_NONE, /* Doesnt support ECC */
161 EDAC_RESERVED, /* Reserved ECC type */
162 EDAC_PARITY, /* Detects parity errors */
163 EDAC_EC, /* Error Checking - no correction */
164 EDAC_SECDED, /* Single bit error correction, Double detection */
165 EDAC_S2ECD2ED, /* Chipkill x2 devices - do these exist? */
166 EDAC_S4ECD4ED, /* Chipkill x4 devices */
167 EDAC_S8ECD8ED, /* Chipkill x8 devices */
168 EDAC_S16ECD16ED, /* Chipkill x16 devices */
169 };
170
171 #define EDAC_FLAG_UNKNOWN BIT(EDAC_UNKNOWN)
172 #define EDAC_FLAG_NONE BIT(EDAC_NONE)
173 #define EDAC_FLAG_PARITY BIT(EDAC_PARITY)
174 #define EDAC_FLAG_EC BIT(EDAC_EC)
175 #define EDAC_FLAG_SECDED BIT(EDAC_SECDED)
176 #define EDAC_FLAG_S2ECD2ED BIT(EDAC_S2ECD2ED)
177 #define EDAC_FLAG_S4ECD4ED BIT(EDAC_S4ECD4ED)
178 #define EDAC_FLAG_S8ECD8ED BIT(EDAC_S8ECD8ED)
179 #define EDAC_FLAG_S16ECD16ED BIT(EDAC_S16ECD16ED)
180
181 /* scrubbing capabilities */
182 enum scrub_type {
183 SCRUB_UNKNOWN = 0, /* Unknown if scrubber is available */
184 SCRUB_NONE, /* No scrubber */
185 SCRUB_SW_PROG, /* SW progressive (sequential) scrubbing */
186 SCRUB_SW_SRC, /* Software scrub only errors */
187 SCRUB_SW_PROG_SRC, /* Progressive software scrub from an error */
188 SCRUB_SW_TUNABLE, /* Software scrub frequency is tunable */
189 SCRUB_HW_PROG, /* HW progressive (sequential) scrubbing */
190 SCRUB_HW_SRC, /* Hardware scrub only errors */
191 SCRUB_HW_PROG_SRC, /* Progressive hardware scrub from an error */
192 SCRUB_HW_TUNABLE /* Hardware scrub frequency is tunable */
193 };
194
195 #define SCRUB_FLAG_SW_PROG BIT(SCRUB_SW_PROG)
196 #define SCRUB_FLAG_SW_SRC BIT(SCRUB_SW_SRC)
197 #define SCRUB_FLAG_SW_PROG_SRC BIT(SCRUB_SW_PROG_SRC)
198 #define SCRUB_FLAG_SW_TUN BIT(SCRUB_SW_SCRUB_TUNABLE)
199 #define SCRUB_FLAG_HW_PROG BIT(SCRUB_HW_PROG)
200 #define SCRUB_FLAG_HW_SRC BIT(SCRUB_HW_SRC)
201 #define SCRUB_FLAG_HW_PROG_SRC BIT(SCRUB_HW_PROG_SRC)
202 #define SCRUB_FLAG_HW_TUN BIT(SCRUB_HW_TUNABLE)
203
204 /* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */
205
206 /* EDAC internal operation states */
207 #define OP_ALLOC 0x100
208 #define OP_RUNNING_POLL 0x201
209 #define OP_RUNNING_INTERRUPT 0x202
210 #define OP_RUNNING_POLL_INTR 0x203
211 #define OP_OFFLINE 0x300
212
213 /*
214 * There are several things to be aware of that aren't at all obvious:
215 *
216 *
217 * SOCKETS, SOCKET SETS, BANKS, ROWS, CHIP-SELECT ROWS, CHANNELS, etc..
218 *
219 * These are some of the many terms that are thrown about that don't always
220 * mean what people think they mean (Inconceivable!). In the interest of
221 * creating a common ground for discussion, terms and their definitions
222 * will be established.
223 *
224 * Memory devices: The individual chip on a memory stick. These devices
225 * commonly output 4 and 8 bits each. Grouping several
226 * of these in parallel provides 64 bits which is common
227 * for a memory stick.
228 *
229 * Memory Stick: A printed circuit board that agregates multiple
230 * memory devices in parallel. This is the atomic
231 * memory component that is purchaseable by Joe consumer
232 * and loaded into a memory socket.
233 *
234 * Socket: A physical connector on the motherboard that accepts
235 * a single memory stick.
236 *
237 * Channel: Set of memory devices on a memory stick that must be
238 * grouped in parallel with one or more additional
239 * channels from other memory sticks. This parallel
240 * grouping of the output from multiple channels are
241 * necessary for the smallest granularity of memory access.
242 * Some memory controllers are capable of single channel -
243 * which means that memory sticks can be loaded
244 * individually. Other memory controllers are only
245 * capable of dual channel - which means that memory
246 * sticks must be loaded as pairs (see "socket set").
247 *
248 * Chip-select row: All of the memory devices that are selected together.
249 * for a single, minimum grain of memory access.
250 * This selects all of the parallel memory devices across
251 * all of the parallel channels. Common chip-select rows
252 * for single channel are 64 bits, for dual channel 128
253 * bits.
254 *
255 * Single-Ranked stick: A Single-ranked stick has 1 chip-select row of memmory.
256 * Motherboards commonly drive two chip-select pins to
257 * a memory stick. A single-ranked stick, will occupy
258 * only one of those rows. The other will be unused.
259 *
260 * Double-Ranked stick: A double-ranked stick has two chip-select rows which
261 * access different sets of memory devices. The two
262 * rows cannot be accessed concurrently.
263 *
264 * Double-sided stick: DEPRECATED TERM, see Double-Ranked stick.
265 * A double-sided stick has two chip-select rows which
266 * access different sets of memory devices. The two
267 * rows cannot be accessed concurrently. "Double-sided"
268 * is irrespective of the memory devices being mounted
269 * on both sides of the memory stick.
270 *
271 * Socket set: All of the memory sticks that are required for for
272 * a single memory access or all of the memory sticks
273 * spanned by a chip-select row. A single socket set
274 * has two chip-select rows and if double-sided sticks
275 * are used these will occupy those chip-select rows.
276 *
277 * Bank: This term is avoided because it is unclear when
278 * needing to distinguish between chip-select rows and
279 * socket sets.
280 *
281 * Controller pages:
282 *
283 * Physical pages:
284 *
285 * Virtual pages:
286 *
287 *
288 * STRUCTURE ORGANIZATION AND CHOICES
289 *
290 *
291 *
292 * PS - I enjoyed writing all that about as much as you enjoyed reading it.
293 */
294
295 struct channel_info {
296 int chan_idx; /* channel index */
297 u32 ce_count; /* Correctable Errors for this CHANNEL */
298 char label[EDAC_MC_LABEL_LEN + 1]; /* DIMM label on motherboard */
299 struct csrow_info *csrow; /* the parent */
300 };
301
302 struct csrow_info {
303 unsigned long first_page; /* first page number in dimm */
304 unsigned long last_page; /* last page number in dimm */
305 unsigned long page_mask; /* used for interleaving -
306 * 0UL for non intlv
307 */
308 u32 nr_pages; /* number of pages in csrow */
309 u32 grain; /* granularity of reported error in bytes */
310 int csrow_idx; /* the chip-select row */
311 enum dev_type dtype; /* memory device type */
312 u32 ue_count; /* Uncorrectable Errors for this csrow */
313 u32 ce_count; /* Correctable Errors for this csrow */
314 enum mem_type mtype; /* memory csrow type */
315 enum edac_type edac_mode; /* EDAC mode for this csrow */
316 struct mem_ctl_info *mci; /* the parent */
317
318 struct kobject kobj; /* sysfs kobject for this csrow */
319
320 /* channel information for this csrow */
321 u32 nr_channels;
322 struct channel_info *channels;
323 };
324
325 /* mcidev_sysfs_attribute structure
326 * used for driver sysfs attributes and in mem_ctl_info
327 * sysfs top level entries
328 */
329 struct mcidev_sysfs_attribute {
330 struct attribute attr;
331 ssize_t (*show)(struct mem_ctl_info *,char *);
332 ssize_t (*store)(struct mem_ctl_info *, const char *,size_t);
333 };
334
335 /* MEMORY controller information structure
336 */
337 struct mem_ctl_info {
338 struct list_head link; /* for global list of mem_ctl_info structs */
339
340 struct module *owner; /* Module owner of this control struct */
341
342 unsigned long mtype_cap; /* memory types supported by mc */
343 unsigned long edac_ctl_cap; /* Mem controller EDAC capabilities */
344 unsigned long edac_cap; /* configuration capabilities - this is
345 * closely related to edac_ctl_cap. The
346 * difference is that the controller may be
347 * capable of s4ecd4ed which would be listed
348 * in edac_ctl_cap, but if channels aren't
349 * capable of s4ecd4ed then the edac_cap would
350 * not have that capability.
351 */
352 unsigned long scrub_cap; /* chipset scrub capabilities */
353 enum scrub_type scrub_mode; /* current scrub mode */
354
355 /* Translates sdram memory scrub rate given in bytes/sec to the
356 internal representation and configures whatever else needs
357 to be configured.
358 */
359 int (*set_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 * bw);
360
361 /* Get the current sdram memory scrub rate from the internal
362 representation and converts it to the closest matching
363 bandwith in bytes/sec.
364 */
365 int (*get_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 * bw);
366
367
368 /* pointer to edac checking routine */
369 void (*edac_check) (struct mem_ctl_info * mci);
370
371 /*
372 * Remaps memory pages: controller pages to physical pages.
373 * For most MC's, this will be NULL.
374 */
375 /* FIXME - why not send the phys page to begin with? */
376 unsigned long (*ctl_page_to_phys) (struct mem_ctl_info * mci,
377 unsigned long page);
378 int mc_idx;
379 int nr_csrows;
380 struct csrow_info *csrows;
381 /*
382 * FIXME - what about controllers on other busses? - IDs must be
383 * unique. dev pointer should be sufficiently unique, but
384 * BUS:SLOT.FUNC numbers may not be unique.
385 */
386 struct device *dev;
387 const char *mod_name;
388 const char *mod_ver;
389 const char *ctl_name;
390 const char *dev_name;
391 char proc_name[MC_PROC_NAME_MAX_LEN + 1];
392 void *pvt_info;
393 u32 ue_noinfo_count; /* Uncorrectable Errors w/o info */
394 u32 ce_noinfo_count; /* Correctable Errors w/o info */
395 u32 ue_count; /* Total Uncorrectable Errors for this MC */
396 u32 ce_count; /* Total Correctable Errors for this MC */
397 unsigned long start_time; /* mci load start time (in jiffies) */
398
399 /* this stuff is for safe removal of mc devices from global list while
400 * NMI handlers may be traversing list
401 */
402 struct rcu_head rcu;
403 struct completion complete;
404
405 /* edac sysfs device control */
406 struct kobject edac_mci_kobj;
407
408 /* Additional top controller level attributes, but specified
409 * by the low level driver.
410 *
411 * Set by the low level driver to provide attributes at the
412 * controller level, same level as 'ue_count' and 'ce_count' above.
413 * An array of structures, NULL terminated
414 *
415 * If attributes are desired, then set to array of attributes
416 * If no attributes are desired, leave NULL
417 */
418 struct mcidev_sysfs_attribute *mc_driver_sysfs_attributes;
419
420 /* work struct for this MC */
421 struct delayed_work work;
422
423 /* the internal state of this controller instance */
424 int op_state;
425 };
426
427 /*
428 * The following are the structures to provide for a generic
429 * or abstract 'edac_device'. This set of structures and the
430 * code that implements the APIs for the same, provide for
431 * registering EDAC type devices which are NOT standard memory.
432 *
433 * CPU caches (L1 and L2)
434 * DMA engines
435 * Core CPU swithces
436 * Fabric switch units
437 * PCIe interface controllers
438 * other EDAC/ECC type devices that can be monitored for
439 * errors, etc.
440 *
441 * It allows for a 2 level set of hiearchry. For example:
442 *
443 * cache could be composed of L1, L2 and L3 levels of cache.
444 * Each CPU core would have its own L1 cache, while sharing
445 * L2 and maybe L3 caches.
446 *
447 * View them arranged, via the sysfs presentation:
448 * /sys/devices/system/edac/..
449 *
450 * mc/ <existing memory device directory>
451 * cpu/cpu0/.. <L1 and L2 block directory>
452 * /L1-cache/ce_count
453 * /ue_count
454 * /L2-cache/ce_count
455 * /ue_count
456 * cpu/cpu1/.. <L1 and L2 block directory>
457 * /L1-cache/ce_count
458 * /ue_count
459 * /L2-cache/ce_count
460 * /ue_count
461 * ...
462 *
463 * the L1 and L2 directories would be "edac_device_block's"
464 */
465
466 struct edac_device_counter {
467 u32 ue_count;
468 u32 ce_count;
469 };
470
471 /* forward reference */
472 struct edac_device_ctl_info;
473 struct edac_device_block;
474
475 /* edac_dev_sysfs_attribute structure
476 * used for driver sysfs attributes in mem_ctl_info
477 * for extra controls and attributes:
478 * like high level error Injection controls
479 */
480 struct edac_dev_sysfs_attribute {
481 struct attribute attr;
482 ssize_t (*show)(struct edac_device_ctl_info *, char *);
483 ssize_t (*store)(struct edac_device_ctl_info *, const char *, size_t);
484 };
485
486 /* edac_dev_sysfs_block_attribute structure
487 *
488 * used in leaf 'block' nodes for adding controls/attributes
489 *
490 * each block in each instance of the containing control structure
491 * can have an array of the following. The show and store functions
492 * will be filled in with the show/store function in the
493 * low level driver.
494 *
495 * The 'value' field will be the actual value field used for
496 * counting
497 */
498 struct edac_dev_sysfs_block_attribute {
499 struct attribute attr;
500 ssize_t (*show)(struct kobject *, struct attribute *, char *);
501 ssize_t (*store)(struct kobject *, struct attribute *,
502 const char *, size_t);
503 struct edac_device_block *block;
504
505 unsigned int value;
506 };
507
508 /* device block control structure */
509 struct edac_device_block {
510 struct edac_device_instance *instance; /* Up Pointer */
511 char name[EDAC_DEVICE_NAME_LEN + 1];
512
513 struct edac_device_counter counters; /* basic UE and CE counters */
514
515 int nr_attribs; /* how many attributes */
516
517 /* this block's attributes, could be NULL */
518 struct edac_dev_sysfs_block_attribute *block_attributes;
519
520 /* edac sysfs device control */
521 struct kobject kobj;
522 };
523
524 /* device instance control structure */
525 struct edac_device_instance {
526 struct edac_device_ctl_info *ctl; /* Up pointer */
527 char name[EDAC_DEVICE_NAME_LEN + 4];
528
529 struct edac_device_counter counters; /* instance counters */
530
531 u32 nr_blocks; /* how many blocks */
532 struct edac_device_block *blocks; /* block array */
533
534 /* edac sysfs device control */
535 struct kobject kobj;
536 };
537
538
539 /*
540 * Abstract edac_device control info structure
541 *
542 */
543 struct edac_device_ctl_info {
544 /* for global list of edac_device_ctl_info structs */
545 struct list_head link;
546
547 struct module *owner; /* Module owner of this control struct */
548
549 int dev_idx;
550
551 /* Per instance controls for this edac_device */
552 int log_ue; /* boolean for logging UEs */
553 int log_ce; /* boolean for logging CEs */
554 int panic_on_ue; /* boolean for panic'ing on an UE */
555 unsigned poll_msec; /* number of milliseconds to poll interval */
556 unsigned long delay; /* number of jiffies for poll_msec */
557
558 /* Additional top controller level attributes, but specified
559 * by the low level driver.
560 *
561 * Set by the low level driver to provide attributes at the
562 * controller level, same level as 'ue_count' and 'ce_count' above.
563 * An array of structures, NULL terminated
564 *
565 * If attributes are desired, then set to array of attributes
566 * If no attributes are desired, leave NULL
567 */
568 struct edac_dev_sysfs_attribute *sysfs_attributes;
569
570 /* pointer to main 'edac' class in sysfs */
571 struct sysdev_class *edac_class;
572
573 /* the internal state of this controller instance */
574 int op_state;
575 /* work struct for this instance */
576 struct delayed_work work;
577
578 /* pointer to edac polling checking routine:
579 * If NOT NULL: points to polling check routine
580 * If NULL: Then assumes INTERRUPT operation, where
581 * MC driver will receive events
582 */
583 void (*edac_check) (struct edac_device_ctl_info * edac_dev);
584
585 struct device *dev; /* pointer to device structure */
586
587 const char *mod_name; /* module name */
588 const char *ctl_name; /* edac controller name */
589 const char *dev_name; /* pci/platform/etc... name */
590
591 void *pvt_info; /* pointer to 'private driver' info */
592
593 unsigned long start_time; /* edac_device load start time (jiffies) */
594
595 /* these are for safe removal of mc devices from global list while
596 * NMI handlers may be traversing list
597 */
598 struct rcu_head rcu;
599 struct completion removal_complete;
600
601 /* sysfs top name under 'edac' directory
602 * and instance name:
603 * cpu/cpu0/...
604 * cpu/cpu1/...
605 * cpu/cpu2/...
606 * ...
607 */
608 char name[EDAC_DEVICE_NAME_LEN + 1];
609
610 /* Number of instances supported on this control structure
611 * and the array of those instances
612 */
613 u32 nr_instances;
614 struct edac_device_instance *instances;
615
616 /* Event counters for the this whole EDAC Device */
617 struct edac_device_counter counters;
618
619 /* edac sysfs device control for the 'name'
620 * device this structure controls
621 */
622 struct kobject kobj;
623 };
624
625 /* To get from the instance's wq to the beginning of the ctl structure */
626 #define to_edac_mem_ctl_work(w) \
627 container_of(w, struct mem_ctl_info, work)
628
629 #define to_edac_device_ctl_work(w) \
630 container_of(w,struct edac_device_ctl_info,work)
631
632 /*
633 * The alloc() and free() functions for the 'edac_device' control info
634 * structure. A MC driver will allocate one of these for each edac_device
635 * it is going to control/register with the EDAC CORE.
636 */
637 extern struct edac_device_ctl_info *edac_device_alloc_ctl_info(
638 unsigned sizeof_private,
639 char *edac_device_name, unsigned nr_instances,
640 char *edac_block_name, unsigned nr_blocks,
641 unsigned offset_value,
642 struct edac_dev_sysfs_block_attribute *block_attributes,
643 unsigned nr_attribs,
644 int device_index);
645
646 /* The offset value can be:
647 * -1 indicating no offset value
648 * 0 for zero-based block numbers
649 * 1 for 1-based block number
650 * other for other-based block number
651 */
652 #define BLOCK_OFFSET_VALUE_OFF ((unsigned) -1)
653
654 extern void edac_device_free_ctl_info(struct edac_device_ctl_info *ctl_info);
655
656 #ifdef CONFIG_PCI
657
658 struct edac_pci_counter {
659 atomic_t pe_count;
660 atomic_t npe_count;
661 };
662
663 /*
664 * Abstract edac_pci control info structure
665 *
666 */
667 struct edac_pci_ctl_info {
668 /* for global list of edac_pci_ctl_info structs */
669 struct list_head link;
670
671 int pci_idx;
672
673 struct sysdev_class *edac_class; /* pointer to class */
674
675 /* the internal state of this controller instance */
676 int op_state;
677 /* work struct for this instance */
678 struct delayed_work work;
679
680 /* pointer to edac polling checking routine:
681 * If NOT NULL: points to polling check routine
682 * If NULL: Then assumes INTERRUPT operation, where
683 * MC driver will receive events
684 */
685 void (*edac_check) (struct edac_pci_ctl_info * edac_dev);
686
687 struct device *dev; /* pointer to device structure */
688
689 const char *mod_name; /* module name */
690 const char *ctl_name; /* edac controller name */
691 const char *dev_name; /* pci/platform/etc... name */
692
693 void *pvt_info; /* pointer to 'private driver' info */
694
695 unsigned long start_time; /* edac_pci load start time (jiffies) */
696
697 /* these are for safe removal of devices from global list while
698 * NMI handlers may be traversing list
699 */
700 struct rcu_head rcu;
701 struct completion complete;
702
703 /* sysfs top name under 'edac' directory
704 * and instance name:
705 * cpu/cpu0/...
706 * cpu/cpu1/...
707 * cpu/cpu2/...
708 * ...
709 */
710 char name[EDAC_DEVICE_NAME_LEN + 1];
711
712 /* Event counters for the this whole EDAC Device */
713 struct edac_pci_counter counters;
714
715 /* edac sysfs device control for the 'name'
716 * device this structure controls
717 */
718 struct kobject kobj;
719 struct completion kobj_complete;
720 };
721
722 #define to_edac_pci_ctl_work(w) \
723 container_of(w, struct edac_pci_ctl_info,work)
724
725 /* write all or some bits in a byte-register*/
pci_write_bits8(struct pci_dev * pdev,int offset,u8 value,u8 mask)726 static inline void pci_write_bits8(struct pci_dev *pdev, int offset, u8 value,
727 u8 mask)
728 {
729 if (mask != 0xff) {
730 u8 buf;
731
732 pci_read_config_byte(pdev, offset, &buf);
733 value &= mask;
734 buf &= ~mask;
735 value |= buf;
736 }
737
738 pci_write_config_byte(pdev, offset, value);
739 }
740
741 /* write all or some bits in a word-register*/
pci_write_bits16(struct pci_dev * pdev,int offset,u16 value,u16 mask)742 static inline void pci_write_bits16(struct pci_dev *pdev, int offset,
743 u16 value, u16 mask)
744 {
745 if (mask != 0xffff) {
746 u16 buf;
747
748 pci_read_config_word(pdev, offset, &buf);
749 value &= mask;
750 buf &= ~mask;
751 value |= buf;
752 }
753
754 pci_write_config_word(pdev, offset, value);
755 }
756
757 /* write all or some bits in a dword-register*/
pci_write_bits32(struct pci_dev * pdev,int offset,u32 value,u32 mask)758 static inline void pci_write_bits32(struct pci_dev *pdev, int offset,
759 u32 value, u32 mask)
760 {
761 if (mask != 0xffff) {
762 u32 buf;
763
764 pci_read_config_dword(pdev, offset, &buf);
765 value &= mask;
766 buf &= ~mask;
767 value |= buf;
768 }
769
770 pci_write_config_dword(pdev, offset, value);
771 }
772
773 #endif /* CONFIG_PCI */
774
775 extern struct mem_ctl_info *edac_mc_alloc(unsigned sz_pvt, unsigned nr_csrows,
776 unsigned nr_chans, int edac_index);
777 extern int edac_mc_add_mc(struct mem_ctl_info *mci);
778 extern void edac_mc_free(struct mem_ctl_info *mci);
779 extern struct mem_ctl_info *edac_mc_find(int idx);
780 extern struct mem_ctl_info *edac_mc_del_mc(struct device *dev);
781 extern int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci,
782 unsigned long page);
783
784 /*
785 * The no info errors are used when error overflows are reported.
786 * There are a limited number of error logging registers that can
787 * be exausted. When all registers are exhausted and an additional
788 * error occurs then an error overflow register records that an
789 * error occured and the type of error, but doesn't have any
790 * further information. The ce/ue versions make for cleaner
791 * reporting logic and function interface - reduces conditional
792 * statement clutter and extra function arguments.
793 */
794 extern void edac_mc_handle_ce(struct mem_ctl_info *mci,
795 unsigned long page_frame_number,
796 unsigned long offset_in_page,
797 unsigned long syndrome, int row, int channel,
798 const char *msg);
799 extern void edac_mc_handle_ce_no_info(struct mem_ctl_info *mci,
800 const char *msg);
801 extern void edac_mc_handle_ue(struct mem_ctl_info *mci,
802 unsigned long page_frame_number,
803 unsigned long offset_in_page, int row,
804 const char *msg);
805 extern void edac_mc_handle_ue_no_info(struct mem_ctl_info *mci,
806 const char *msg);
807 extern void edac_mc_handle_fbd_ue(struct mem_ctl_info *mci, unsigned int csrow,
808 unsigned int channel0, unsigned int channel1,
809 char *msg);
810 extern void edac_mc_handle_fbd_ce(struct mem_ctl_info *mci, unsigned int csrow,
811 unsigned int channel, char *msg);
812
813 /*
814 * edac_device APIs
815 */
816 extern int edac_device_add_device(struct edac_device_ctl_info *edac_dev);
817 extern struct edac_device_ctl_info *edac_device_del_device(struct device *dev);
818 extern void edac_device_handle_ue(struct edac_device_ctl_info *edac_dev,
819 int inst_nr, int block_nr, const char *msg);
820 extern void edac_device_handle_ce(struct edac_device_ctl_info *edac_dev,
821 int inst_nr, int block_nr, const char *msg);
822
823 /*
824 * edac_pci APIs
825 */
826 extern struct edac_pci_ctl_info *edac_pci_alloc_ctl_info(unsigned int sz_pvt,
827 const char *edac_pci_name);
828
829 extern void edac_pci_free_ctl_info(struct edac_pci_ctl_info *pci);
830
831 extern void edac_pci_reset_delay_period(struct edac_pci_ctl_info *pci,
832 unsigned long value);
833
834 extern int edac_pci_add_device(struct edac_pci_ctl_info *pci, int edac_idx);
835 extern struct edac_pci_ctl_info *edac_pci_del_device(struct device *dev);
836
837 extern struct edac_pci_ctl_info *edac_pci_create_generic_ctl(
838 struct device *dev,
839 const char *mod_name);
840
841 extern void edac_pci_release_generic_ctl(struct edac_pci_ctl_info *pci);
842 extern int edac_pci_create_sysfs(struct edac_pci_ctl_info *pci);
843 extern void edac_pci_remove_sysfs(struct edac_pci_ctl_info *pci);
844
845 /*
846 * edac misc APIs
847 */
848 extern char *edac_op_state_to_string(int op_state);
849
850 #endif /* _EDAC_CORE_H_ */
851