1 /*
2 * Code to handle x86 style IRQs plus some generic interrupt stuff.
3 *
4 * Copyright (C) 1992 Linus Torvalds
5 * Copyright (C) 1994, 1995, 1996, 1997, 1998 Ralf Baechle
6 * Copyright (C) 1999 SuSE GmbH (Philipp Rumpf, prumpf@tux.org)
7 * Copyright (C) 1999-2000 Grant Grundler
8 * Copyright (c) 2005 Matthew Wilcox
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2, or (at your option)
13 * any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24 #include <linux/bitops.h>
25 #include <linux/errno.h>
26 #include <linux/init.h>
27 #include <linux/interrupt.h>
28 #include <linux/kernel_stat.h>
29 #include <linux/seq_file.h>
30 #include <linux/spinlock.h>
31 #include <linux/types.h>
32 #include <asm/io.h>
33
34 #include <asm/smp.h>
35
36 #undef PARISC_IRQ_CR16_COUNTS
37
38 extern irqreturn_t timer_interrupt(int, void *);
39 extern irqreturn_t ipi_interrupt(int, void *);
40
41 #define EIEM_MASK(irq) (1UL<<(CPU_IRQ_MAX - irq))
42
43 /* Bits in EIEM correlate with cpu_irq_action[].
44 ** Numbered *Big Endian*! (ie bit 0 is MSB)
45 */
46 static volatile unsigned long cpu_eiem = 0;
47
48 /*
49 ** local ACK bitmap ... habitually set to 1, but reset to zero
50 ** between ->ack() and ->end() of the interrupt to prevent
51 ** re-interruption of a processing interrupt.
52 */
53 static DEFINE_PER_CPU(unsigned long, local_ack_eiem) = ~0UL;
54
cpu_disable_irq(unsigned int irq)55 static void cpu_disable_irq(unsigned int irq)
56 {
57 unsigned long eirr_bit = EIEM_MASK(irq);
58
59 cpu_eiem &= ~eirr_bit;
60 /* Do nothing on the other CPUs. If they get this interrupt,
61 * The & cpu_eiem in the do_cpu_irq_mask() ensures they won't
62 * handle it, and the set_eiem() at the bottom will ensure it
63 * then gets disabled */
64 }
65
cpu_enable_irq(unsigned int irq)66 static void cpu_enable_irq(unsigned int irq)
67 {
68 unsigned long eirr_bit = EIEM_MASK(irq);
69
70 cpu_eiem |= eirr_bit;
71
72 /* This is just a simple NOP IPI. But what it does is cause
73 * all the other CPUs to do a set_eiem(cpu_eiem) at the end
74 * of the interrupt handler */
75 smp_send_all_nop();
76 }
77
cpu_startup_irq(unsigned int irq)78 static unsigned int cpu_startup_irq(unsigned int irq)
79 {
80 cpu_enable_irq(irq);
81 return 0;
82 }
83
no_ack_irq(unsigned int irq)84 void no_ack_irq(unsigned int irq) { }
no_end_irq(unsigned int irq)85 void no_end_irq(unsigned int irq) { }
86
cpu_ack_irq(unsigned int irq)87 void cpu_ack_irq(unsigned int irq)
88 {
89 unsigned long mask = EIEM_MASK(irq);
90 int cpu = smp_processor_id();
91
92 /* Clear in EIEM so we can no longer process */
93 per_cpu(local_ack_eiem, cpu) &= ~mask;
94
95 /* disable the interrupt */
96 set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu));
97
98 /* and now ack it */
99 mtctl(mask, 23);
100 }
101
cpu_end_irq(unsigned int irq)102 void cpu_end_irq(unsigned int irq)
103 {
104 unsigned long mask = EIEM_MASK(irq);
105 int cpu = smp_processor_id();
106
107 /* set it in the eiems---it's no longer in process */
108 per_cpu(local_ack_eiem, cpu) |= mask;
109
110 /* enable the interrupt */
111 set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu));
112 }
113
114 #ifdef CONFIG_SMP
cpu_check_affinity(unsigned int irq,const struct cpumask * dest)115 int cpu_check_affinity(unsigned int irq, const struct cpumask *dest)
116 {
117 int cpu_dest;
118
119 /* timer and ipi have to always be received on all CPUs */
120 if (CHECK_IRQ_PER_CPU(irq)) {
121 /* Bad linux design decision. The mask has already
122 * been set; we must reset it */
123 cpumask_setall(&irq_desc[irq].affinity);
124 return -EINVAL;
125 }
126
127 /* whatever mask they set, we just allow one CPU */
128 cpu_dest = first_cpu(*dest);
129
130 return cpu_dest;
131 }
132
cpu_set_affinity_irq(unsigned int irq,const struct cpumask * dest)133 static void cpu_set_affinity_irq(unsigned int irq, const struct cpumask *dest)
134 {
135 int cpu_dest;
136
137 cpu_dest = cpu_check_affinity(irq, dest);
138 if (cpu_dest < 0)
139 return;
140
141 cpumask_copy(&irq_desc[irq].affinity, &cpumask_of_cpu(cpu_dest));
142 }
143 #endif
144
145 static struct hw_interrupt_type cpu_interrupt_type = {
146 .typename = "CPU",
147 .startup = cpu_startup_irq,
148 .shutdown = cpu_disable_irq,
149 .enable = cpu_enable_irq,
150 .disable = cpu_disable_irq,
151 .ack = cpu_ack_irq,
152 .end = cpu_end_irq,
153 #ifdef CONFIG_SMP
154 .set_affinity = cpu_set_affinity_irq,
155 #endif
156 /* XXX: Needs to be written. We managed without it so far, but
157 * we really ought to write it.
158 */
159 .retrigger = NULL,
160 };
161
show_interrupts(struct seq_file * p,void * v)162 int show_interrupts(struct seq_file *p, void *v)
163 {
164 int i = *(loff_t *) v, j;
165 unsigned long flags;
166
167 if (i == 0) {
168 seq_puts(p, " ");
169 for_each_online_cpu(j)
170 seq_printf(p, " CPU%d", j);
171
172 #ifdef PARISC_IRQ_CR16_COUNTS
173 seq_printf(p, " [min/avg/max] (CPU cycle counts)");
174 #endif
175 seq_putc(p, '\n');
176 }
177
178 if (i < NR_IRQS) {
179 struct irqaction *action;
180
181 spin_lock_irqsave(&irq_desc[i].lock, flags);
182 action = irq_desc[i].action;
183 if (!action)
184 goto skip;
185 seq_printf(p, "%3d: ", i);
186 #ifdef CONFIG_SMP
187 for_each_online_cpu(j)
188 seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
189 #else
190 seq_printf(p, "%10u ", kstat_irqs(i));
191 #endif
192
193 seq_printf(p, " %14s", irq_desc[i].chip->typename);
194 #ifndef PARISC_IRQ_CR16_COUNTS
195 seq_printf(p, " %s", action->name);
196
197 while ((action = action->next))
198 seq_printf(p, ", %s", action->name);
199 #else
200 for ( ;action; action = action->next) {
201 unsigned int k, avg, min, max;
202
203 min = max = action->cr16_hist[0];
204
205 for (avg = k = 0; k < PARISC_CR16_HIST_SIZE; k++) {
206 int hist = action->cr16_hist[k];
207
208 if (hist) {
209 avg += hist;
210 } else
211 break;
212
213 if (hist > max) max = hist;
214 if (hist < min) min = hist;
215 }
216
217 avg /= k;
218 seq_printf(p, " %s[%d/%d/%d]", action->name,
219 min,avg,max);
220 }
221 #endif
222
223 seq_putc(p, '\n');
224 skip:
225 spin_unlock_irqrestore(&irq_desc[i].lock, flags);
226 }
227
228 return 0;
229 }
230
231
232
233 /*
234 ** The following form a "set": Virtual IRQ, Transaction Address, Trans Data.
235 ** Respectively, these map to IRQ region+EIRR, Processor HPA, EIRR bit.
236 **
237 ** To use txn_XXX() interfaces, get a Virtual IRQ first.
238 ** Then use that to get the Transaction address and data.
239 */
240
cpu_claim_irq(unsigned int irq,struct irq_chip * type,void * data)241 int cpu_claim_irq(unsigned int irq, struct irq_chip *type, void *data)
242 {
243 if (irq_desc[irq].action)
244 return -EBUSY;
245 if (irq_desc[irq].chip != &cpu_interrupt_type)
246 return -EBUSY;
247
248 if (type) {
249 irq_desc[irq].chip = type;
250 irq_desc[irq].chip_data = data;
251 cpu_interrupt_type.enable(irq);
252 }
253 return 0;
254 }
255
txn_claim_irq(int irq)256 int txn_claim_irq(int irq)
257 {
258 return cpu_claim_irq(irq, NULL, NULL) ? -1 : irq;
259 }
260
261 /*
262 * The bits_wide parameter accommodates the limitations of the HW/SW which
263 * use these bits:
264 * Legacy PA I/O (GSC/NIO): 5 bits (architected EIM register)
265 * V-class (EPIC): 6 bits
266 * N/L/A-class (iosapic): 8 bits
267 * PCI 2.2 MSI: 16 bits
268 * Some PCI devices: 32 bits (Symbios SCSI/ATM/HyperFabric)
269 *
270 * On the service provider side:
271 * o PA 1.1 (and PA2.0 narrow mode) 5-bits (width of EIR register)
272 * o PA 2.0 wide mode 6-bits (per processor)
273 * o IA64 8-bits (0-256 total)
274 *
275 * So a Legacy PA I/O device on a PA 2.0 box can't use all the bits supported
276 * by the processor...and the N/L-class I/O subsystem supports more bits than
277 * PA2.0 has. The first case is the problem.
278 */
txn_alloc_irq(unsigned int bits_wide)279 int txn_alloc_irq(unsigned int bits_wide)
280 {
281 int irq;
282
283 /* never return irq 0 cause that's the interval timer */
284 for (irq = CPU_IRQ_BASE + 1; irq <= CPU_IRQ_MAX; irq++) {
285 if (cpu_claim_irq(irq, NULL, NULL) < 0)
286 continue;
287 if ((irq - CPU_IRQ_BASE) >= (1 << bits_wide))
288 continue;
289 return irq;
290 }
291
292 /* unlikely, but be prepared */
293 return -1;
294 }
295
296
txn_affinity_addr(unsigned int irq,int cpu)297 unsigned long txn_affinity_addr(unsigned int irq, int cpu)
298 {
299 #ifdef CONFIG_SMP
300 cpumask_copy(&irq_desc[irq].affinity, cpumask_of(cpu));
301 #endif
302
303 return per_cpu(cpu_data, cpu).txn_addr;
304 }
305
306
txn_alloc_addr(unsigned int virt_irq)307 unsigned long txn_alloc_addr(unsigned int virt_irq)
308 {
309 static int next_cpu = -1;
310
311 next_cpu++; /* assign to "next" CPU we want this bugger on */
312
313 /* validate entry */
314 while ((next_cpu < NR_CPUS) &&
315 (!per_cpu(cpu_data, next_cpu).txn_addr ||
316 !cpu_online(next_cpu)))
317 next_cpu++;
318
319 if (next_cpu >= NR_CPUS)
320 next_cpu = 0; /* nothing else, assign monarch */
321
322 return txn_affinity_addr(virt_irq, next_cpu);
323 }
324
325
txn_alloc_data(unsigned int virt_irq)326 unsigned int txn_alloc_data(unsigned int virt_irq)
327 {
328 return virt_irq - CPU_IRQ_BASE;
329 }
330
eirr_to_irq(unsigned long eirr)331 static inline int eirr_to_irq(unsigned long eirr)
332 {
333 int bit = fls_long(eirr);
334 return (BITS_PER_LONG - bit) + TIMER_IRQ;
335 }
336
337 /* ONLY called from entry.S:intr_extint() */
do_cpu_irq_mask(struct pt_regs * regs)338 void do_cpu_irq_mask(struct pt_regs *regs)
339 {
340 struct pt_regs *old_regs;
341 unsigned long eirr_val;
342 int irq, cpu = smp_processor_id();
343 #ifdef CONFIG_SMP
344 cpumask_t dest;
345 #endif
346
347 old_regs = set_irq_regs(regs);
348 local_irq_disable();
349 irq_enter();
350
351 eirr_val = mfctl(23) & cpu_eiem & per_cpu(local_ack_eiem, cpu);
352 if (!eirr_val)
353 goto set_out;
354 irq = eirr_to_irq(eirr_val);
355
356 #ifdef CONFIG_SMP
357 cpumask_copy(&dest, &irq_desc[irq].affinity);
358 if (CHECK_IRQ_PER_CPU(irq_desc[irq].status) &&
359 !cpu_isset(smp_processor_id(), dest)) {
360 int cpu = first_cpu(dest);
361
362 printk(KERN_DEBUG "redirecting irq %d from CPU %d to %d\n",
363 irq, smp_processor_id(), cpu);
364 gsc_writel(irq + CPU_IRQ_BASE,
365 per_cpu(cpu_data, cpu).hpa);
366 goto set_out;
367 }
368 #endif
369 __do_IRQ(irq);
370
371 out:
372 irq_exit();
373 set_irq_regs(old_regs);
374 return;
375
376 set_out:
377 set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu));
378 goto out;
379 }
380
381 static struct irqaction timer_action = {
382 .handler = timer_interrupt,
383 .name = "timer",
384 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_PERCPU | IRQF_IRQPOLL,
385 };
386
387 #ifdef CONFIG_SMP
388 static struct irqaction ipi_action = {
389 .handler = ipi_interrupt,
390 .name = "IPI",
391 .flags = IRQF_DISABLED | IRQF_PERCPU,
392 };
393 #endif
394
claim_cpu_irqs(void)395 static void claim_cpu_irqs(void)
396 {
397 int i;
398 for (i = CPU_IRQ_BASE; i <= CPU_IRQ_MAX; i++) {
399 irq_desc[i].chip = &cpu_interrupt_type;
400 }
401
402 irq_desc[TIMER_IRQ].action = &timer_action;
403 irq_desc[TIMER_IRQ].status = IRQ_PER_CPU;
404 #ifdef CONFIG_SMP
405 irq_desc[IPI_IRQ].action = &ipi_action;
406 irq_desc[IPI_IRQ].status = IRQ_PER_CPU;
407 #endif
408 }
409
init_IRQ(void)410 void __init init_IRQ(void)
411 {
412 local_irq_disable(); /* PARANOID - should already be disabled */
413 mtctl(~0UL, 23); /* EIRR : clear all pending external intr */
414 claim_cpu_irqs();
415 #ifdef CONFIG_SMP
416 if (!cpu_eiem)
417 cpu_eiem = EIEM_MASK(IPI_IRQ) | EIEM_MASK(TIMER_IRQ);
418 #else
419 cpu_eiem = EIEM_MASK(TIMER_IRQ);
420 #endif
421 set_eiem(cpu_eiem); /* EIEM : enable all external intr */
422
423 }
424
ack_bad_irq(unsigned int irq)425 void ack_bad_irq(unsigned int irq)
426 {
427 printk(KERN_WARNING "unexpected IRQ %d\n", irq);
428 }
429