• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1 /*
2  * arch/arm/mach-ep93xx/core.c
3  * Core routines for Cirrus EP93xx chips.
4  *
5  * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
6  * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org>
7  *
8  * Thanks go to Michael Burian and Ray Lehtiniemi for their key
9  * role in the ep93xx linux community.
10  *
11  * This program is free software; you can redistribute it and/or modify
12  * it under the terms of the GNU General Public License as published by
13  * the Free Software Foundation; either version 2 of the License, or (at
14  * your option) any later version.
15  */
16 
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/spinlock.h>
20 #include <linux/sched.h>
21 #include <linux/interrupt.h>
22 #include <linux/serial.h>
23 #include <linux/tty.h>
24 #include <linux/bitops.h>
25 #include <linux/serial_8250.h>
26 #include <linux/serial_core.h>
27 #include <linux/device.h>
28 #include <linux/mm.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/time.h>
31 #include <linux/timex.h>
32 #include <linux/delay.h>
33 #include <linux/termios.h>
34 #include <linux/amba/bus.h>
35 #include <linux/amba/serial.h>
36 #include <linux/io.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-gpio.h>
39 
40 #include <asm/types.h>
41 #include <asm/setup.h>
42 #include <asm/memory.h>
43 #include <mach/hardware.h>
44 #include <asm/irq.h>
45 #include <asm/system.h>
46 #include <asm/tlbflush.h>
47 #include <asm/pgtable.h>
48 
49 #include <asm/mach/map.h>
50 #include <asm/mach/time.h>
51 #include <asm/mach/irq.h>
52 #include <mach/gpio.h>
53 
54 #include <asm/hardware/vic.h>
55 
56 
57 /*************************************************************************
58  * Static I/O mappings that are needed for all EP93xx platforms
59  *************************************************************************/
60 static struct map_desc ep93xx_io_desc[] __initdata = {
61 	{
62 		.virtual	= EP93XX_AHB_VIRT_BASE,
63 		.pfn		= __phys_to_pfn(EP93XX_AHB_PHYS_BASE),
64 		.length		= EP93XX_AHB_SIZE,
65 		.type		= MT_DEVICE,
66 	}, {
67 		.virtual	= EP93XX_APB_VIRT_BASE,
68 		.pfn		= __phys_to_pfn(EP93XX_APB_PHYS_BASE),
69 		.length		= EP93XX_APB_SIZE,
70 		.type		= MT_DEVICE,
71 	},
72 };
73 
ep93xx_map_io(void)74 void __init ep93xx_map_io(void)
75 {
76 	iotable_init(ep93xx_io_desc, ARRAY_SIZE(ep93xx_io_desc));
77 }
78 
79 
80 /*************************************************************************
81  * Timer handling for EP93xx
82  *************************************************************************
83  * The ep93xx has four internal timers.  Timers 1, 2 (both 16 bit) and
84  * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate
85  * an interrupt on underflow.  Timer 4 (40 bit) counts down at 983.04 kHz,
86  * is free-running, and can't generate interrupts.
87  *
88  * The 508 kHz timers are ideal for use for the timer interrupt, as the
89  * most common values of HZ divide 508 kHz nicely.  We pick one of the 16
90  * bit timers (timer 1) since we don't need more than 16 bits of reload
91  * value as long as HZ >= 8.
92  *
93  * The higher clock rate of timer 4 makes it a better choice than the
94  * other timers for use in gettimeoffset(), while the fact that it can't
95  * generate interrupts means we don't have to worry about not being able
96  * to use this timer for something else.  We also use timer 4 for keeping
97  * track of lost jiffies.
98  */
99 static unsigned int last_jiffy_time;
100 
101 #define TIMER4_TICKS_PER_JIFFY		((CLOCK_TICK_RATE + (HZ/2)) / HZ)
102 
ep93xx_timer_interrupt(int irq,void * dev_id)103 static int ep93xx_timer_interrupt(int irq, void *dev_id)
104 {
105 	__raw_writel(1, EP93XX_TIMER1_CLEAR);
106 	while ((signed long)
107 		(__raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time)
108 						>= TIMER4_TICKS_PER_JIFFY) {
109 		last_jiffy_time += TIMER4_TICKS_PER_JIFFY;
110 		timer_tick();
111 	}
112 
113 	return IRQ_HANDLED;
114 }
115 
116 static struct irqaction ep93xx_timer_irq = {
117 	.name		= "ep93xx timer",
118 	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
119 	.handler	= ep93xx_timer_interrupt,
120 };
121 
ep93xx_timer_init(void)122 static void __init ep93xx_timer_init(void)
123 {
124 	/* Enable periodic HZ timer.  */
125 	__raw_writel(0x48, EP93XX_TIMER1_CONTROL);
126 	__raw_writel((508469 / HZ) - 1, EP93XX_TIMER1_LOAD);
127 	__raw_writel(0xc8, EP93XX_TIMER1_CONTROL);
128 
129 	/* Enable lost jiffy timer.  */
130 	__raw_writel(0x100, EP93XX_TIMER4_VALUE_HIGH);
131 
132 	setup_irq(IRQ_EP93XX_TIMER1, &ep93xx_timer_irq);
133 }
134 
ep93xx_gettimeoffset(void)135 static unsigned long ep93xx_gettimeoffset(void)
136 {
137 	int offset;
138 
139 	offset = __raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time;
140 
141 	/* Calculate (1000000 / 983040) * offset.  */
142 	return offset + (53 * offset / 3072);
143 }
144 
145 struct sys_timer ep93xx_timer = {
146 	.init		= ep93xx_timer_init,
147 	.offset		= ep93xx_gettimeoffset,
148 };
149 
150 
151 /*************************************************************************
152  * GPIO handling for EP93xx
153  *************************************************************************/
154 static unsigned char gpio_int_unmasked[3];
155 static unsigned char gpio_int_enabled[3];
156 static unsigned char gpio_int_type1[3];
157 static unsigned char gpio_int_type2[3];
158 static unsigned char gpio_int_debouce[3];
159 
160 /* Port ordering is: A B F */
161 static const u8 int_type1_register_offset[3]	= { 0x90, 0xac, 0x4c };
162 static const u8 int_type2_register_offset[3]	= { 0x94, 0xb0, 0x50 };
163 static const u8 eoi_register_offset[3]		= { 0x98, 0xb4, 0x54 };
164 static const u8 int_en_register_offset[3]	= { 0x9c, 0xb8, 0x58 };
165 static const u8 int_debounce_register_offset[3]	= { 0xa8, 0xc4, 0x64 };
166 
ep93xx_gpio_update_int_params(unsigned port)167 void ep93xx_gpio_update_int_params(unsigned port)
168 {
169 	BUG_ON(port > 2);
170 
171 	__raw_writeb(0, EP93XX_GPIO_REG(int_en_register_offset[port]));
172 
173 	__raw_writeb(gpio_int_type2[port],
174 		EP93XX_GPIO_REG(int_type2_register_offset[port]));
175 
176 	__raw_writeb(gpio_int_type1[port],
177 		EP93XX_GPIO_REG(int_type1_register_offset[port]));
178 
179 	__raw_writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
180 		EP93XX_GPIO_REG(int_en_register_offset[port]));
181 }
182 
ep93xx_gpio_int_mask(unsigned line)183 void ep93xx_gpio_int_mask(unsigned line)
184 {
185 	gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7));
186 }
187 
ep93xx_gpio_int_debounce(unsigned int irq,int enable)188 void ep93xx_gpio_int_debounce(unsigned int irq, int enable)
189 {
190 	int line = irq_to_gpio(irq);
191 	int port = line >> 3;
192 	int port_mask = 1 << (line & 7);
193 
194 	if (enable)
195 		gpio_int_debouce[port] |= port_mask;
196 	else
197 		gpio_int_debouce[port] &= ~port_mask;
198 
199 	__raw_writeb(gpio_int_debouce[port],
200 		EP93XX_GPIO_REG(int_debounce_register_offset[port]));
201 }
202 EXPORT_SYMBOL(ep93xx_gpio_int_debounce);
203 
204 /*************************************************************************
205  * EP93xx IRQ handling
206  *************************************************************************/
ep93xx_gpio_ab_irq_handler(unsigned int irq,struct irq_desc * desc)207 static void ep93xx_gpio_ab_irq_handler(unsigned int irq, struct irq_desc *desc)
208 {
209 	unsigned char status;
210 	int i;
211 
212 	status = __raw_readb(EP93XX_GPIO_A_INT_STATUS);
213 	for (i = 0; i < 8; i++) {
214 		if (status & (1 << i)) {
215 			int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_A(0)) + i;
216 			generic_handle_irq(gpio_irq);
217 		}
218 	}
219 
220 	status = __raw_readb(EP93XX_GPIO_B_INT_STATUS);
221 	for (i = 0; i < 8; i++) {
222 		if (status & (1 << i)) {
223 			int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_B(0)) + i;
224 			desc = irq_desc + gpio_irq;
225 			generic_handle_irq(gpio_irq);
226 		}
227 	}
228 }
229 
ep93xx_gpio_f_irq_handler(unsigned int irq,struct irq_desc * desc)230 static void ep93xx_gpio_f_irq_handler(unsigned int irq, struct irq_desc *desc)
231 {
232 	/*
233 	 * map discontiguous hw irq range to continous sw irq range:
234 	 *
235 	 *  IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7})
236 	 */
237 	int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
238 	int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_F(0)) + port_f_idx;
239 
240 	generic_handle_irq(gpio_irq);
241 }
242 
ep93xx_gpio_irq_ack(unsigned int irq)243 static void ep93xx_gpio_irq_ack(unsigned int irq)
244 {
245 	int line = irq_to_gpio(irq);
246 	int port = line >> 3;
247 	int port_mask = 1 << (line & 7);
248 
249 	if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
250 		gpio_int_type2[port] ^= port_mask; /* switch edge direction */
251 		ep93xx_gpio_update_int_params(port);
252 	}
253 
254 	__raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
255 }
256 
ep93xx_gpio_irq_mask_ack(unsigned int irq)257 static void ep93xx_gpio_irq_mask_ack(unsigned int irq)
258 {
259 	int line = irq_to_gpio(irq);
260 	int port = line >> 3;
261 	int port_mask = 1 << (line & 7);
262 
263 	if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
264 		gpio_int_type2[port] ^= port_mask; /* switch edge direction */
265 
266 	gpio_int_unmasked[port] &= ~port_mask;
267 	ep93xx_gpio_update_int_params(port);
268 
269 	__raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
270 }
271 
ep93xx_gpio_irq_mask(unsigned int irq)272 static void ep93xx_gpio_irq_mask(unsigned int irq)
273 {
274 	int line = irq_to_gpio(irq);
275 	int port = line >> 3;
276 
277 	gpio_int_unmasked[port] &= ~(1 << (line & 7));
278 	ep93xx_gpio_update_int_params(port);
279 }
280 
ep93xx_gpio_irq_unmask(unsigned int irq)281 static void ep93xx_gpio_irq_unmask(unsigned int irq)
282 {
283 	int line = irq_to_gpio(irq);
284 	int port = line >> 3;
285 
286 	gpio_int_unmasked[port] |= 1 << (line & 7);
287 	ep93xx_gpio_update_int_params(port);
288 }
289 
290 
291 /*
292  * gpio_int_type1 controls whether the interrupt is level (0) or
293  * edge (1) triggered, while gpio_int_type2 controls whether it
294  * triggers on low/falling (0) or high/rising (1).
295  */
ep93xx_gpio_irq_type(unsigned int irq,unsigned int type)296 static int ep93xx_gpio_irq_type(unsigned int irq, unsigned int type)
297 {
298 	struct irq_desc *desc = irq_desc + irq;
299 	const int gpio = irq_to_gpio(irq);
300 	const int port = gpio >> 3;
301 	const int port_mask = 1 << (gpio & 7);
302 
303 	gpio_direction_input(gpio);
304 
305 	switch (type) {
306 	case IRQ_TYPE_EDGE_RISING:
307 		gpio_int_type1[port] |= port_mask;
308 		gpio_int_type2[port] |= port_mask;
309 		desc->handle_irq = handle_edge_irq;
310 		break;
311 	case IRQ_TYPE_EDGE_FALLING:
312 		gpio_int_type1[port] |= port_mask;
313 		gpio_int_type2[port] &= ~port_mask;
314 		desc->handle_irq = handle_edge_irq;
315 		break;
316 	case IRQ_TYPE_LEVEL_HIGH:
317 		gpio_int_type1[port] &= ~port_mask;
318 		gpio_int_type2[port] |= port_mask;
319 		desc->handle_irq = handle_level_irq;
320 		break;
321 	case IRQ_TYPE_LEVEL_LOW:
322 		gpio_int_type1[port] &= ~port_mask;
323 		gpio_int_type2[port] &= ~port_mask;
324 		desc->handle_irq = handle_level_irq;
325 		break;
326 	case IRQ_TYPE_EDGE_BOTH:
327 		gpio_int_type1[port] |= port_mask;
328 		/* set initial polarity based on current input level */
329 		if (gpio_get_value(gpio))
330 			gpio_int_type2[port] &= ~port_mask; /* falling */
331 		else
332 			gpio_int_type2[port] |= port_mask; /* rising */
333 		desc->handle_irq = handle_edge_irq;
334 		break;
335 	default:
336 		pr_err("ep93xx: failed to set irq type %d for gpio %d\n",
337 		       type, gpio);
338 		return -EINVAL;
339 	}
340 
341 	gpio_int_enabled[port] |= port_mask;
342 
343 	desc->status &= ~IRQ_TYPE_SENSE_MASK;
344 	desc->status |= type & IRQ_TYPE_SENSE_MASK;
345 
346 	ep93xx_gpio_update_int_params(port);
347 
348 	return 0;
349 }
350 
351 static struct irq_chip ep93xx_gpio_irq_chip = {
352 	.name		= "GPIO",
353 	.ack		= ep93xx_gpio_irq_ack,
354 	.mask_ack	= ep93xx_gpio_irq_mask_ack,
355 	.mask		= ep93xx_gpio_irq_mask,
356 	.unmask		= ep93xx_gpio_irq_unmask,
357 	.set_type	= ep93xx_gpio_irq_type,
358 };
359 
360 
ep93xx_init_irq(void)361 void __init ep93xx_init_irq(void)
362 {
363 	int gpio_irq;
364 
365 	vic_init((void *)EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK);
366 	vic_init((void *)EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK);
367 
368 	for (gpio_irq = gpio_to_irq(0);
369 	     gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
370 		set_irq_chip(gpio_irq, &ep93xx_gpio_irq_chip);
371 		set_irq_handler(gpio_irq, handle_level_irq);
372 		set_irq_flags(gpio_irq, IRQF_VALID);
373 	}
374 
375 	set_irq_chained_handler(IRQ_EP93XX_GPIO_AB, ep93xx_gpio_ab_irq_handler);
376 	set_irq_chained_handler(IRQ_EP93XX_GPIO0MUX, ep93xx_gpio_f_irq_handler);
377 	set_irq_chained_handler(IRQ_EP93XX_GPIO1MUX, ep93xx_gpio_f_irq_handler);
378 	set_irq_chained_handler(IRQ_EP93XX_GPIO2MUX, ep93xx_gpio_f_irq_handler);
379 	set_irq_chained_handler(IRQ_EP93XX_GPIO3MUX, ep93xx_gpio_f_irq_handler);
380 	set_irq_chained_handler(IRQ_EP93XX_GPIO4MUX, ep93xx_gpio_f_irq_handler);
381 	set_irq_chained_handler(IRQ_EP93XX_GPIO5MUX, ep93xx_gpio_f_irq_handler);
382 	set_irq_chained_handler(IRQ_EP93XX_GPIO6MUX, ep93xx_gpio_f_irq_handler);
383 	set_irq_chained_handler(IRQ_EP93XX_GPIO7MUX, ep93xx_gpio_f_irq_handler);
384 }
385 
386 
387 /*************************************************************************
388  * EP93xx peripheral handling
389  *************************************************************************/
390 #define EP93XX_UART_MCR_OFFSET		(0x0100)
391 
ep93xx_uart_set_mctrl(struct amba_device * dev,void __iomem * base,unsigned int mctrl)392 static void ep93xx_uart_set_mctrl(struct amba_device *dev,
393 				  void __iomem *base, unsigned int mctrl)
394 {
395 	unsigned int mcr;
396 
397 	mcr = 0;
398 	if (!(mctrl & TIOCM_RTS))
399 		mcr |= 2;
400 	if (!(mctrl & TIOCM_DTR))
401 		mcr |= 1;
402 
403 	__raw_writel(mcr, base + EP93XX_UART_MCR_OFFSET);
404 }
405 
406 static struct amba_pl010_data ep93xx_uart_data = {
407 	.set_mctrl	= ep93xx_uart_set_mctrl,
408 };
409 
410 static struct amba_device uart1_device = {
411 	.dev		= {
412 		.init_name	= "apb:uart1",
413 		.platform_data	= &ep93xx_uart_data,
414 	},
415 	.res		= {
416 		.start	= EP93XX_UART1_PHYS_BASE,
417 		.end	= EP93XX_UART1_PHYS_BASE + 0x0fff,
418 		.flags	= IORESOURCE_MEM,
419 	},
420 	.irq		= { IRQ_EP93XX_UART1, NO_IRQ },
421 	.periphid	= 0x00041010,
422 };
423 
424 static struct amba_device uart2_device = {
425 	.dev		= {
426 		.init_name	= "apb:uart2",
427 		.platform_data	= &ep93xx_uart_data,
428 	},
429 	.res		= {
430 		.start	= EP93XX_UART2_PHYS_BASE,
431 		.end	= EP93XX_UART2_PHYS_BASE + 0x0fff,
432 		.flags	= IORESOURCE_MEM,
433 	},
434 	.irq		= { IRQ_EP93XX_UART2, NO_IRQ },
435 	.periphid	= 0x00041010,
436 };
437 
438 static struct amba_device uart3_device = {
439 	.dev		= {
440 		.init_name	= "apb:uart3",
441 		.platform_data	= &ep93xx_uart_data,
442 	},
443 	.res		= {
444 		.start	= EP93XX_UART3_PHYS_BASE,
445 		.end	= EP93XX_UART3_PHYS_BASE + 0x0fff,
446 		.flags	= IORESOURCE_MEM,
447 	},
448 	.irq		= { IRQ_EP93XX_UART3, NO_IRQ },
449 	.periphid	= 0x00041010,
450 };
451 
452 
453 static struct platform_device ep93xx_rtc_device = {
454        .name           = "ep93xx-rtc",
455        .id             = -1,
456        .num_resources  = 0,
457 };
458 
459 
460 static struct resource ep93xx_ohci_resources[] = {
461 	[0] = {
462 		.start	= EP93XX_USB_PHYS_BASE,
463 		.end	= EP93XX_USB_PHYS_BASE + 0x0fff,
464 		.flags	= IORESOURCE_MEM,
465 	},
466 	[1] = {
467 		.start	= IRQ_EP93XX_USB,
468 		.end	= IRQ_EP93XX_USB,
469 		.flags	= IORESOURCE_IRQ,
470 	},
471 };
472 
473 
474 static struct platform_device ep93xx_ohci_device = {
475 	.name		= "ep93xx-ohci",
476 	.id		= -1,
477 	.dev		= {
478 		.dma_mask		= &ep93xx_ohci_device.dev.coherent_dma_mask,
479 		.coherent_dma_mask	= DMA_BIT_MASK(32),
480 	},
481 	.num_resources	= ARRAY_SIZE(ep93xx_ohci_resources),
482 	.resource	= ep93xx_ohci_resources,
483 };
484 
485 static struct ep93xx_eth_data ep93xx_eth_data;
486 
487 static struct resource ep93xx_eth_resource[] = {
488 	{
489 		.start	= EP93XX_ETHERNET_PHYS_BASE,
490 		.end	= EP93XX_ETHERNET_PHYS_BASE + 0xffff,
491 		.flags	= IORESOURCE_MEM,
492 	}, {
493 		.start	= IRQ_EP93XX_ETHERNET,
494 		.end	= IRQ_EP93XX_ETHERNET,
495 		.flags	= IORESOURCE_IRQ,
496 	}
497 };
498 
499 static struct platform_device ep93xx_eth_device = {
500 	.name		= "ep93xx-eth",
501 	.id		= -1,
502 	.dev		= {
503 		.platform_data	= &ep93xx_eth_data,
504 	},
505 	.num_resources	= ARRAY_SIZE(ep93xx_eth_resource),
506 	.resource	= ep93xx_eth_resource,
507 };
508 
ep93xx_register_eth(struct ep93xx_eth_data * data,int copy_addr)509 void __init ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr)
510 {
511 	if (copy_addr) {
512 		memcpy(data->dev_addr,
513 			(void *)(EP93XX_ETHERNET_BASE + 0x50), 6);
514 	}
515 
516 	ep93xx_eth_data = *data;
517 	platform_device_register(&ep93xx_eth_device);
518 }
519 
520 static struct i2c_gpio_platform_data ep93xx_i2c_data = {
521 	.sda_pin		= EP93XX_GPIO_LINE_EEDAT,
522 	.sda_is_open_drain	= 0,
523 	.scl_pin		= EP93XX_GPIO_LINE_EECLK,
524 	.scl_is_open_drain	= 0,
525 	.udelay			= 2,
526 };
527 
528 static struct platform_device ep93xx_i2c_device = {
529 	.name			= "i2c-gpio",
530 	.id			= 0,
531 	.dev.platform_data	= &ep93xx_i2c_data,
532 };
533 
ep93xx_register_i2c(struct i2c_board_info * devices,int num)534 void __init ep93xx_register_i2c(struct i2c_board_info *devices, int num)
535 {
536 	i2c_register_board_info(0, devices, num);
537 	platform_device_register(&ep93xx_i2c_device);
538 }
539 
540 extern void ep93xx_gpio_init(void);
541 
ep93xx_init_devices(void)542 void __init ep93xx_init_devices(void)
543 {
544 	unsigned int v;
545 
546 	/*
547 	 * Disallow access to MaverickCrunch initially.
548 	 */
549 	v = __raw_readl(EP93XX_SYSCON_DEVICE_CONFIG);
550 	v &= ~EP93XX_SYSCON_DEVICE_CONFIG_CRUNCH_ENABLE;
551 	__raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
552 	__raw_writel(v, EP93XX_SYSCON_DEVICE_CONFIG);
553 
554 	ep93xx_gpio_init();
555 
556 	amba_device_register(&uart1_device, &iomem_resource);
557 	amba_device_register(&uart2_device, &iomem_resource);
558 	amba_device_register(&uart3_device, &iomem_resource);
559 
560 	platform_device_register(&ep93xx_rtc_device);
561 	platform_device_register(&ep93xx_ohci_device);
562 }
563