1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2007-2008 Solarflare Communications Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
8 */
9
10 #include <linux/delay.h>
11 #include <linux/seq_file.h>
12 #include "efx.h"
13 #include "mdio_10g.h"
14 #include "falcon.h"
15 #include "phy.h"
16 #include "falcon_hwdefs.h"
17 #include "boards.h"
18 #include "workarounds.h"
19 #include "selftest.h"
20
21 /* We expect these MMDs to be in the package. SFT9001 also has a
22 * clause 22 extension MMD, but since it doesn't have all the generic
23 * MMD registers it is pointless to include it here.
24 */
25 #define TENXPRESS_REQUIRED_DEVS (MDIO_MMDREG_DEVS_PMAPMD | \
26 MDIO_MMDREG_DEVS_PCS | \
27 MDIO_MMDREG_DEVS_PHYXS | \
28 MDIO_MMDREG_DEVS_AN)
29
30 #define SFX7101_LOOPBACKS ((1 << LOOPBACK_PHYXS) | \
31 (1 << LOOPBACK_PCS) | \
32 (1 << LOOPBACK_PMAPMD) | \
33 (1 << LOOPBACK_NETWORK))
34
35 #define SFT9001_LOOPBACKS ((1 << LOOPBACK_GPHY) | \
36 (1 << LOOPBACK_PHYXS) | \
37 (1 << LOOPBACK_PCS) | \
38 (1 << LOOPBACK_PMAPMD) | \
39 (1 << LOOPBACK_NETWORK))
40
41 /* We complain if we fail to see the link partner as 10G capable this many
42 * times in a row (must be > 1 as sampling the autoneg. registers is racy)
43 */
44 #define MAX_BAD_LP_TRIES (5)
45
46 /* LASI Control */
47 #define PMA_PMD_LASI_CTRL 36866
48 #define PMA_PMD_LASI_STATUS 36869
49 #define PMA_PMD_LS_ALARM_LBN 0
50 #define PMA_PMD_LS_ALARM_WIDTH 1
51 #define PMA_PMD_TX_ALARM_LBN 1
52 #define PMA_PMD_TX_ALARM_WIDTH 1
53 #define PMA_PMD_RX_ALARM_LBN 2
54 #define PMA_PMD_RX_ALARM_WIDTH 1
55 #define PMA_PMD_AN_ALARM_LBN 3
56 #define PMA_PMD_AN_ALARM_WIDTH 1
57
58 /* Extended control register */
59 #define PMA_PMD_XCONTROL_REG 49152
60 #define PMA_PMD_EXT_GMII_EN_LBN 1
61 #define PMA_PMD_EXT_GMII_EN_WIDTH 1
62 #define PMA_PMD_EXT_CLK_OUT_LBN 2
63 #define PMA_PMD_EXT_CLK_OUT_WIDTH 1
64 #define PMA_PMD_LNPGA_POWERDOWN_LBN 8 /* SFX7101 only */
65 #define PMA_PMD_LNPGA_POWERDOWN_WIDTH 1
66 #define PMA_PMD_EXT_CLK312_LBN 8 /* SFT9001 only */
67 #define PMA_PMD_EXT_CLK312_WIDTH 1
68 #define PMA_PMD_EXT_LPOWER_LBN 12
69 #define PMA_PMD_EXT_LPOWER_WIDTH 1
70 #define PMA_PMD_EXT_ROBUST_LBN 14
71 #define PMA_PMD_EXT_ROBUST_WIDTH 1
72 #define PMA_PMD_EXT_SSR_LBN 15
73 #define PMA_PMD_EXT_SSR_WIDTH 1
74
75 /* extended status register */
76 #define PMA_PMD_XSTATUS_REG 49153
77 #define PMA_PMD_XSTAT_FLP_LBN (12)
78
79 /* LED control register */
80 #define PMA_PMD_LED_CTRL_REG 49159
81 #define PMA_PMA_LED_ACTIVITY_LBN (3)
82
83 /* LED function override register */
84 #define PMA_PMD_LED_OVERR_REG 49161
85 /* Bit positions for different LEDs (there are more but not wired on SFE4001)*/
86 #define PMA_PMD_LED_LINK_LBN (0)
87 #define PMA_PMD_LED_SPEED_LBN (2)
88 #define PMA_PMD_LED_TX_LBN (4)
89 #define PMA_PMD_LED_RX_LBN (6)
90 /* Override settings */
91 #define PMA_PMD_LED_AUTO (0) /* H/W control */
92 #define PMA_PMD_LED_ON (1)
93 #define PMA_PMD_LED_OFF (2)
94 #define PMA_PMD_LED_FLASH (3)
95 #define PMA_PMD_LED_MASK 3
96 /* All LEDs under hardware control */
97 #define PMA_PMD_LED_FULL_AUTO (0)
98 /* Green and Amber under hardware control, Red off */
99 #define PMA_PMD_LED_DEFAULT (PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN)
100
101 #define PMA_PMD_SPEED_ENABLE_REG 49192
102 #define PMA_PMD_100TX_ADV_LBN 1
103 #define PMA_PMD_100TX_ADV_WIDTH 1
104 #define PMA_PMD_1000T_ADV_LBN 2
105 #define PMA_PMD_1000T_ADV_WIDTH 1
106 #define PMA_PMD_10000T_ADV_LBN 3
107 #define PMA_PMD_10000T_ADV_WIDTH 1
108 #define PMA_PMD_SPEED_LBN 4
109 #define PMA_PMD_SPEED_WIDTH 4
110
111 /* Cable diagnostics - SFT9001 only */
112 #define PMA_PMD_CDIAG_CTRL_REG 49213
113 #define CDIAG_CTRL_IMMED_LBN 15
114 #define CDIAG_CTRL_BRK_LINK_LBN 12
115 #define CDIAG_CTRL_IN_PROG_LBN 11
116 #define CDIAG_CTRL_LEN_UNIT_LBN 10
117 #define CDIAG_CTRL_LEN_METRES 1
118 #define PMA_PMD_CDIAG_RES_REG 49174
119 #define CDIAG_RES_A_LBN 12
120 #define CDIAG_RES_B_LBN 8
121 #define CDIAG_RES_C_LBN 4
122 #define CDIAG_RES_D_LBN 0
123 #define CDIAG_RES_WIDTH 4
124 #define CDIAG_RES_OPEN 2
125 #define CDIAG_RES_OK 1
126 #define CDIAG_RES_INVALID 0
127 /* Set of 4 registers for pairs A-D */
128 #define PMA_PMD_CDIAG_LEN_REG 49175
129
130 /* Serdes control registers - SFT9001 only */
131 #define PMA_PMD_CSERDES_CTRL_REG 64258
132 /* Set the 156.25 MHz output to 312.5 MHz to drive Falcon's XMAC */
133 #define PMA_PMD_CSERDES_DEFAULT 0x000f
134
135 /* Misc register defines - SFX7101 only */
136 #define PCS_CLOCK_CTRL_REG 55297
137 #define PLL312_RST_N_LBN 2
138
139 #define PCS_SOFT_RST2_REG 55302
140 #define SERDES_RST_N_LBN 13
141 #define XGXS_RST_N_LBN 12
142
143 #define PCS_TEST_SELECT_REG 55303 /* PRM 10.5.8 */
144 #define CLK312_EN_LBN 3
145
146 /* PHYXS registers */
147 #define PHYXS_XCONTROL_REG 49152
148 #define PHYXS_RESET_LBN 15
149 #define PHYXS_RESET_WIDTH 1
150
151 #define PHYXS_TEST1 (49162)
152 #define LOOPBACK_NEAR_LBN (8)
153 #define LOOPBACK_NEAR_WIDTH (1)
154
155 #define PCS_10GBASET_STAT1 32
156 #define PCS_10GBASET_BLKLK_LBN 0
157 #define PCS_10GBASET_BLKLK_WIDTH 1
158
159 /* Boot status register */
160 #define PCS_BOOT_STATUS_REG 53248
161 #define PCS_BOOT_FATAL_ERR_LBN (0)
162 #define PCS_BOOT_PROGRESS_LBN (1)
163 #define PCS_BOOT_PROGRESS_WIDTH (2)
164 #define PCS_BOOT_COMPLETE_LBN (3)
165
166 #define PCS_BOOT_MAX_DELAY (100)
167 #define PCS_BOOT_POLL_DELAY (10)
168
169 /* 100M/1G PHY registers */
170 #define GPHY_XCONTROL_REG 49152
171 #define GPHY_ISOLATE_LBN 10
172 #define GPHY_ISOLATE_WIDTH 1
173 #define GPHY_DUPLEX_LBN 8
174 #define GPHY_DUPLEX_WIDTH 1
175 #define GPHY_LOOPBACK_NEAR_LBN 14
176 #define GPHY_LOOPBACK_NEAR_WIDTH 1
177
178 #define C22EXT_STATUS_REG 49153
179 #define C22EXT_STATUS_LINK_LBN 2
180 #define C22EXT_STATUS_LINK_WIDTH 1
181
182 #define C22EXT_MSTSLV_CTRL 49161
183 #define C22EXT_MSTSLV_CTRL_ADV_1000_HD_LBN 8
184 #define C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN 9
185
186 #define C22EXT_MSTSLV_STATUS 49162
187 #define C22EXT_MSTSLV_STATUS_LP_1000_HD_LBN 10
188 #define C22EXT_MSTSLV_STATUS_LP_1000_FD_LBN 11
189
190 /* Time to wait between powering down the LNPGA and turning off the power
191 * rails */
192 #define LNPGA_PDOWN_WAIT (HZ / 5)
193
194 struct tenxpress_phy_data {
195 enum efx_loopback_mode loopback_mode;
196 enum efx_phy_mode phy_mode;
197 int bad_lp_tries;
198 };
199
show_phy_short_reach(struct device * dev,struct device_attribute * attr,char * buf)200 static ssize_t show_phy_short_reach(struct device *dev,
201 struct device_attribute *attr, char *buf)
202 {
203 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
204 int reg;
205
206 reg = mdio_clause45_read(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
207 MDIO_PMAPMD_10GBT_TXPWR);
208 return sprintf(buf, "%d\n",
209 !!(reg & (1 << MDIO_PMAPMD_10GBT_TXPWR_SHORT_LBN)));
210 }
211
set_phy_short_reach(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)212 static ssize_t set_phy_short_reach(struct device *dev,
213 struct device_attribute *attr,
214 const char *buf, size_t count)
215 {
216 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
217
218 rtnl_lock();
219 mdio_clause45_set_flag(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
220 MDIO_PMAPMD_10GBT_TXPWR,
221 MDIO_PMAPMD_10GBT_TXPWR_SHORT_LBN,
222 count != 0 && *buf != '0');
223 efx_reconfigure_port(efx);
224 rtnl_unlock();
225
226 return count;
227 }
228
229 static DEVICE_ATTR(phy_short_reach, 0644, show_phy_short_reach,
230 set_phy_short_reach);
231
232 /* Check that the C166 has booted successfully */
tenxpress_phy_check(struct efx_nic * efx)233 static int tenxpress_phy_check(struct efx_nic *efx)
234 {
235 int phy_id = efx->mii.phy_id;
236 int count = PCS_BOOT_MAX_DELAY / PCS_BOOT_POLL_DELAY;
237 int boot_stat;
238
239 /* Wait for the boot to complete (or not) */
240 while (count) {
241 boot_stat = mdio_clause45_read(efx, phy_id,
242 MDIO_MMD_PCS,
243 PCS_BOOT_STATUS_REG);
244 if (boot_stat & (1 << PCS_BOOT_COMPLETE_LBN))
245 break;
246 count--;
247 udelay(PCS_BOOT_POLL_DELAY);
248 }
249
250 if (!count) {
251 EFX_ERR(efx, "%s: PHY boot timed out. Last status "
252 "%x\n", __func__,
253 (boot_stat >> PCS_BOOT_PROGRESS_LBN) &
254 ((1 << PCS_BOOT_PROGRESS_WIDTH) - 1));
255 return -ETIMEDOUT;
256 }
257
258 return 0;
259 }
260
tenxpress_init(struct efx_nic * efx)261 static int tenxpress_init(struct efx_nic *efx)
262 {
263 int phy_id = efx->mii.phy_id;
264 int reg;
265 int rc;
266
267 if (efx->phy_type == PHY_TYPE_SFX7101) {
268 /* Enable 312.5 MHz clock */
269 mdio_clause45_write(efx, phy_id,
270 MDIO_MMD_PCS, PCS_TEST_SELECT_REG,
271 1 << CLK312_EN_LBN);
272 } else {
273 /* Enable 312.5 MHz clock and GMII */
274 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD,
275 PMA_PMD_XCONTROL_REG);
276 reg |= ((1 << PMA_PMD_EXT_GMII_EN_LBN) |
277 (1 << PMA_PMD_EXT_CLK_OUT_LBN) |
278 (1 << PMA_PMD_EXT_CLK312_LBN) |
279 (1 << PMA_PMD_EXT_ROBUST_LBN));
280
281 mdio_clause45_write(efx, phy_id, MDIO_MMD_PMAPMD,
282 PMA_PMD_XCONTROL_REG, reg);
283 mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_C22EXT,
284 GPHY_XCONTROL_REG, GPHY_ISOLATE_LBN,
285 false);
286 }
287
288 rc = tenxpress_phy_check(efx);
289 if (rc < 0)
290 return rc;
291
292 /* Set the LEDs up as: Green = Link, Amber = Link/Act, Red = Off */
293 if (efx->phy_type == PHY_TYPE_SFX7101) {
294 mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_PMAPMD,
295 PMA_PMD_LED_CTRL_REG,
296 PMA_PMA_LED_ACTIVITY_LBN,
297 true);
298 mdio_clause45_write(efx, phy_id, MDIO_MMD_PMAPMD,
299 PMA_PMD_LED_OVERR_REG, PMA_PMD_LED_DEFAULT);
300 }
301
302 return rc;
303 }
304
tenxpress_phy_init(struct efx_nic * efx)305 static int tenxpress_phy_init(struct efx_nic *efx)
306 {
307 struct tenxpress_phy_data *phy_data;
308 int rc = 0;
309
310 phy_data = kzalloc(sizeof(*phy_data), GFP_KERNEL);
311 if (!phy_data)
312 return -ENOMEM;
313 efx->phy_data = phy_data;
314 phy_data->phy_mode = efx->phy_mode;
315
316 if (!(efx->phy_mode & PHY_MODE_SPECIAL)) {
317 if (efx->phy_type == PHY_TYPE_SFT9001A) {
318 int reg;
319 reg = mdio_clause45_read(efx, efx->mii.phy_id,
320 MDIO_MMD_PMAPMD,
321 PMA_PMD_XCONTROL_REG);
322 reg |= (1 << PMA_PMD_EXT_SSR_LBN);
323 mdio_clause45_write(efx, efx->mii.phy_id,
324 MDIO_MMD_PMAPMD,
325 PMA_PMD_XCONTROL_REG, reg);
326 mdelay(200);
327 }
328
329 rc = mdio_clause45_wait_reset_mmds(efx,
330 TENXPRESS_REQUIRED_DEVS);
331 if (rc < 0)
332 goto fail;
333
334 rc = mdio_clause45_check_mmds(efx, TENXPRESS_REQUIRED_DEVS, 0);
335 if (rc < 0)
336 goto fail;
337 }
338
339 rc = tenxpress_init(efx);
340 if (rc < 0)
341 goto fail;
342 mdio_clause45_set_pause(efx);
343
344 if (efx->phy_type == PHY_TYPE_SFT9001B) {
345 rc = device_create_file(&efx->pci_dev->dev,
346 &dev_attr_phy_short_reach);
347 if (rc)
348 goto fail;
349 }
350
351 schedule_timeout_uninterruptible(HZ / 5); /* 200ms */
352
353 /* Let XGXS and SerDes out of reset */
354 falcon_reset_xaui(efx);
355
356 return 0;
357
358 fail:
359 kfree(efx->phy_data);
360 efx->phy_data = NULL;
361 return rc;
362 }
363
364 /* Perform a "special software reset" on the PHY. The caller is
365 * responsible for saving and restoring the PHY hardware registers
366 * properly, and masking/unmasking LASI */
tenxpress_special_reset(struct efx_nic * efx)367 static int tenxpress_special_reset(struct efx_nic *efx)
368 {
369 int rc, reg;
370
371 /* The XGMAC clock is driven from the SFC7101/SFT9001 312MHz clock, so
372 * a special software reset can glitch the XGMAC sufficiently for stats
373 * requests to fail. */
374 efx_stats_disable(efx);
375
376 /* Initiate reset */
377 reg = mdio_clause45_read(efx, efx->mii.phy_id,
378 MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG);
379 reg |= (1 << PMA_PMD_EXT_SSR_LBN);
380 mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
381 PMA_PMD_XCONTROL_REG, reg);
382
383 mdelay(200);
384
385 /* Wait for the blocks to come out of reset */
386 rc = mdio_clause45_wait_reset_mmds(efx,
387 TENXPRESS_REQUIRED_DEVS);
388 if (rc < 0)
389 goto out;
390
391 /* Try and reconfigure the device */
392 rc = tenxpress_init(efx);
393 if (rc < 0)
394 goto out;
395
396 /* Wait for the XGXS state machine to churn */
397 mdelay(10);
398 out:
399 efx_stats_enable(efx);
400 return rc;
401 }
402
sfx7101_check_bad_lp(struct efx_nic * efx,bool link_ok)403 static void sfx7101_check_bad_lp(struct efx_nic *efx, bool link_ok)
404 {
405 struct tenxpress_phy_data *pd = efx->phy_data;
406 int phy_id = efx->mii.phy_id;
407 bool bad_lp;
408 int reg;
409
410 if (link_ok) {
411 bad_lp = false;
412 } else {
413 /* Check that AN has started but not completed. */
414 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN,
415 MDIO_AN_STATUS);
416 if (!(reg & (1 << MDIO_AN_STATUS_LP_AN_CAP_LBN)))
417 return; /* LP status is unknown */
418 bad_lp = !(reg & (1 << MDIO_AN_STATUS_AN_DONE_LBN));
419 if (bad_lp)
420 pd->bad_lp_tries++;
421 }
422
423 /* Nothing to do if all is well and was previously so. */
424 if (!pd->bad_lp_tries)
425 return;
426
427 /* Use the RX (red) LED as an error indicator once we've seen AN
428 * failure several times in a row, and also log a message. */
429 if (!bad_lp || pd->bad_lp_tries == MAX_BAD_LP_TRIES) {
430 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD,
431 PMA_PMD_LED_OVERR_REG);
432 reg &= ~(PMA_PMD_LED_MASK << PMA_PMD_LED_RX_LBN);
433 if (!bad_lp) {
434 reg |= PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN;
435 } else {
436 reg |= PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN;
437 EFX_ERR(efx, "appears to be plugged into a port"
438 " that is not 10GBASE-T capable. The PHY"
439 " supports 10GBASE-T ONLY, so no link can"
440 " be established\n");
441 }
442 mdio_clause45_write(efx, phy_id, MDIO_MMD_PMAPMD,
443 PMA_PMD_LED_OVERR_REG, reg);
444 pd->bad_lp_tries = bad_lp;
445 }
446 }
447
sfx7101_link_ok(struct efx_nic * efx)448 static bool sfx7101_link_ok(struct efx_nic *efx)
449 {
450 return mdio_clause45_links_ok(efx,
451 MDIO_MMDREG_DEVS_PMAPMD |
452 MDIO_MMDREG_DEVS_PCS |
453 MDIO_MMDREG_DEVS_PHYXS);
454 }
455
sft9001_link_ok(struct efx_nic * efx,struct ethtool_cmd * ecmd)456 static bool sft9001_link_ok(struct efx_nic *efx, struct ethtool_cmd *ecmd)
457 {
458 int phy_id = efx->mii.phy_id;
459 u32 reg;
460
461 if (efx_phy_mode_disabled(efx->phy_mode))
462 return false;
463 else if (efx->loopback_mode == LOOPBACK_GPHY)
464 return true;
465 else if (efx->loopback_mode)
466 return mdio_clause45_links_ok(efx,
467 MDIO_MMDREG_DEVS_PMAPMD |
468 MDIO_MMDREG_DEVS_PHYXS);
469
470 /* We must use the same definition of link state as LASI,
471 * otherwise we can miss a link state transition
472 */
473 if (ecmd->speed == 10000) {
474 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PCS,
475 PCS_10GBASET_STAT1);
476 return reg & (1 << PCS_10GBASET_BLKLK_LBN);
477 } else {
478 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_C22EXT,
479 C22EXT_STATUS_REG);
480 return reg & (1 << C22EXT_STATUS_LINK_LBN);
481 }
482 }
483
tenxpress_ext_loopback(struct efx_nic * efx)484 static void tenxpress_ext_loopback(struct efx_nic *efx)
485 {
486 int phy_id = efx->mii.phy_id;
487
488 mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_PHYXS,
489 PHYXS_TEST1, LOOPBACK_NEAR_LBN,
490 efx->loopback_mode == LOOPBACK_PHYXS);
491 if (efx->phy_type != PHY_TYPE_SFX7101)
492 mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_C22EXT,
493 GPHY_XCONTROL_REG,
494 GPHY_LOOPBACK_NEAR_LBN,
495 efx->loopback_mode == LOOPBACK_GPHY);
496 }
497
tenxpress_low_power(struct efx_nic * efx)498 static void tenxpress_low_power(struct efx_nic *efx)
499 {
500 int phy_id = efx->mii.phy_id;
501
502 if (efx->phy_type == PHY_TYPE_SFX7101)
503 mdio_clause45_set_mmds_lpower(
504 efx, !!(efx->phy_mode & PHY_MODE_LOW_POWER),
505 TENXPRESS_REQUIRED_DEVS);
506 else
507 mdio_clause45_set_flag(
508 efx, phy_id, MDIO_MMD_PMAPMD,
509 PMA_PMD_XCONTROL_REG, PMA_PMD_EXT_LPOWER_LBN,
510 !!(efx->phy_mode & PHY_MODE_LOW_POWER));
511 }
512
tenxpress_phy_reconfigure(struct efx_nic * efx)513 static void tenxpress_phy_reconfigure(struct efx_nic *efx)
514 {
515 struct tenxpress_phy_data *phy_data = efx->phy_data;
516 struct ethtool_cmd ecmd;
517 bool phy_mode_change, loop_reset;
518
519 if (efx->phy_mode & (PHY_MODE_OFF | PHY_MODE_SPECIAL)) {
520 phy_data->phy_mode = efx->phy_mode;
521 return;
522 }
523
524 tenxpress_low_power(efx);
525
526 phy_mode_change = (efx->phy_mode == PHY_MODE_NORMAL &&
527 phy_data->phy_mode != PHY_MODE_NORMAL);
528 loop_reset = (LOOPBACK_OUT_OF(phy_data, efx, efx->phy_op->loopbacks) ||
529 LOOPBACK_CHANGED(phy_data, efx, 1 << LOOPBACK_GPHY));
530
531 if (loop_reset || phy_mode_change) {
532 int rc;
533
534 efx->phy_op->get_settings(efx, &ecmd);
535
536 if (loop_reset || phy_mode_change) {
537 tenxpress_special_reset(efx);
538
539 /* Reset XAUI if we were in 10G, and are staying
540 * in 10G. If we're moving into and out of 10G
541 * then xaui will be reset anyway */
542 if (EFX_IS10G(efx))
543 falcon_reset_xaui(efx);
544 }
545
546 rc = efx->phy_op->set_settings(efx, &ecmd);
547 WARN_ON(rc);
548 }
549
550 mdio_clause45_transmit_disable(efx);
551 mdio_clause45_phy_reconfigure(efx);
552 tenxpress_ext_loopback(efx);
553
554 phy_data->loopback_mode = efx->loopback_mode;
555 phy_data->phy_mode = efx->phy_mode;
556
557 if (efx->phy_type == PHY_TYPE_SFX7101) {
558 efx->link_speed = 10000;
559 efx->link_fd = true;
560 efx->link_up = sfx7101_link_ok(efx);
561 } else {
562 efx->phy_op->get_settings(efx, &ecmd);
563 efx->link_speed = ecmd.speed;
564 efx->link_fd = ecmd.duplex == DUPLEX_FULL;
565 efx->link_up = sft9001_link_ok(efx, &ecmd);
566 }
567 efx->link_fc = mdio_clause45_get_pause(efx);
568 }
569
570 /* Poll PHY for interrupt */
tenxpress_phy_poll(struct efx_nic * efx)571 static void tenxpress_phy_poll(struct efx_nic *efx)
572 {
573 struct tenxpress_phy_data *phy_data = efx->phy_data;
574 bool change = false, link_ok;
575 unsigned link_fc;
576
577 if (efx->phy_type == PHY_TYPE_SFX7101) {
578 link_ok = sfx7101_link_ok(efx);
579 if (link_ok != efx->link_up) {
580 change = true;
581 } else {
582 link_fc = mdio_clause45_get_pause(efx);
583 if (link_fc != efx->link_fc)
584 change = true;
585 }
586 sfx7101_check_bad_lp(efx, link_ok);
587 } else if (efx->loopback_mode) {
588 bool link_ok = sft9001_link_ok(efx, NULL);
589 if (link_ok != efx->link_up)
590 change = true;
591 } else {
592 u32 status = mdio_clause45_read(efx, efx->mii.phy_id,
593 MDIO_MMD_PMAPMD,
594 PMA_PMD_LASI_STATUS);
595 if (status & (1 << PMA_PMD_LS_ALARM_LBN))
596 change = true;
597 }
598
599 if (change)
600 falcon_sim_phy_event(efx);
601
602 if (phy_data->phy_mode != PHY_MODE_NORMAL)
603 return;
604 }
605
tenxpress_phy_fini(struct efx_nic * efx)606 static void tenxpress_phy_fini(struct efx_nic *efx)
607 {
608 int reg;
609
610 if (efx->phy_type == PHY_TYPE_SFT9001B)
611 device_remove_file(&efx->pci_dev->dev,
612 &dev_attr_phy_short_reach);
613
614 if (efx->phy_type == PHY_TYPE_SFX7101) {
615 /* Power down the LNPGA */
616 reg = (1 << PMA_PMD_LNPGA_POWERDOWN_LBN);
617 mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
618 PMA_PMD_XCONTROL_REG, reg);
619
620 /* Waiting here ensures that the board fini, which can turn
621 * off the power to the PHY, won't get run until the LNPGA
622 * powerdown has been given long enough to complete. */
623 schedule_timeout_uninterruptible(LNPGA_PDOWN_WAIT); /* 200 ms */
624 }
625
626 kfree(efx->phy_data);
627 efx->phy_data = NULL;
628 }
629
630
631 /* Set the RX and TX LEDs and Link LED flashing. The other LEDs
632 * (which probably aren't wired anyway) are left in AUTO mode */
tenxpress_phy_blink(struct efx_nic * efx,bool blink)633 void tenxpress_phy_blink(struct efx_nic *efx, bool blink)
634 {
635 int reg;
636
637 if (blink)
638 reg = (PMA_PMD_LED_FLASH << PMA_PMD_LED_TX_LBN) |
639 (PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN) |
640 (PMA_PMD_LED_FLASH << PMA_PMD_LED_LINK_LBN);
641 else
642 reg = PMA_PMD_LED_DEFAULT;
643
644 mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
645 PMA_PMD_LED_OVERR_REG, reg);
646 }
647
648 static const char *const sfx7101_test_names[] = {
649 "bist"
650 };
651
652 static int
sfx7101_run_tests(struct efx_nic * efx,int * results,unsigned flags)653 sfx7101_run_tests(struct efx_nic *efx, int *results, unsigned flags)
654 {
655 int rc;
656
657 if (!(flags & ETH_TEST_FL_OFFLINE))
658 return 0;
659
660 /* BIST is automatically run after a special software reset */
661 rc = tenxpress_special_reset(efx);
662 results[0] = rc ? -1 : 1;
663 return rc;
664 }
665
666 static const char *const sft9001_test_names[] = {
667 "bist",
668 "cable.pairA.status",
669 "cable.pairB.status",
670 "cable.pairC.status",
671 "cable.pairD.status",
672 "cable.pairA.length",
673 "cable.pairB.length",
674 "cable.pairC.length",
675 "cable.pairD.length",
676 };
677
sft9001_run_tests(struct efx_nic * efx,int * results,unsigned flags)678 static int sft9001_run_tests(struct efx_nic *efx, int *results, unsigned flags)
679 {
680 struct ethtool_cmd ecmd;
681 int phy_id = efx->mii.phy_id;
682 int rc = 0, rc2, i, res_reg;
683
684 if (!(flags & ETH_TEST_FL_OFFLINE))
685 return 0;
686
687 efx->phy_op->get_settings(efx, &ecmd);
688
689 /* Initialise cable diagnostic results to unknown failure */
690 for (i = 1; i < 9; ++i)
691 results[i] = -1;
692
693 /* Run cable diagnostics; wait up to 5 seconds for them to complete.
694 * A cable fault is not a self-test failure, but a timeout is. */
695 mdio_clause45_write(efx, phy_id, MDIO_MMD_PMAPMD,
696 PMA_PMD_CDIAG_CTRL_REG,
697 (1 << CDIAG_CTRL_IMMED_LBN) |
698 (1 << CDIAG_CTRL_BRK_LINK_LBN) |
699 (CDIAG_CTRL_LEN_METRES << CDIAG_CTRL_LEN_UNIT_LBN));
700 i = 0;
701 while (mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD,
702 PMA_PMD_CDIAG_CTRL_REG) &
703 (1 << CDIAG_CTRL_IN_PROG_LBN)) {
704 if (++i == 50) {
705 rc = -ETIMEDOUT;
706 goto reset;
707 }
708 msleep(100);
709 }
710 res_reg = mdio_clause45_read(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
711 PMA_PMD_CDIAG_RES_REG);
712 for (i = 0; i < 4; i++) {
713 int pair_res =
714 (res_reg >> (CDIAG_RES_A_LBN - i * CDIAG_RES_WIDTH))
715 & ((1 << CDIAG_RES_WIDTH) - 1);
716 int len_reg = mdio_clause45_read(efx, efx->mii.phy_id,
717 MDIO_MMD_PMAPMD,
718 PMA_PMD_CDIAG_LEN_REG + i);
719 if (pair_res == CDIAG_RES_OK)
720 results[1 + i] = 1;
721 else if (pair_res == CDIAG_RES_INVALID)
722 results[1 + i] = -1;
723 else
724 results[1 + i] = -pair_res;
725 if (pair_res != CDIAG_RES_INVALID &&
726 pair_res != CDIAG_RES_OPEN &&
727 len_reg != 0xffff)
728 results[5 + i] = len_reg;
729 }
730
731 /* We must reset to exit cable diagnostic mode. The BIST will
732 * also run when we do this. */
733 reset:
734 rc2 = tenxpress_special_reset(efx);
735 results[0] = rc2 ? -1 : 1;
736 if (!rc)
737 rc = rc2;
738
739 rc2 = efx->phy_op->set_settings(efx, &ecmd);
740 if (!rc)
741 rc = rc2;
742
743 return rc;
744 }
745
746 static void
tenxpress_get_settings(struct efx_nic * efx,struct ethtool_cmd * ecmd)747 tenxpress_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
748 {
749 int phy_id = efx->mii.phy_id;
750 u32 adv = 0, lpa = 0;
751 int reg;
752
753 if (efx->phy_type != PHY_TYPE_SFX7101) {
754 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_C22EXT,
755 C22EXT_MSTSLV_CTRL);
756 if (reg & (1 << C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN))
757 adv |= ADVERTISED_1000baseT_Full;
758 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_C22EXT,
759 C22EXT_MSTSLV_STATUS);
760 if (reg & (1 << C22EXT_MSTSLV_STATUS_LP_1000_HD_LBN))
761 lpa |= ADVERTISED_1000baseT_Half;
762 if (reg & (1 << C22EXT_MSTSLV_STATUS_LP_1000_FD_LBN))
763 lpa |= ADVERTISED_1000baseT_Full;
764 }
765 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN,
766 MDIO_AN_10GBT_CTRL);
767 if (reg & (1 << MDIO_AN_10GBT_CTRL_ADV_10G_LBN))
768 adv |= ADVERTISED_10000baseT_Full;
769 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN,
770 MDIO_AN_10GBT_STATUS);
771 if (reg & (1 << MDIO_AN_10GBT_STATUS_LP_10G_LBN))
772 lpa |= ADVERTISED_10000baseT_Full;
773
774 mdio_clause45_get_settings_ext(efx, ecmd, adv, lpa);
775
776 if (efx->phy_type != PHY_TYPE_SFX7101)
777 ecmd->supported |= (SUPPORTED_100baseT_Full |
778 SUPPORTED_1000baseT_Full);
779
780 /* In loopback, the PHY automatically brings up the correct interface,
781 * but doesn't advertise the correct speed. So override it */
782 if (efx->loopback_mode == LOOPBACK_GPHY)
783 ecmd->speed = SPEED_1000;
784 else if (LOOPBACK_MASK(efx) & efx->phy_op->loopbacks)
785 ecmd->speed = SPEED_10000;
786 }
787
tenxpress_set_settings(struct efx_nic * efx,struct ethtool_cmd * ecmd)788 static int tenxpress_set_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
789 {
790 if (!ecmd->autoneg)
791 return -EINVAL;
792
793 return mdio_clause45_set_settings(efx, ecmd);
794 }
795
sfx7101_set_npage_adv(struct efx_nic * efx,u32 advertising)796 static void sfx7101_set_npage_adv(struct efx_nic *efx, u32 advertising)
797 {
798 mdio_clause45_set_flag(efx, efx->mii.phy_id, MDIO_MMD_AN,
799 MDIO_AN_10GBT_CTRL,
800 MDIO_AN_10GBT_CTRL_ADV_10G_LBN,
801 advertising & ADVERTISED_10000baseT_Full);
802 }
803
sft9001_set_npage_adv(struct efx_nic * efx,u32 advertising)804 static void sft9001_set_npage_adv(struct efx_nic *efx, u32 advertising)
805 {
806 int phy_id = efx->mii.phy_id;
807
808 mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_C22EXT,
809 C22EXT_MSTSLV_CTRL,
810 C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN,
811 advertising & ADVERTISED_1000baseT_Full);
812 mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_AN,
813 MDIO_AN_10GBT_CTRL,
814 MDIO_AN_10GBT_CTRL_ADV_10G_LBN,
815 advertising & ADVERTISED_10000baseT_Full);
816 }
817
818 struct efx_phy_operations falcon_sfx7101_phy_ops = {
819 .macs = EFX_XMAC,
820 .init = tenxpress_phy_init,
821 .reconfigure = tenxpress_phy_reconfigure,
822 .poll = tenxpress_phy_poll,
823 .fini = tenxpress_phy_fini,
824 .clear_interrupt = efx_port_dummy_op_void,
825 .get_settings = tenxpress_get_settings,
826 .set_settings = tenxpress_set_settings,
827 .set_npage_adv = sfx7101_set_npage_adv,
828 .num_tests = ARRAY_SIZE(sfx7101_test_names),
829 .test_names = sfx7101_test_names,
830 .run_tests = sfx7101_run_tests,
831 .mmds = TENXPRESS_REQUIRED_DEVS,
832 .loopbacks = SFX7101_LOOPBACKS,
833 };
834
835 struct efx_phy_operations falcon_sft9001_phy_ops = {
836 .macs = EFX_GMAC | EFX_XMAC,
837 .init = tenxpress_phy_init,
838 .reconfigure = tenxpress_phy_reconfigure,
839 .poll = tenxpress_phy_poll,
840 .fini = tenxpress_phy_fini,
841 .clear_interrupt = efx_port_dummy_op_void,
842 .get_settings = tenxpress_get_settings,
843 .set_settings = tenxpress_set_settings,
844 .set_npage_adv = sft9001_set_npage_adv,
845 .num_tests = ARRAY_SIZE(sft9001_test_names),
846 .test_names = sft9001_test_names,
847 .run_tests = sft9001_run_tests,
848 .mmds = TENXPRESS_REQUIRED_DEVS,
849 .loopbacks = SFT9001_LOOPBACKS,
850 };
851