1 /* 2 * Copyright (c) 2006 - 2008 NetEffect, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef __NES_HW_H 34 #define __NES_HW_H 35 36 #include <linux/inet_lro.h> 37 38 #define NES_PHY_TYPE_1G 2 39 #define NES_PHY_TYPE_IRIS 3 40 #define NES_PHY_TYPE_ARGUS 4 41 #define NES_PHY_TYPE_PUMA_1G 5 42 #define NES_PHY_TYPE_PUMA_10G 6 43 #define NES_PHY_TYPE_GLADIUS 7 44 45 #define NES_MULTICAST_PF_MAX 8 46 47 enum pci_regs { 48 NES_INT_STAT = 0x0000, 49 NES_INT_MASK = 0x0004, 50 NES_INT_PENDING = 0x0008, 51 NES_INTF_INT_STAT = 0x000C, 52 NES_INTF_INT_MASK = 0x0010, 53 NES_TIMER_STAT = 0x0014, 54 NES_PERIODIC_CONTROL = 0x0018, 55 NES_ONE_SHOT_CONTROL = 0x001C, 56 NES_EEPROM_COMMAND = 0x0020, 57 NES_EEPROM_DATA = 0x0024, 58 NES_FLASH_COMMAND = 0x0028, 59 NES_FLASH_DATA = 0x002C, 60 NES_SOFTWARE_RESET = 0x0030, 61 NES_CQ_ACK = 0x0034, 62 NES_WQE_ALLOC = 0x0040, 63 NES_CQE_ALLOC = 0x0044, 64 }; 65 66 enum indexed_regs { 67 NES_IDX_CREATE_CQP_LOW = 0x0000, 68 NES_IDX_CREATE_CQP_HIGH = 0x0004, 69 NES_IDX_QP_CONTROL = 0x0040, 70 NES_IDX_FLM_CONTROL = 0x0080, 71 NES_IDX_INT_CPU_STATUS = 0x00a0, 72 NES_IDX_GPIO_CONTROL = 0x00f0, 73 NES_IDX_GPIO_DATA = 0x00f4, 74 NES_IDX_TCP_CONFIG0 = 0x01e4, 75 NES_IDX_TCP_TIMER_CONFIG = 0x01ec, 76 NES_IDX_TCP_NOW = 0x01f0, 77 NES_IDX_QP_MAX_CFG_SIZES = 0x0200, 78 NES_IDX_QP_CTX_SIZE = 0x0218, 79 NES_IDX_TCP_TIMER_SIZE0 = 0x0238, 80 NES_IDX_TCP_TIMER_SIZE1 = 0x0240, 81 NES_IDX_ARP_CACHE_SIZE = 0x0258, 82 NES_IDX_CQ_CTX_SIZE = 0x0260, 83 NES_IDX_MRT_SIZE = 0x0278, 84 NES_IDX_PBL_REGION_SIZE = 0x0280, 85 NES_IDX_IRRQ_COUNT = 0x02b0, 86 NES_IDX_RX_WINDOW_BUFFER_PAGE_TABLE_SIZE = 0x02f0, 87 NES_IDX_RX_WINDOW_BUFFER_SIZE = 0x0300, 88 NES_IDX_DST_IP_ADDR = 0x0400, 89 NES_IDX_PCIX_DIAG = 0x08e8, 90 NES_IDX_MPP_DEBUG = 0x0a00, 91 NES_IDX_PORT_RX_DISCARDS = 0x0a30, 92 NES_IDX_PORT_TX_DISCARDS = 0x0a34, 93 NES_IDX_MPP_LB_DEBUG = 0x0b00, 94 NES_IDX_DENALI_CTL_22 = 0x1058, 95 NES_IDX_MAC_TX_CONTROL = 0x2000, 96 NES_IDX_MAC_TX_CONFIG = 0x2004, 97 NES_IDX_MAC_TX_PAUSE_QUANTA = 0x2008, 98 NES_IDX_MAC_RX_CONTROL = 0x200c, 99 NES_IDX_MAC_RX_CONFIG = 0x2010, 100 NES_IDX_MAC_EXACT_MATCH_BOTTOM = 0x201c, 101 NES_IDX_MAC_MDIO_CONTROL = 0x2084, 102 NES_IDX_MAC_TX_OCTETS_LOW = 0x2100, 103 NES_IDX_MAC_TX_OCTETS_HIGH = 0x2104, 104 NES_IDX_MAC_TX_FRAMES_LOW = 0x2108, 105 NES_IDX_MAC_TX_FRAMES_HIGH = 0x210c, 106 NES_IDX_MAC_TX_PAUSE_FRAMES = 0x2118, 107 NES_IDX_MAC_TX_ERRORS = 0x2138, 108 NES_IDX_MAC_RX_OCTETS_LOW = 0x213c, 109 NES_IDX_MAC_RX_OCTETS_HIGH = 0x2140, 110 NES_IDX_MAC_RX_FRAMES_LOW = 0x2144, 111 NES_IDX_MAC_RX_FRAMES_HIGH = 0x2148, 112 NES_IDX_MAC_RX_BC_FRAMES_LOW = 0x214c, 113 NES_IDX_MAC_RX_MC_FRAMES_HIGH = 0x2150, 114 NES_IDX_MAC_RX_PAUSE_FRAMES = 0x2154, 115 NES_IDX_MAC_RX_SHORT_FRAMES = 0x2174, 116 NES_IDX_MAC_RX_OVERSIZED_FRAMES = 0x2178, 117 NES_IDX_MAC_RX_JABBER_FRAMES = 0x217c, 118 NES_IDX_MAC_RX_CRC_ERR_FRAMES = 0x2180, 119 NES_IDX_MAC_RX_LENGTH_ERR_FRAMES = 0x2184, 120 NES_IDX_MAC_RX_SYMBOL_ERR_FRAMES = 0x2188, 121 NES_IDX_MAC_INT_STATUS = 0x21f0, 122 NES_IDX_MAC_INT_MASK = 0x21f4, 123 NES_IDX_PHY_PCS_CONTROL_STATUS0 = 0x2800, 124 NES_IDX_PHY_PCS_CONTROL_STATUS1 = 0x2a00, 125 NES_IDX_ETH_SERDES_COMMON_CONTROL0 = 0x2808, 126 NES_IDX_ETH_SERDES_COMMON_CONTROL1 = 0x2a08, 127 NES_IDX_ETH_SERDES_COMMON_STATUS0 = 0x280c, 128 NES_IDX_ETH_SERDES_COMMON_STATUS1 = 0x2a0c, 129 NES_IDX_ETH_SERDES_TX_EMP0 = 0x2810, 130 NES_IDX_ETH_SERDES_TX_EMP1 = 0x2a10, 131 NES_IDX_ETH_SERDES_TX_DRIVE0 = 0x2814, 132 NES_IDX_ETH_SERDES_TX_DRIVE1 = 0x2a14, 133 NES_IDX_ETH_SERDES_RX_MODE0 = 0x2818, 134 NES_IDX_ETH_SERDES_RX_MODE1 = 0x2a18, 135 NES_IDX_ETH_SERDES_RX_SIGDET0 = 0x281c, 136 NES_IDX_ETH_SERDES_RX_SIGDET1 = 0x2a1c, 137 NES_IDX_ETH_SERDES_BYPASS0 = 0x2820, 138 NES_IDX_ETH_SERDES_BYPASS1 = 0x2a20, 139 NES_IDX_ETH_SERDES_LOOPBACK_CONTROL0 = 0x2824, 140 NES_IDX_ETH_SERDES_LOOPBACK_CONTROL1 = 0x2a24, 141 NES_IDX_ETH_SERDES_RX_EQ_CONTROL0 = 0x2828, 142 NES_IDX_ETH_SERDES_RX_EQ_CONTROL1 = 0x2a28, 143 NES_IDX_ETH_SERDES_RX_EQ_STATUS0 = 0x282c, 144 NES_IDX_ETH_SERDES_RX_EQ_STATUS1 = 0x2a2c, 145 NES_IDX_ETH_SERDES_CDR_RESET0 = 0x2830, 146 NES_IDX_ETH_SERDES_CDR_RESET1 = 0x2a30, 147 NES_IDX_ETH_SERDES_CDR_CONTROL0 = 0x2834, 148 NES_IDX_ETH_SERDES_CDR_CONTROL1 = 0x2a34, 149 NES_IDX_ETH_SERDES_TX_HIGHZ_LANE_MODE0 = 0x2838, 150 NES_IDX_ETH_SERDES_TX_HIGHZ_LANE_MODE1 = 0x2a38, 151 NES_IDX_ENDNODE0_NSTAT_RX_DISCARD = 0x3080, 152 NES_IDX_ENDNODE0_NSTAT_RX_OCTETS_LO = 0x3000, 153 NES_IDX_ENDNODE0_NSTAT_RX_OCTETS_HI = 0x3004, 154 NES_IDX_ENDNODE0_NSTAT_RX_FRAMES_LO = 0x3008, 155 NES_IDX_ENDNODE0_NSTAT_RX_FRAMES_HI = 0x300c, 156 NES_IDX_ENDNODE0_NSTAT_TX_OCTETS_LO = 0x7000, 157 NES_IDX_ENDNODE0_NSTAT_TX_OCTETS_HI = 0x7004, 158 NES_IDX_ENDNODE0_NSTAT_TX_FRAMES_LO = 0x7008, 159 NES_IDX_ENDNODE0_NSTAT_TX_FRAMES_HI = 0x700c, 160 NES_IDX_WQM_CONFIG1 = 0x5004, 161 NES_IDX_CM_CONFIG = 0x5100, 162 NES_IDX_NIC_LOGPORT_TO_PHYPORT = 0x6000, 163 NES_IDX_NIC_PHYPORT_TO_USW = 0x6008, 164 NES_IDX_NIC_ACTIVE = 0x6010, 165 NES_IDX_NIC_UNICAST_ALL = 0x6018, 166 NES_IDX_NIC_MULTICAST_ALL = 0x6020, 167 NES_IDX_NIC_MULTICAST_ENABLE = 0x6028, 168 NES_IDX_NIC_BROADCAST_ON = 0x6030, 169 NES_IDX_USED_CHUNKS_TX = 0x60b0, 170 NES_IDX_TX_POOL_SIZE = 0x60b8, 171 NES_IDX_QUAD_HASH_TABLE_SIZE = 0x6148, 172 NES_IDX_PERFECT_FILTER_LOW = 0x6200, 173 NES_IDX_PERFECT_FILTER_HIGH = 0x6204, 174 NES_IDX_IPV4_TCP_REXMITS = 0x7080, 175 NES_IDX_DEBUG_ERROR_CONTROL_STATUS = 0x913c, 176 NES_IDX_DEBUG_ERROR_MASKS0 = 0x9140, 177 NES_IDX_DEBUG_ERROR_MASKS1 = 0x9144, 178 NES_IDX_DEBUG_ERROR_MASKS2 = 0x9148, 179 NES_IDX_DEBUG_ERROR_MASKS3 = 0x914c, 180 NES_IDX_DEBUG_ERROR_MASKS4 = 0x9150, 181 NES_IDX_DEBUG_ERROR_MASKS5 = 0x9154, 182 }; 183 184 #define NES_IDX_MAC_TX_CONFIG_ENABLE_PAUSE 1 185 #define NES_IDX_MPP_DEBUG_PORT_DISABLE_PAUSE (1 << 17) 186 187 enum nes_cqp_opcodes { 188 NES_CQP_CREATE_QP = 0x00, 189 NES_CQP_MODIFY_QP = 0x01, 190 NES_CQP_DESTROY_QP = 0x02, 191 NES_CQP_CREATE_CQ = 0x03, 192 NES_CQP_MODIFY_CQ = 0x04, 193 NES_CQP_DESTROY_CQ = 0x05, 194 NES_CQP_ALLOCATE_STAG = 0x09, 195 NES_CQP_REGISTER_STAG = 0x0a, 196 NES_CQP_QUERY_STAG = 0x0b, 197 NES_CQP_REGISTER_SHARED_STAG = 0x0c, 198 NES_CQP_DEALLOCATE_STAG = 0x0d, 199 NES_CQP_MANAGE_ARP_CACHE = 0x0f, 200 NES_CQP_SUSPEND_QPS = 0x11, 201 NES_CQP_UPLOAD_CONTEXT = 0x13, 202 NES_CQP_CREATE_CEQ = 0x16, 203 NES_CQP_DESTROY_CEQ = 0x18, 204 NES_CQP_CREATE_AEQ = 0x19, 205 NES_CQP_DESTROY_AEQ = 0x1b, 206 NES_CQP_LMI_ACCESS = 0x20, 207 NES_CQP_FLUSH_WQES = 0x22, 208 NES_CQP_MANAGE_APBVT = 0x23 209 }; 210 211 enum nes_cqp_wqe_word_idx { 212 NES_CQP_WQE_OPCODE_IDX = 0, 213 NES_CQP_WQE_ID_IDX = 1, 214 NES_CQP_WQE_COMP_CTX_LOW_IDX = 2, 215 NES_CQP_WQE_COMP_CTX_HIGH_IDX = 3, 216 NES_CQP_WQE_COMP_SCRATCH_LOW_IDX = 4, 217 NES_CQP_WQE_COMP_SCRATCH_HIGH_IDX = 5, 218 }; 219 220 enum nes_cqp_cq_wqeword_idx { 221 NES_CQP_CQ_WQE_PBL_LOW_IDX = 6, 222 NES_CQP_CQ_WQE_PBL_HIGH_IDX = 7, 223 NES_CQP_CQ_WQE_CQ_CONTEXT_LOW_IDX = 8, 224 NES_CQP_CQ_WQE_CQ_CONTEXT_HIGH_IDX = 9, 225 NES_CQP_CQ_WQE_DOORBELL_INDEX_HIGH_IDX = 10, 226 }; 227 228 enum nes_cqp_stag_wqeword_idx { 229 NES_CQP_STAG_WQE_PBL_BLK_COUNT_IDX = 1, 230 NES_CQP_STAG_WQE_LEN_HIGH_PD_IDX = 6, 231 NES_CQP_STAG_WQE_LEN_LOW_IDX = 7, 232 NES_CQP_STAG_WQE_STAG_IDX = 8, 233 NES_CQP_STAG_WQE_VA_LOW_IDX = 10, 234 NES_CQP_STAG_WQE_VA_HIGH_IDX = 11, 235 NES_CQP_STAG_WQE_PA_LOW_IDX = 12, 236 NES_CQP_STAG_WQE_PA_HIGH_IDX = 13, 237 NES_CQP_STAG_WQE_PBL_LEN_IDX = 14 238 }; 239 240 #define NES_CQP_OP_IWARP_STATE_SHIFT 28 241 242 enum nes_cqp_qp_bits { 243 NES_CQP_QP_ARP_VALID = (1<<8), 244 NES_CQP_QP_WINBUF_VALID = (1<<9), 245 NES_CQP_QP_CONTEXT_VALID = (1<<10), 246 NES_CQP_QP_ORD_VALID = (1<<11), 247 NES_CQP_QP_WINBUF_DATAIND_EN = (1<<12), 248 NES_CQP_QP_VIRT_WQS = (1<<13), 249 NES_CQP_QP_DEL_HTE = (1<<14), 250 NES_CQP_QP_CQS_VALID = (1<<15), 251 NES_CQP_QP_TYPE_TSA = 0, 252 NES_CQP_QP_TYPE_IWARP = (1<<16), 253 NES_CQP_QP_TYPE_CQP = (4<<16), 254 NES_CQP_QP_TYPE_NIC = (5<<16), 255 NES_CQP_QP_MSS_CHG = (1<<20), 256 NES_CQP_QP_STATIC_RESOURCES = (1<<21), 257 NES_CQP_QP_IGNORE_MW_BOUND = (1<<22), 258 NES_CQP_QP_VWQ_USE_LMI = (1<<23), 259 NES_CQP_QP_IWARP_STATE_IDLE = (1<<NES_CQP_OP_IWARP_STATE_SHIFT), 260 NES_CQP_QP_IWARP_STATE_RTS = (2<<NES_CQP_OP_IWARP_STATE_SHIFT), 261 NES_CQP_QP_IWARP_STATE_CLOSING = (3<<NES_CQP_OP_IWARP_STATE_SHIFT), 262 NES_CQP_QP_IWARP_STATE_TERMINATE = (5<<NES_CQP_OP_IWARP_STATE_SHIFT), 263 NES_CQP_QP_IWARP_STATE_ERROR = (6<<NES_CQP_OP_IWARP_STATE_SHIFT), 264 NES_CQP_QP_IWARP_STATE_MASK = (7<<NES_CQP_OP_IWARP_STATE_SHIFT), 265 NES_CQP_QP_RESET = (1<<31), 266 }; 267 268 enum nes_cqp_qp_wqe_word_idx { 269 NES_CQP_QP_WQE_CONTEXT_LOW_IDX = 6, 270 NES_CQP_QP_WQE_CONTEXT_HIGH_IDX = 7, 271 NES_CQP_QP_WQE_NEW_MSS_IDX = 15, 272 }; 273 274 enum nes_nic_ctx_bits { 275 NES_NIC_CTX_RQ_SIZE_32 = (3<<8), 276 NES_NIC_CTX_RQ_SIZE_512 = (3<<8), 277 NES_NIC_CTX_SQ_SIZE_32 = (1<<10), 278 NES_NIC_CTX_SQ_SIZE_512 = (3<<10), 279 }; 280 281 enum nes_nic_qp_ctx_word_idx { 282 NES_NIC_CTX_MISC_IDX = 0, 283 NES_NIC_CTX_SQ_LOW_IDX = 2, 284 NES_NIC_CTX_SQ_HIGH_IDX = 3, 285 NES_NIC_CTX_RQ_LOW_IDX = 4, 286 NES_NIC_CTX_RQ_HIGH_IDX = 5, 287 }; 288 289 enum nes_cqp_cq_bits { 290 NES_CQP_CQ_CEQE_MASK = (1<<9), 291 NES_CQP_CQ_CEQ_VALID = (1<<10), 292 NES_CQP_CQ_RESIZE = (1<<11), 293 NES_CQP_CQ_CHK_OVERFLOW = (1<<12), 294 NES_CQP_CQ_4KB_CHUNK = (1<<14), 295 NES_CQP_CQ_VIRT = (1<<15), 296 }; 297 298 enum nes_cqp_stag_bits { 299 NES_CQP_STAG_VA_TO = (1<<9), 300 NES_CQP_STAG_DEALLOC_PBLS = (1<<10), 301 NES_CQP_STAG_PBL_BLK_SIZE = (1<<11), 302 NES_CQP_STAG_MR = (1<<13), 303 NES_CQP_STAG_RIGHTS_LOCAL_READ = (1<<16), 304 NES_CQP_STAG_RIGHTS_LOCAL_WRITE = (1<<17), 305 NES_CQP_STAG_RIGHTS_REMOTE_READ = (1<<18), 306 NES_CQP_STAG_RIGHTS_REMOTE_WRITE = (1<<19), 307 NES_CQP_STAG_RIGHTS_WINDOW_BIND = (1<<20), 308 NES_CQP_STAG_REM_ACC_EN = (1<<21), 309 NES_CQP_STAG_LEAVE_PENDING = (1<<31), 310 }; 311 312 enum nes_cqp_ceq_wqeword_idx { 313 NES_CQP_CEQ_WQE_ELEMENT_COUNT_IDX = 1, 314 NES_CQP_CEQ_WQE_PBL_LOW_IDX = 6, 315 NES_CQP_CEQ_WQE_PBL_HIGH_IDX = 7, 316 }; 317 318 enum nes_cqp_ceq_bits { 319 NES_CQP_CEQ_4KB_CHUNK = (1<<14), 320 NES_CQP_CEQ_VIRT = (1<<15), 321 }; 322 323 enum nes_cqp_aeq_wqeword_idx { 324 NES_CQP_AEQ_WQE_ELEMENT_COUNT_IDX = 1, 325 NES_CQP_AEQ_WQE_PBL_LOW_IDX = 6, 326 NES_CQP_AEQ_WQE_PBL_HIGH_IDX = 7, 327 }; 328 329 enum nes_cqp_aeq_bits { 330 NES_CQP_AEQ_4KB_CHUNK = (1<<14), 331 NES_CQP_AEQ_VIRT = (1<<15), 332 }; 333 334 enum nes_cqp_lmi_wqeword_idx { 335 NES_CQP_LMI_WQE_LMI_OFFSET_IDX = 1, 336 NES_CQP_LMI_WQE_FRAG_LOW_IDX = 8, 337 NES_CQP_LMI_WQE_FRAG_HIGH_IDX = 9, 338 NES_CQP_LMI_WQE_FRAG_LEN_IDX = 10, 339 }; 340 341 enum nes_cqp_arp_wqeword_idx { 342 NES_CQP_ARP_WQE_MAC_ADDR_LOW_IDX = 6, 343 NES_CQP_ARP_WQE_MAC_HIGH_IDX = 7, 344 NES_CQP_ARP_WQE_REACHABILITY_MAX_IDX = 1, 345 }; 346 347 enum nes_cqp_upload_wqeword_idx { 348 NES_CQP_UPLOAD_WQE_CTXT_LOW_IDX = 6, 349 NES_CQP_UPLOAD_WQE_CTXT_HIGH_IDX = 7, 350 NES_CQP_UPLOAD_WQE_HTE_IDX = 8, 351 }; 352 353 enum nes_cqp_arp_bits { 354 NES_CQP_ARP_VALID = (1<<8), 355 NES_CQP_ARP_PERM = (1<<9), 356 }; 357 358 enum nes_cqp_flush_bits { 359 NES_CQP_FLUSH_SQ = (1<<30), 360 NES_CQP_FLUSH_RQ = (1<<31), 361 }; 362 363 enum nes_cqe_opcode_bits { 364 NES_CQE_STAG_VALID = (1<<6), 365 NES_CQE_ERROR = (1<<7), 366 NES_CQE_SQ = (1<<8), 367 NES_CQE_SE = (1<<9), 368 NES_CQE_PSH = (1<<29), 369 NES_CQE_FIN = (1<<30), 370 NES_CQE_VALID = (1<<31), 371 }; 372 373 374 enum nes_cqe_word_idx { 375 NES_CQE_PAYLOAD_LENGTH_IDX = 0, 376 NES_CQE_COMP_COMP_CTX_LOW_IDX = 2, 377 NES_CQE_COMP_COMP_CTX_HIGH_IDX = 3, 378 NES_CQE_INV_STAG_IDX = 4, 379 NES_CQE_QP_ID_IDX = 5, 380 NES_CQE_ERROR_CODE_IDX = 6, 381 NES_CQE_OPCODE_IDX = 7, 382 }; 383 384 enum nes_ceqe_word_idx { 385 NES_CEQE_CQ_CTX_LOW_IDX = 0, 386 NES_CEQE_CQ_CTX_HIGH_IDX = 1, 387 }; 388 389 enum nes_ceqe_status_bit { 390 NES_CEQE_VALID = (1<<31), 391 }; 392 393 enum nes_int_bits { 394 NES_INT_CEQ0 = (1<<0), 395 NES_INT_CEQ1 = (1<<1), 396 NES_INT_CEQ2 = (1<<2), 397 NES_INT_CEQ3 = (1<<3), 398 NES_INT_CEQ4 = (1<<4), 399 NES_INT_CEQ5 = (1<<5), 400 NES_INT_CEQ6 = (1<<6), 401 NES_INT_CEQ7 = (1<<7), 402 NES_INT_CEQ8 = (1<<8), 403 NES_INT_CEQ9 = (1<<9), 404 NES_INT_CEQ10 = (1<<10), 405 NES_INT_CEQ11 = (1<<11), 406 NES_INT_CEQ12 = (1<<12), 407 NES_INT_CEQ13 = (1<<13), 408 NES_INT_CEQ14 = (1<<14), 409 NES_INT_CEQ15 = (1<<15), 410 NES_INT_AEQ0 = (1<<16), 411 NES_INT_AEQ1 = (1<<17), 412 NES_INT_AEQ2 = (1<<18), 413 NES_INT_AEQ3 = (1<<19), 414 NES_INT_AEQ4 = (1<<20), 415 NES_INT_AEQ5 = (1<<21), 416 NES_INT_AEQ6 = (1<<22), 417 NES_INT_AEQ7 = (1<<23), 418 NES_INT_MAC0 = (1<<24), 419 NES_INT_MAC1 = (1<<25), 420 NES_INT_MAC2 = (1<<26), 421 NES_INT_MAC3 = (1<<27), 422 NES_INT_TSW = (1<<28), 423 NES_INT_TIMER = (1<<29), 424 NES_INT_INTF = (1<<30), 425 }; 426 427 enum nes_intf_int_bits { 428 NES_INTF_INT_PCIERR = (1<<0), 429 NES_INTF_PERIODIC_TIMER = (1<<2), 430 NES_INTF_ONE_SHOT_TIMER = (1<<3), 431 NES_INTF_INT_CRITERR = (1<<14), 432 NES_INTF_INT_AEQ0_OFLOW = (1<<16), 433 NES_INTF_INT_AEQ1_OFLOW = (1<<17), 434 NES_INTF_INT_AEQ2_OFLOW = (1<<18), 435 NES_INTF_INT_AEQ3_OFLOW = (1<<19), 436 NES_INTF_INT_AEQ4_OFLOW = (1<<20), 437 NES_INTF_INT_AEQ5_OFLOW = (1<<21), 438 NES_INTF_INT_AEQ6_OFLOW = (1<<22), 439 NES_INTF_INT_AEQ7_OFLOW = (1<<23), 440 NES_INTF_INT_AEQ_OFLOW = (0xff<<16), 441 }; 442 443 enum nes_mac_int_bits { 444 NES_MAC_INT_LINK_STAT_CHG = (1<<1), 445 NES_MAC_INT_XGMII_EXT = (1<<2), 446 NES_MAC_INT_TX_UNDERFLOW = (1<<6), 447 NES_MAC_INT_TX_ERROR = (1<<7), 448 }; 449 450 enum nes_cqe_allocate_bits { 451 NES_CQE_ALLOC_INC_SELECT = (1<<28), 452 NES_CQE_ALLOC_NOTIFY_NEXT = (1<<29), 453 NES_CQE_ALLOC_NOTIFY_SE = (1<<30), 454 NES_CQE_ALLOC_RESET = (1<<31), 455 }; 456 457 enum nes_nic_rq_wqe_word_idx { 458 NES_NIC_RQ_WQE_LENGTH_1_0_IDX = 0, 459 NES_NIC_RQ_WQE_LENGTH_3_2_IDX = 1, 460 NES_NIC_RQ_WQE_FRAG0_LOW_IDX = 2, 461 NES_NIC_RQ_WQE_FRAG0_HIGH_IDX = 3, 462 NES_NIC_RQ_WQE_FRAG1_LOW_IDX = 4, 463 NES_NIC_RQ_WQE_FRAG1_HIGH_IDX = 5, 464 NES_NIC_RQ_WQE_FRAG2_LOW_IDX = 6, 465 NES_NIC_RQ_WQE_FRAG2_HIGH_IDX = 7, 466 NES_NIC_RQ_WQE_FRAG3_LOW_IDX = 8, 467 NES_NIC_RQ_WQE_FRAG3_HIGH_IDX = 9, 468 }; 469 470 enum nes_nic_sq_wqe_word_idx { 471 NES_NIC_SQ_WQE_MISC_IDX = 0, 472 NES_NIC_SQ_WQE_TOTAL_LENGTH_IDX = 1, 473 NES_NIC_SQ_WQE_LSO_INFO_IDX = 2, 474 NES_NIC_SQ_WQE_LENGTH_0_TAG_IDX = 3, 475 NES_NIC_SQ_WQE_LENGTH_2_1_IDX = 4, 476 NES_NIC_SQ_WQE_LENGTH_4_3_IDX = 5, 477 NES_NIC_SQ_WQE_FRAG0_LOW_IDX = 6, 478 NES_NIC_SQ_WQE_FRAG0_HIGH_IDX = 7, 479 NES_NIC_SQ_WQE_FRAG1_LOW_IDX = 8, 480 NES_NIC_SQ_WQE_FRAG1_HIGH_IDX = 9, 481 NES_NIC_SQ_WQE_FRAG2_LOW_IDX = 10, 482 NES_NIC_SQ_WQE_FRAG2_HIGH_IDX = 11, 483 NES_NIC_SQ_WQE_FRAG3_LOW_IDX = 12, 484 NES_NIC_SQ_WQE_FRAG3_HIGH_IDX = 13, 485 NES_NIC_SQ_WQE_FRAG4_LOW_IDX = 14, 486 NES_NIC_SQ_WQE_FRAG4_HIGH_IDX = 15, 487 }; 488 489 enum nes_iwarp_sq_wqe_word_idx { 490 NES_IWARP_SQ_WQE_MISC_IDX = 0, 491 NES_IWARP_SQ_WQE_TOTAL_PAYLOAD_IDX = 1, 492 NES_IWARP_SQ_WQE_COMP_CTX_LOW_IDX = 2, 493 NES_IWARP_SQ_WQE_COMP_CTX_HIGH_IDX = 3, 494 NES_IWARP_SQ_WQE_COMP_SCRATCH_LOW_IDX = 4, 495 NES_IWARP_SQ_WQE_COMP_SCRATCH_HIGH_IDX = 5, 496 NES_IWARP_SQ_WQE_INV_STAG_LOW_IDX = 7, 497 NES_IWARP_SQ_WQE_RDMA_TO_LOW_IDX = 8, 498 NES_IWARP_SQ_WQE_RDMA_TO_HIGH_IDX = 9, 499 NES_IWARP_SQ_WQE_RDMA_LENGTH_IDX = 10, 500 NES_IWARP_SQ_WQE_RDMA_STAG_IDX = 11, 501 NES_IWARP_SQ_WQE_IMM_DATA_START_IDX = 12, 502 NES_IWARP_SQ_WQE_FRAG0_LOW_IDX = 16, 503 NES_IWARP_SQ_WQE_FRAG0_HIGH_IDX = 17, 504 NES_IWARP_SQ_WQE_LENGTH0_IDX = 18, 505 NES_IWARP_SQ_WQE_STAG0_IDX = 19, 506 NES_IWARP_SQ_WQE_FRAG1_LOW_IDX = 20, 507 NES_IWARP_SQ_WQE_FRAG1_HIGH_IDX = 21, 508 NES_IWARP_SQ_WQE_LENGTH1_IDX = 22, 509 NES_IWARP_SQ_WQE_STAG1_IDX = 23, 510 NES_IWARP_SQ_WQE_FRAG2_LOW_IDX = 24, 511 NES_IWARP_SQ_WQE_FRAG2_HIGH_IDX = 25, 512 NES_IWARP_SQ_WQE_LENGTH2_IDX = 26, 513 NES_IWARP_SQ_WQE_STAG2_IDX = 27, 514 NES_IWARP_SQ_WQE_FRAG3_LOW_IDX = 28, 515 NES_IWARP_SQ_WQE_FRAG3_HIGH_IDX = 29, 516 NES_IWARP_SQ_WQE_LENGTH3_IDX = 30, 517 NES_IWARP_SQ_WQE_STAG3_IDX = 31, 518 }; 519 520 enum nes_iwarp_sq_bind_wqe_word_idx { 521 NES_IWARP_SQ_BIND_WQE_MR_IDX = 6, 522 NES_IWARP_SQ_BIND_WQE_MW_IDX = 7, 523 NES_IWARP_SQ_BIND_WQE_LENGTH_LOW_IDX = 8, 524 NES_IWARP_SQ_BIND_WQE_LENGTH_HIGH_IDX = 9, 525 NES_IWARP_SQ_BIND_WQE_VA_FBO_LOW_IDX = 10, 526 NES_IWARP_SQ_BIND_WQE_VA_FBO_HIGH_IDX = 11, 527 }; 528 529 enum nes_iwarp_sq_fmr_wqe_word_idx { 530 NES_IWARP_SQ_FMR_WQE_MR_STAG_IDX = 7, 531 NES_IWARP_SQ_FMR_WQE_LENGTH_LOW_IDX = 8, 532 NES_IWARP_SQ_FMR_WQE_LENGTH_HIGH_IDX = 9, 533 NES_IWARP_SQ_FMR_WQE_VA_FBO_LOW_IDX = 10, 534 NES_IWARP_SQ_FMR_WQE_VA_FBO_HIGH_IDX = 11, 535 NES_IWARP_SQ_FMR_WQE_PBL_ADDR_LOW_IDX = 12, 536 NES_IWARP_SQ_FMR_WQE_PBL_ADDR_HIGH_IDX = 13, 537 NES_IWARP_SQ_FMR_WQE_PBL_LENGTH_IDX = 14, 538 }; 539 540 enum nes_iwarp_sq_locinv_wqe_word_idx { 541 NES_IWARP_SQ_LOCINV_WQE_INV_STAG_IDX = 6, 542 }; 543 544 545 enum nes_iwarp_rq_wqe_word_idx { 546 NES_IWARP_RQ_WQE_TOTAL_PAYLOAD_IDX = 1, 547 NES_IWARP_RQ_WQE_COMP_CTX_LOW_IDX = 2, 548 NES_IWARP_RQ_WQE_COMP_CTX_HIGH_IDX = 3, 549 NES_IWARP_RQ_WQE_COMP_SCRATCH_LOW_IDX = 4, 550 NES_IWARP_RQ_WQE_COMP_SCRATCH_HIGH_IDX = 5, 551 NES_IWARP_RQ_WQE_FRAG0_LOW_IDX = 8, 552 NES_IWARP_RQ_WQE_FRAG0_HIGH_IDX = 9, 553 NES_IWARP_RQ_WQE_LENGTH0_IDX = 10, 554 NES_IWARP_RQ_WQE_STAG0_IDX = 11, 555 NES_IWARP_RQ_WQE_FRAG1_LOW_IDX = 12, 556 NES_IWARP_RQ_WQE_FRAG1_HIGH_IDX = 13, 557 NES_IWARP_RQ_WQE_LENGTH1_IDX = 14, 558 NES_IWARP_RQ_WQE_STAG1_IDX = 15, 559 NES_IWARP_RQ_WQE_FRAG2_LOW_IDX = 16, 560 NES_IWARP_RQ_WQE_FRAG2_HIGH_IDX = 17, 561 NES_IWARP_RQ_WQE_LENGTH2_IDX = 18, 562 NES_IWARP_RQ_WQE_STAG2_IDX = 19, 563 NES_IWARP_RQ_WQE_FRAG3_LOW_IDX = 20, 564 NES_IWARP_RQ_WQE_FRAG3_HIGH_IDX = 21, 565 NES_IWARP_RQ_WQE_LENGTH3_IDX = 22, 566 NES_IWARP_RQ_WQE_STAG3_IDX = 23, 567 }; 568 569 enum nes_nic_sq_wqe_bits { 570 NES_NIC_SQ_WQE_PHDR_CS_READY = (1<<21), 571 NES_NIC_SQ_WQE_LSO_ENABLE = (1<<22), 572 NES_NIC_SQ_WQE_TAGVALUE_ENABLE = (1<<23), 573 NES_NIC_SQ_WQE_DISABLE_CHKSUM = (1<<30), 574 NES_NIC_SQ_WQE_COMPLETION = (1<<31), 575 }; 576 577 enum nes_nic_cqe_word_idx { 578 NES_NIC_CQE_ACCQP_ID_IDX = 0, 579 NES_NIC_CQE_TAG_PKT_TYPE_IDX = 2, 580 NES_NIC_CQE_MISC_IDX = 3, 581 }; 582 583 #define NES_PKT_TYPE_APBVT_BITS 0xC112 584 #define NES_PKT_TYPE_APBVT_MASK 0xff3e 585 586 #define NES_PKT_TYPE_PVALID_BITS 0x10000000 587 #define NES_PKT_TYPE_PVALID_MASK 0x30000000 588 589 #define NES_PKT_TYPE_TCPV4_BITS 0x0110 590 #define NES_PKT_TYPE_TCPV4_MASK 0x3f30 591 592 #define NES_PKT_TYPE_UDPV4_BITS 0x0210 593 #define NES_PKT_TYPE_UDPV4_MASK 0x3f30 594 595 #define NES_PKT_TYPE_IPV4_BITS 0x0010 596 #define NES_PKT_TYPE_IPV4_MASK 0x3f30 597 598 #define NES_PKT_TYPE_OTHER_BITS 0x0000 599 #define NES_PKT_TYPE_OTHER_MASK 0x0030 600 601 #define NES_NIC_CQE_ERRV_SHIFT 16 602 enum nes_nic_ev_bits { 603 NES_NIC_ERRV_BITS_MODE = (1<<0), 604 NES_NIC_ERRV_BITS_IPV4_CSUM_ERR = (1<<1), 605 NES_NIC_ERRV_BITS_TCPUDP_CSUM_ERR = (1<<2), 606 NES_NIC_ERRV_BITS_WQE_OVERRUN = (1<<3), 607 NES_NIC_ERRV_BITS_IPH_ERR = (1<<4), 608 }; 609 610 enum nes_nic_cqe_bits { 611 NES_NIC_CQE_ERRV_MASK = (0xff<<NES_NIC_CQE_ERRV_SHIFT), 612 NES_NIC_CQE_SQ = (1<<24), 613 NES_NIC_CQE_ACCQP_PORT = (1<<28), 614 NES_NIC_CQE_ACCQP_VALID = (1<<29), 615 NES_NIC_CQE_TAG_VALID = (1<<30), 616 NES_NIC_CQE_VALID = (1<<31), 617 }; 618 619 enum nes_aeqe_word_idx { 620 NES_AEQE_COMP_CTXT_LOW_IDX = 0, 621 NES_AEQE_COMP_CTXT_HIGH_IDX = 1, 622 NES_AEQE_COMP_QP_CQ_ID_IDX = 2, 623 NES_AEQE_MISC_IDX = 3, 624 }; 625 626 enum nes_aeqe_bits { 627 NES_AEQE_QP = (1<<16), 628 NES_AEQE_CQ = (1<<17), 629 NES_AEQE_SQ = (1<<18), 630 NES_AEQE_INBOUND_RDMA = (1<<19), 631 NES_AEQE_IWARP_STATE_MASK = (7<<20), 632 NES_AEQE_TCP_STATE_MASK = (0xf<<24), 633 NES_AEQE_VALID = (1<<31), 634 }; 635 636 #define NES_AEQE_IWARP_STATE_SHIFT 20 637 #define NES_AEQE_TCP_STATE_SHIFT 24 638 639 enum nes_aeqe_iwarp_state { 640 NES_AEQE_IWARP_STATE_NON_EXISTANT = 0, 641 NES_AEQE_IWARP_STATE_IDLE = 1, 642 NES_AEQE_IWARP_STATE_RTS = 2, 643 NES_AEQE_IWARP_STATE_CLOSING = 3, 644 NES_AEQE_IWARP_STATE_TERMINATE = 5, 645 NES_AEQE_IWARP_STATE_ERROR = 6 646 }; 647 648 enum nes_aeqe_tcp_state { 649 NES_AEQE_TCP_STATE_NON_EXISTANT = 0, 650 NES_AEQE_TCP_STATE_CLOSED = 1, 651 NES_AEQE_TCP_STATE_LISTEN = 2, 652 NES_AEQE_TCP_STATE_SYN_SENT = 3, 653 NES_AEQE_TCP_STATE_SYN_RCVD = 4, 654 NES_AEQE_TCP_STATE_ESTABLISHED = 5, 655 NES_AEQE_TCP_STATE_CLOSE_WAIT = 6, 656 NES_AEQE_TCP_STATE_FIN_WAIT_1 = 7, 657 NES_AEQE_TCP_STATE_CLOSING = 8, 658 NES_AEQE_TCP_STATE_LAST_ACK = 9, 659 NES_AEQE_TCP_STATE_FIN_WAIT_2 = 10, 660 NES_AEQE_TCP_STATE_TIME_WAIT = 11 661 }; 662 663 enum nes_aeqe_aeid { 664 NES_AEQE_AEID_AMP_UNALLOCATED_STAG = 0x0102, 665 NES_AEQE_AEID_AMP_INVALID_STAG = 0x0103, 666 NES_AEQE_AEID_AMP_BAD_QP = 0x0104, 667 NES_AEQE_AEID_AMP_BAD_PD = 0x0105, 668 NES_AEQE_AEID_AMP_BAD_STAG_KEY = 0x0106, 669 NES_AEQE_AEID_AMP_BAD_STAG_INDEX = 0x0107, 670 NES_AEQE_AEID_AMP_BOUNDS_VIOLATION = 0x0108, 671 NES_AEQE_AEID_AMP_RIGHTS_VIOLATION = 0x0109, 672 NES_AEQE_AEID_AMP_TO_WRAP = 0x010a, 673 NES_AEQE_AEID_AMP_FASTREG_SHARED = 0x010b, 674 NES_AEQE_AEID_AMP_FASTREG_VALID_STAG = 0x010c, 675 NES_AEQE_AEID_AMP_FASTREG_MW_STAG = 0x010d, 676 NES_AEQE_AEID_AMP_FASTREG_INVALID_RIGHTS = 0x010e, 677 NES_AEQE_AEID_AMP_FASTREG_PBL_TABLE_OVERFLOW = 0x010f, 678 NES_AEQE_AEID_AMP_FASTREG_INVALID_LENGTH = 0x0110, 679 NES_AEQE_AEID_AMP_INVALIDATE_SHARED = 0x0111, 680 NES_AEQE_AEID_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS = 0x0112, 681 NES_AEQE_AEID_AMP_INVALIDATE_MR_WITH_BOUND_WINDOWS = 0x0113, 682 NES_AEQE_AEID_AMP_MWBIND_VALID_STAG = 0x0114, 683 NES_AEQE_AEID_AMP_MWBIND_OF_MR_STAG = 0x0115, 684 NES_AEQE_AEID_AMP_MWBIND_TO_ZERO_BASED_STAG = 0x0116, 685 NES_AEQE_AEID_AMP_MWBIND_TO_MW_STAG = 0x0117, 686 NES_AEQE_AEID_AMP_MWBIND_INVALID_RIGHTS = 0x0118, 687 NES_AEQE_AEID_AMP_MWBIND_INVALID_BOUNDS = 0x0119, 688 NES_AEQE_AEID_AMP_MWBIND_TO_INVALID_PARENT = 0x011a, 689 NES_AEQE_AEID_AMP_MWBIND_BIND_DISABLED = 0x011b, 690 NES_AEQE_AEID_BAD_CLOSE = 0x0201, 691 NES_AEQE_AEID_RDMAP_ROE_BAD_LLP_CLOSE = 0x0202, 692 NES_AEQE_AEID_CQ_OPERATION_ERROR = 0x0203, 693 NES_AEQE_AEID_PRIV_OPERATION_DENIED = 0x0204, 694 NES_AEQE_AEID_RDMA_READ_WHILE_ORD_ZERO = 0x0205, 695 NES_AEQE_AEID_STAG_ZERO_INVALID = 0x0206, 696 NES_AEQE_AEID_DDP_INVALID_MSN_GAP_IN_MSN = 0x0301, 697 NES_AEQE_AEID_DDP_INVALID_MSN_RANGE_IS_NOT_VALID = 0x0302, 698 NES_AEQE_AEID_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER = 0x0303, 699 NES_AEQE_AEID_DDP_UBE_INVALID_DDP_VERSION = 0x0304, 700 NES_AEQE_AEID_DDP_UBE_INVALID_MO = 0x0305, 701 NES_AEQE_AEID_DDP_UBE_INVALID_MSN_NO_BUFFER_AVAILABLE = 0x0306, 702 NES_AEQE_AEID_DDP_UBE_INVALID_QN = 0x0307, 703 NES_AEQE_AEID_DDP_NO_L_BIT = 0x0308, 704 NES_AEQE_AEID_RDMAP_ROE_INVALID_RDMAP_VERSION = 0x0311, 705 NES_AEQE_AEID_RDMAP_ROE_UNEXPECTED_OPCODE = 0x0312, 706 NES_AEQE_AEID_ROE_INVALID_RDMA_READ_REQUEST = 0x0313, 707 NES_AEQE_AEID_ROE_INVALID_RDMA_WRITE_OR_READ_RESP = 0x0314, 708 NES_AEQE_AEID_INVALID_ARP_ENTRY = 0x0401, 709 NES_AEQE_AEID_INVALID_TCP_OPTION_RCVD = 0x0402, 710 NES_AEQE_AEID_STALE_ARP_ENTRY = 0x0403, 711 NES_AEQE_AEID_LLP_CLOSE_COMPLETE = 0x0501, 712 NES_AEQE_AEID_LLP_CONNECTION_RESET = 0x0502, 713 NES_AEQE_AEID_LLP_FIN_RECEIVED = 0x0503, 714 NES_AEQE_AEID_LLP_RECEIVED_MARKER_AND_LENGTH_FIELDS_DONT_MATCH = 0x0504, 715 NES_AEQE_AEID_LLP_RECEIVED_MPA_CRC_ERROR = 0x0505, 716 NES_AEQE_AEID_LLP_SEGMENT_TOO_LARGE = 0x0506, 717 NES_AEQE_AEID_LLP_SEGMENT_TOO_SMALL = 0x0507, 718 NES_AEQE_AEID_LLP_SYN_RECEIVED = 0x0508, 719 NES_AEQE_AEID_LLP_TERMINATE_RECEIVED = 0x0509, 720 NES_AEQE_AEID_LLP_TOO_MANY_RETRIES = 0x050a, 721 NES_AEQE_AEID_LLP_TOO_MANY_KEEPALIVE_RETRIES = 0x050b, 722 NES_AEQE_AEID_RESET_SENT = 0x0601, 723 NES_AEQE_AEID_TERMINATE_SENT = 0x0602, 724 NES_AEQE_AEID_DDP_LCE_LOCAL_CATASTROPHIC = 0x0700 725 }; 726 727 enum nes_iwarp_sq_opcodes { 728 NES_IWARP_SQ_WQE_WRPDU = (1<<15), 729 NES_IWARP_SQ_WQE_PSH = (1<<21), 730 NES_IWARP_SQ_WQE_STREAMING = (1<<23), 731 NES_IWARP_SQ_WQE_IMM_DATA = (1<<28), 732 NES_IWARP_SQ_WQE_READ_FENCE = (1<<29), 733 NES_IWARP_SQ_WQE_LOCAL_FENCE = (1<<30), 734 NES_IWARP_SQ_WQE_SIGNALED_COMPL = (1<<31), 735 }; 736 737 enum nes_iwarp_sq_wqe_bits { 738 NES_IWARP_SQ_OP_RDMAW = 0, 739 NES_IWARP_SQ_OP_RDMAR = 1, 740 NES_IWARP_SQ_OP_SEND = 3, 741 NES_IWARP_SQ_OP_SENDINV = 4, 742 NES_IWARP_SQ_OP_SENDSE = 5, 743 NES_IWARP_SQ_OP_SENDSEINV = 6, 744 NES_IWARP_SQ_OP_BIND = 8, 745 NES_IWARP_SQ_OP_FAST_REG = 9, 746 NES_IWARP_SQ_OP_LOCINV = 10, 747 NES_IWARP_SQ_OP_RDMAR_LOCINV = 11, 748 NES_IWARP_SQ_OP_NOP = 12, 749 }; 750 751 #define NES_EEPROM_READ_REQUEST (1<<16) 752 #define NES_MAC_ADDR_VALID (1<<20) 753 754 /* 755 * NES index registers init values. 756 */ 757 struct nes_init_values { 758 u32 index; 759 u32 data; 760 u8 wrt; 761 }; 762 763 /* 764 * NES registers in BAR0. 765 */ 766 struct nes_pci_regs { 767 u32 int_status; 768 u32 int_mask; 769 u32 int_pending; 770 u32 intf_int_status; 771 u32 intf_int_mask; 772 u32 other_regs[59]; /* pad out to 256 bytes for now */ 773 }; 774 775 #define NES_CQP_SQ_SIZE 128 776 #define NES_CCQ_SIZE 128 777 #define NES_NIC_WQ_SIZE 512 778 #define NES_NIC_CTX_SIZE ((NES_NIC_CTX_RQ_SIZE_512) | (NES_NIC_CTX_SQ_SIZE_512)) 779 #define NES_NIC_BACK_STORE 0x00038000 780 781 struct nes_device; 782 783 struct nes_hw_nic_qp_context { 784 __le32 context_words[6]; 785 }; 786 787 struct nes_hw_nic_sq_wqe { 788 __le32 wqe_words[16]; 789 }; 790 791 struct nes_hw_nic_rq_wqe { 792 __le32 wqe_words[16]; 793 }; 794 795 struct nes_hw_nic_cqe { 796 __le32 cqe_words[4]; 797 }; 798 799 struct nes_hw_cqp_qp_context { 800 __le32 context_words[4]; 801 }; 802 803 struct nes_hw_cqp_wqe { 804 __le32 wqe_words[16]; 805 }; 806 807 struct nes_hw_qp_wqe { 808 __le32 wqe_words[32]; 809 }; 810 811 struct nes_hw_cqe { 812 __le32 cqe_words[8]; 813 }; 814 815 struct nes_hw_ceqe { 816 __le32 ceqe_words[2]; 817 }; 818 819 struct nes_hw_aeqe { 820 __le32 aeqe_words[4]; 821 }; 822 823 struct nes_cqp_request { 824 union { 825 u64 cqp_callback_context; 826 void *cqp_callback_pointer; 827 }; 828 wait_queue_head_t waitq; 829 struct nes_hw_cqp_wqe cqp_wqe; 830 struct list_head list; 831 atomic_t refcount; 832 void (*cqp_callback)(struct nes_device *nesdev, struct nes_cqp_request *cqp_request); 833 u16 major_code; 834 u16 minor_code; 835 u8 waiting; 836 u8 request_done; 837 u8 dynamic; 838 u8 callback; 839 }; 840 841 struct nes_hw_cqp { 842 struct nes_hw_cqp_wqe *sq_vbase; 843 dma_addr_t sq_pbase; 844 spinlock_t lock; 845 wait_queue_head_t waitq; 846 u16 qp_id; 847 u16 sq_head; 848 u16 sq_tail; 849 u16 sq_size; 850 }; 851 852 #define NES_FIRST_FRAG_SIZE 128 853 struct nes_first_frag { 854 u8 buffer[NES_FIRST_FRAG_SIZE]; 855 }; 856 857 struct nes_hw_nic { 858 struct nes_first_frag *first_frag_vbase; /* virtual address of first frags */ 859 struct nes_hw_nic_sq_wqe *sq_vbase; /* virtual address of sq */ 860 struct nes_hw_nic_rq_wqe *rq_vbase; /* virtual address of rq */ 861 struct sk_buff *tx_skb[NES_NIC_WQ_SIZE]; 862 struct sk_buff *rx_skb[NES_NIC_WQ_SIZE]; 863 dma_addr_t frag_paddr[NES_NIC_WQ_SIZE]; 864 unsigned long first_frag_overflow[BITS_TO_LONGS(NES_NIC_WQ_SIZE)]; 865 dma_addr_t sq_pbase; /* PCI memory for host rings */ 866 dma_addr_t rq_pbase; /* PCI memory for host rings */ 867 868 u16 qp_id; 869 u16 sq_head; 870 u16 sq_tail; 871 u16 sq_size; 872 u16 rq_head; 873 u16 rq_tail; 874 u16 rq_size; 875 u8 replenishing_rq; 876 u8 reserved; 877 878 spinlock_t sq_lock; 879 spinlock_t rq_lock; 880 }; 881 882 struct nes_hw_nic_cq { 883 struct nes_hw_nic_cqe volatile *cq_vbase; /* PCI memory for host rings */ 884 void (*ce_handler)(struct nes_device *nesdev, struct nes_hw_nic_cq *cq); 885 dma_addr_t cq_pbase; /* PCI memory for host rings */ 886 int rx_cqes_completed; 887 int cqe_allocs_pending; 888 int rx_pkts_indicated; 889 u16 cq_head; 890 u16 cq_size; 891 u16 cq_number; 892 u8 cqes_pending; 893 }; 894 895 struct nes_hw_qp { 896 struct nes_hw_qp_wqe *sq_vbase; /* PCI memory for host rings */ 897 struct nes_hw_qp_wqe *rq_vbase; /* PCI memory for host rings */ 898 void *q2_vbase; /* PCI memory for host rings */ 899 dma_addr_t sq_pbase; /* PCI memory for host rings */ 900 dma_addr_t rq_pbase; /* PCI memory for host rings */ 901 dma_addr_t q2_pbase; /* PCI memory for host rings */ 902 u32 qp_id; 903 u16 sq_head; 904 u16 sq_tail; 905 u16 sq_size; 906 u16 rq_head; 907 u16 rq_tail; 908 u16 rq_size; 909 u8 rq_encoded_size; 910 u8 sq_encoded_size; 911 }; 912 913 struct nes_hw_cq { 914 struct nes_hw_cqe *cq_vbase; /* PCI memory for host rings */ 915 void (*ce_handler)(struct nes_device *nesdev, struct nes_hw_cq *cq); 916 dma_addr_t cq_pbase; /* PCI memory for host rings */ 917 u16 cq_head; 918 u16 cq_size; 919 u16 cq_number; 920 }; 921 922 struct nes_hw_ceq { 923 struct nes_hw_ceqe volatile *ceq_vbase; /* PCI memory for host rings */ 924 dma_addr_t ceq_pbase; /* PCI memory for host rings */ 925 u16 ceq_head; 926 u16 ceq_size; 927 }; 928 929 struct nes_hw_aeq { 930 struct nes_hw_aeqe volatile *aeq_vbase; /* PCI memory for host rings */ 931 dma_addr_t aeq_pbase; /* PCI memory for host rings */ 932 u16 aeq_head; 933 u16 aeq_size; 934 }; 935 936 struct nic_qp_map { 937 u8 qpid; 938 u8 nic_index; 939 u8 logical_port; 940 u8 is_hnic; 941 }; 942 943 #define NES_CQP_ARP_AEQ_INDEX_MASK 0x000f0000 944 #define NES_CQP_ARP_AEQ_INDEX_SHIFT 16 945 946 #define NES_CQP_APBVT_ADD 0x00008000 947 #define NES_CQP_APBVT_NIC_SHIFT 16 948 949 #define NES_ARP_ADD 1 950 #define NES_ARP_DELETE 2 951 #define NES_ARP_RESOLVE 3 952 953 #define NES_MAC_SW_IDLE 0 954 #define NES_MAC_SW_INTERRUPT 1 955 #define NES_MAC_SW_MH 2 956 957 struct nes_arp_entry { 958 u32 ip_addr; 959 u8 mac_addr[ETH_ALEN]; 960 }; 961 962 #define NES_NIC_FAST_TIMER 96 963 #define NES_NIC_FAST_TIMER_LOW 40 964 #define NES_NIC_FAST_TIMER_HIGH 1000 965 #define DEFAULT_NES_QL_HIGH 256 966 #define DEFAULT_NES_QL_LOW 16 967 #define DEFAULT_NES_QL_TARGET 64 968 #define DEFAULT_JUMBO_NES_QL_LOW 12 969 #define DEFAULT_JUMBO_NES_QL_TARGET 40 970 #define DEFAULT_JUMBO_NES_QL_HIGH 128 971 #define NES_NIC_CQ_DOWNWARD_TREND 16 972 #define NES_PFT_SIZE 48 973 974 struct nes_hw_tune_timer { 975 /* u16 cq_count; */ 976 u16 threshold_low; 977 u16 threshold_target; 978 u16 threshold_high; 979 u16 timer_in_use; 980 u16 timer_in_use_old; 981 u16 timer_in_use_min; 982 u16 timer_in_use_max; 983 u8 timer_direction_upward; 984 u8 timer_direction_downward; 985 u16 cq_count_old; 986 u8 cq_direction_downward; 987 }; 988 989 #define NES_TIMER_INT_LIMIT 2 990 #define NES_TIMER_INT_LIMIT_DYNAMIC 10 991 #define NES_TIMER_ENABLE_LIMIT 4 992 #define NES_MAX_LINK_INTERRUPTS 128 993 #define NES_MAX_LINK_CHECK 200 994 #define NES_MAX_LRO_DESCRIPTORS 32 995 #define NES_LRO_MAX_AGGR 64 996 997 struct nes_adapter { 998 u64 fw_ver; 999 unsigned long *allocated_qps; 1000 unsigned long *allocated_cqs; 1001 unsigned long *allocated_mrs; 1002 unsigned long *allocated_pds; 1003 unsigned long *allocated_arps; 1004 struct nes_qp **qp_table; 1005 struct workqueue_struct *work_q; 1006 1007 struct list_head list; 1008 struct list_head active_listeners; 1009 /* list of the netdev's associated with each logical port */ 1010 struct list_head nesvnic_list[4]; 1011 1012 struct timer_list mh_timer; 1013 struct timer_list lc_timer; 1014 struct work_struct work; 1015 spinlock_t resource_lock; 1016 spinlock_t phy_lock; 1017 spinlock_t pbl_lock; 1018 spinlock_t periodic_timer_lock; 1019 1020 struct nes_arp_entry arp_table[NES_MAX_ARP_TABLE_SIZE]; 1021 1022 /* Adapter CEQ and AEQs */ 1023 struct nes_hw_ceq ceq[16]; 1024 struct nes_hw_aeq aeq[8]; 1025 1026 struct nes_hw_tune_timer tune_timer; 1027 1028 unsigned long doorbell_start; 1029 1030 u32 hw_rev; 1031 u32 vendor_id; 1032 u32 vendor_part_id; 1033 u32 device_cap_flags; 1034 u32 tick_delta; 1035 u32 timer_int_req; 1036 u32 arp_table_size; 1037 u32 next_arp_index; 1038 1039 u32 max_mr; 1040 u32 max_256pbl; 1041 u32 max_4kpbl; 1042 u32 free_256pbl; 1043 u32 free_4kpbl; 1044 u32 max_mr_size; 1045 u32 max_qp; 1046 u32 next_qp; 1047 u32 max_irrq; 1048 u32 max_qp_wr; 1049 u32 max_sge; 1050 u32 max_cq; 1051 u32 next_cq; 1052 u32 max_cqe; 1053 u32 max_pd; 1054 u32 base_pd; 1055 u32 next_pd; 1056 u32 hte_index_mask; 1057 1058 /* EEPROM information */ 1059 u32 rx_pool_size; 1060 u32 tx_pool_size; 1061 u32 rx_threshold; 1062 u32 tcp_timer_core_clk_divisor; 1063 u32 iwarp_config; 1064 u32 cm_config; 1065 u32 sws_timer_config; 1066 u32 tcp_config1; 1067 u32 wqm_wat; 1068 u32 core_clock; 1069 u32 firmware_version; 1070 1071 u32 nic_rx_eth_route_err; 1072 1073 u32 et_rx_coalesce_usecs; 1074 u32 et_rx_max_coalesced_frames; 1075 u32 et_rx_coalesce_usecs_irq; 1076 u32 et_rx_max_coalesced_frames_irq; 1077 u32 et_pkt_rate_low; 1078 u32 et_rx_coalesce_usecs_low; 1079 u32 et_rx_max_coalesced_frames_low; 1080 u32 et_pkt_rate_high; 1081 u32 et_rx_coalesce_usecs_high; 1082 u32 et_rx_max_coalesced_frames_high; 1083 u32 et_rate_sample_interval; 1084 u32 timer_int_limit; 1085 u32 wqm_quanta; 1086 1087 /* Adapter base MAC address */ 1088 u32 mac_addr_low; 1089 u16 mac_addr_high; 1090 1091 u16 firmware_eeprom_offset; 1092 u16 software_eeprom_offset; 1093 1094 u16 max_irrq_wr; 1095 1096 /* pd config for each port */ 1097 u16 pd_config_size[4]; 1098 u16 pd_config_base[4]; 1099 1100 u16 link_interrupt_count[4]; 1101 u8 crit_error_count[32]; 1102 1103 /* the phy index for each port */ 1104 u8 phy_index[4]; 1105 u8 mac_sw_state[4]; 1106 u8 mac_link_down[4]; 1107 u8 phy_type[4]; 1108 u8 log_port; 1109 1110 /* PCI information */ 1111 unsigned int devfn; 1112 unsigned char bus_number; 1113 unsigned char OneG_Mode; 1114 1115 unsigned char ref_count; 1116 u8 netdev_count; 1117 u8 netdev_max; /* from host nic address count in EEPROM */ 1118 u8 port_count; 1119 u8 virtwq; 1120 u8 et_use_adaptive_rx_coalesce; 1121 u8 adapter_fcn_count; 1122 u8 pft_mcast_map[NES_PFT_SIZE]; 1123 }; 1124 1125 struct nes_pbl { 1126 u64 *pbl_vbase; 1127 dma_addr_t pbl_pbase; 1128 struct page *page; 1129 unsigned long user_base; 1130 u32 pbl_size; 1131 struct list_head list; 1132 /* TODO: need to add list for two level tables */ 1133 }; 1134 1135 struct nes_listener { 1136 struct work_struct work; 1137 struct workqueue_struct *wq; 1138 struct nes_vnic *nesvnic; 1139 struct iw_cm_id *cm_id; 1140 struct list_head list; 1141 unsigned long socket; 1142 u8 accept_failed; 1143 }; 1144 1145 struct nes_ib_device; 1146 1147 struct nes_vnic { 1148 struct nes_ib_device *nesibdev; 1149 u64 sq_full; 1150 u64 sq_locked; 1151 u64 tso_requests; 1152 u64 segmented_tso_requests; 1153 u64 linearized_skbs; 1154 u64 tx_sw_dropped; 1155 u64 endnode_nstat_rx_discard; 1156 u64 endnode_nstat_rx_octets; 1157 u64 endnode_nstat_rx_frames; 1158 u64 endnode_nstat_tx_octets; 1159 u64 endnode_nstat_tx_frames; 1160 u64 endnode_ipv4_tcp_retransmits; 1161 /* void *mem; */ 1162 struct nes_device *nesdev; 1163 struct net_device *netdev; 1164 struct vlan_group *vlan_grp; 1165 atomic_t rx_skbs_needed; 1166 atomic_t rx_skb_timer_running; 1167 int budget; 1168 u32 msg_enable; 1169 /* u32 tx_avail; */ 1170 __be32 local_ipaddr; 1171 struct napi_struct napi; 1172 spinlock_t tx_lock; /* could use netdev tx lock? */ 1173 struct timer_list rq_wqes_timer; 1174 u32 nic_mem_size; 1175 void *nic_vbase; 1176 dma_addr_t nic_pbase; 1177 struct nes_hw_nic nic; 1178 struct nes_hw_nic_cq nic_cq; 1179 u32 mcrq_qp_id; 1180 struct nes_ucontext *mcrq_ucontext; 1181 struct nes_cqp_request* (*get_cqp_request)(struct nes_device *nesdev); 1182 void (*post_cqp_request)(struct nes_device*, struct nes_cqp_request *); 1183 int (*mcrq_mcast_filter)( struct nes_vnic* nesvnic, __u8* dmi_addr ); 1184 struct net_device_stats netstats; 1185 /* used to put the netdev on the adapters logical port list */ 1186 struct list_head list; 1187 u16 max_frame_size; 1188 u8 netdev_open; 1189 u8 linkup; 1190 u8 logical_port; 1191 u8 netdev_index; /* might not be needed, indexes nesdev->netdev */ 1192 u8 perfect_filter_index; 1193 u8 nic_index; 1194 u8 qp_nic_index[4]; 1195 u8 next_qp_nic_index; 1196 u8 of_device_registered; 1197 u8 rdma_enabled; 1198 u8 rx_checksum_disabled; 1199 u32 lro_max_aggr; 1200 struct net_lro_mgr lro_mgr; 1201 struct net_lro_desc lro_desc[NES_MAX_LRO_DESCRIPTORS]; 1202 }; 1203 1204 struct nes_ib_device { 1205 struct ib_device ibdev; 1206 struct nes_vnic *nesvnic; 1207 1208 /* Virtual RNIC Limits */ 1209 u32 max_mr; 1210 u32 max_qp; 1211 u32 max_cq; 1212 u32 max_pd; 1213 u32 num_mr; 1214 u32 num_qp; 1215 u32 num_cq; 1216 u32 num_pd; 1217 }; 1218 1219 #define nes_vlan_rx vlan_hwaccel_receive_skb 1220 #define nes_netif_rx netif_receive_skb 1221 1222 #endif /* __NES_HW_H */ 1223