1 /*
2 * Local APIC handling, local APIC timers
3 *
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
5 *
6 * Fixes
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
9 * and Rolf G. Tews
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
13 * Pavel Machek and
14 * Mikael Pettersson : PM converted to driver model.
15 */
16
17 #include <linux/init.h>
18
19 #include <linux/mm.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/ioport.h>
27 #include <linux/cpu.h>
28 #include <linux/clockchips.h>
29 #include <linux/acpi_pmtmr.h>
30 #include <linux/module.h>
31 #include <linux/dmi.h>
32 #include <linux/dmar.h>
33 #include <linux/ftrace.h>
34 #include <linux/smp.h>
35 #include <linux/nmi.h>
36 #include <linux/timex.h>
37
38 #include <asm/atomic.h>
39 #include <asm/mtrr.h>
40 #include <asm/mpspec.h>
41 #include <asm/desc.h>
42 #include <asm/arch_hooks.h>
43 #include <asm/hpet.h>
44 #include <asm/pgalloc.h>
45 #include <asm/i8253.h>
46 #include <asm/idle.h>
47 #include <asm/proto.h>
48 #include <asm/apic.h>
49 #include <asm/i8259.h>
50 #include <asm/smp.h>
51
52 #include <mach_apic.h>
53 #include <mach_apicdef.h>
54 #include <mach_ipi.h>
55
56 /*
57 * Sanity check
58 */
59 #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
60 # error SPURIOUS_APIC_VECTOR definition error
61 #endif
62
63 #ifdef CONFIG_X86_32
64 /*
65 * Knob to control our willingness to enable the local APIC.
66 *
67 * +1=force-enable
68 */
69 static int force_enable_local_apic;
70 /*
71 * APIC command line parameters
72 */
parse_lapic(char * arg)73 static int __init parse_lapic(char *arg)
74 {
75 force_enable_local_apic = 1;
76 return 0;
77 }
78 early_param("lapic", parse_lapic);
79 /* Local APIC was disabled by the BIOS and enabled by the kernel */
80 static int enabled_via_apicbase;
81
82 #endif
83
84 #ifdef CONFIG_X86_64
85 static int apic_calibrate_pmtmr __initdata;
setup_apicpmtimer(char * s)86 static __init int setup_apicpmtimer(char *s)
87 {
88 apic_calibrate_pmtmr = 1;
89 notsc_setup(NULL);
90 return 0;
91 }
92 __setup("apicpmtimer", setup_apicpmtimer);
93 #endif
94
95 #ifdef CONFIG_X86_64
96 #define HAVE_X2APIC
97 #endif
98
99 #ifdef HAVE_X2APIC
100 int x2apic;
101 /* x2apic enabled before OS handover */
102 static int x2apic_preenabled;
103 static int disable_x2apic;
setup_nox2apic(char * str)104 static __init int setup_nox2apic(char *str)
105 {
106 disable_x2apic = 1;
107 setup_clear_cpu_cap(X86_FEATURE_X2APIC);
108 return 0;
109 }
110 early_param("nox2apic", setup_nox2apic);
111 #endif
112
113 unsigned long mp_lapic_addr;
114 int disable_apic;
115 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
116 static int disable_apic_timer __cpuinitdata;
117 /* Local APIC timer works in C2 */
118 int local_apic_timer_c2_ok;
119 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
120
121 int first_system_vector = 0xfe;
122
123 /*
124 * Debug level, exported for io_apic.c
125 */
126 unsigned int apic_verbosity;
127
128 int pic_mode;
129
130 /* Have we found an MP table */
131 int smp_found_config;
132
133 static struct resource lapic_resource = {
134 .name = "Local APIC",
135 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
136 };
137
138 static unsigned int calibration_result;
139
140 static int lapic_next_event(unsigned long delta,
141 struct clock_event_device *evt);
142 static void lapic_timer_setup(enum clock_event_mode mode,
143 struct clock_event_device *evt);
144 static void lapic_timer_broadcast(const struct cpumask *mask);
145 static void apic_pm_activate(void);
146
147 /*
148 * The local apic timer can be used for any function which is CPU local.
149 */
150 static struct clock_event_device lapic_clockevent = {
151 .name = "lapic",
152 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
153 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
154 .shift = 32,
155 .set_mode = lapic_timer_setup,
156 .set_next_event = lapic_next_event,
157 .broadcast = lapic_timer_broadcast,
158 .rating = 100,
159 .irq = -1,
160 };
161 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
162
163 static unsigned long apic_phys;
164
165 /*
166 * Get the LAPIC version
167 */
lapic_get_version(void)168 static inline int lapic_get_version(void)
169 {
170 return GET_APIC_VERSION(apic_read(APIC_LVR));
171 }
172
173 /*
174 * Check, if the APIC is integrated or a separate chip
175 */
lapic_is_integrated(void)176 static inline int lapic_is_integrated(void)
177 {
178 #ifdef CONFIG_X86_64
179 return 1;
180 #else
181 return APIC_INTEGRATED(lapic_get_version());
182 #endif
183 }
184
185 /*
186 * Check, whether this is a modern or a first generation APIC
187 */
modern_apic(void)188 static int modern_apic(void)
189 {
190 /* AMD systems use old APIC versions, so check the CPU */
191 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
192 boot_cpu_data.x86 >= 0xf)
193 return 1;
194 return lapic_get_version() >= 0x14;
195 }
196
197 /*
198 * Paravirt kernels also might be using these below ops. So we still
199 * use generic apic_read()/apic_write(), which might be pointing to different
200 * ops in PARAVIRT case.
201 */
xapic_wait_icr_idle(void)202 void xapic_wait_icr_idle(void)
203 {
204 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
205 cpu_relax();
206 }
207
safe_xapic_wait_icr_idle(void)208 u32 safe_xapic_wait_icr_idle(void)
209 {
210 u32 send_status;
211 int timeout;
212
213 timeout = 0;
214 do {
215 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
216 if (!send_status)
217 break;
218 udelay(100);
219 } while (timeout++ < 1000);
220
221 return send_status;
222 }
223
xapic_icr_write(u32 low,u32 id)224 void xapic_icr_write(u32 low, u32 id)
225 {
226 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
227 apic_write(APIC_ICR, low);
228 }
229
xapic_icr_read(void)230 static u64 xapic_icr_read(void)
231 {
232 u32 icr1, icr2;
233
234 icr2 = apic_read(APIC_ICR2);
235 icr1 = apic_read(APIC_ICR);
236
237 return icr1 | ((u64)icr2 << 32);
238 }
239
240 static struct apic_ops xapic_ops = {
241 .read = native_apic_mem_read,
242 .write = native_apic_mem_write,
243 .icr_read = xapic_icr_read,
244 .icr_write = xapic_icr_write,
245 .wait_icr_idle = xapic_wait_icr_idle,
246 .safe_wait_icr_idle = safe_xapic_wait_icr_idle,
247 };
248
249 struct apic_ops __read_mostly *apic_ops = &xapic_ops;
250 EXPORT_SYMBOL_GPL(apic_ops);
251
252 #ifdef HAVE_X2APIC
x2apic_wait_icr_idle(void)253 static void x2apic_wait_icr_idle(void)
254 {
255 /* no need to wait for icr idle in x2apic */
256 return;
257 }
258
safe_x2apic_wait_icr_idle(void)259 static u32 safe_x2apic_wait_icr_idle(void)
260 {
261 /* no need to wait for icr idle in x2apic */
262 return 0;
263 }
264
x2apic_icr_write(u32 low,u32 id)265 void x2apic_icr_write(u32 low, u32 id)
266 {
267 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
268 }
269
x2apic_icr_read(void)270 static u64 x2apic_icr_read(void)
271 {
272 unsigned long val;
273
274 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
275 return val;
276 }
277
278 static struct apic_ops x2apic_ops = {
279 .read = native_apic_msr_read,
280 .write = native_apic_msr_write,
281 .icr_read = x2apic_icr_read,
282 .icr_write = x2apic_icr_write,
283 .wait_icr_idle = x2apic_wait_icr_idle,
284 .safe_wait_icr_idle = safe_x2apic_wait_icr_idle,
285 };
286 #endif
287
288 /**
289 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
290 */
enable_NMI_through_LVT0(void)291 void __cpuinit enable_NMI_through_LVT0(void)
292 {
293 unsigned int v;
294
295 /* unmask and set to NMI */
296 v = APIC_DM_NMI;
297
298 /* Level triggered for 82489DX (32bit mode) */
299 if (!lapic_is_integrated())
300 v |= APIC_LVT_LEVEL_TRIGGER;
301
302 apic_write(APIC_LVT0, v);
303 }
304
305 #ifdef CONFIG_X86_32
306 /**
307 * get_physical_broadcast - Get number of physical broadcast IDs
308 */
get_physical_broadcast(void)309 int get_physical_broadcast(void)
310 {
311 return modern_apic() ? 0xff : 0xf;
312 }
313 #endif
314
315 /**
316 * lapic_get_maxlvt - get the maximum number of local vector table entries
317 */
lapic_get_maxlvt(void)318 int lapic_get_maxlvt(void)
319 {
320 unsigned int v;
321
322 v = apic_read(APIC_LVR);
323 /*
324 * - we always have APIC integrated on 64bit mode
325 * - 82489DXs do not report # of LVT entries
326 */
327 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
328 }
329
330 /*
331 * Local APIC timer
332 */
333
334 /* Clock divisor */
335 #define APIC_DIVISOR 16
336
337 /*
338 * This function sets up the local APIC timer, with a timeout of
339 * 'clocks' APIC bus clock. During calibration we actually call
340 * this function twice on the boot CPU, once with a bogus timeout
341 * value, second time for real. The other (noncalibrating) CPUs
342 * call this function only once, with the real, calibrated value.
343 *
344 * We do reads before writes even if unnecessary, to get around the
345 * P5 APIC double write bug.
346 */
__setup_APIC_LVTT(unsigned int clocks,int oneshot,int irqen)347 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
348 {
349 unsigned int lvtt_value, tmp_value;
350
351 lvtt_value = LOCAL_TIMER_VECTOR;
352 if (!oneshot)
353 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
354 if (!lapic_is_integrated())
355 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
356
357 if (!irqen)
358 lvtt_value |= APIC_LVT_MASKED;
359
360 apic_write(APIC_LVTT, lvtt_value);
361
362 /*
363 * Divide PICLK by 16
364 */
365 tmp_value = apic_read(APIC_TDCR);
366 apic_write(APIC_TDCR,
367 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
368 APIC_TDR_DIV_16);
369
370 if (!oneshot)
371 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
372 }
373
374 /*
375 * Setup extended LVT, AMD specific (K8, family 10h)
376 *
377 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
378 * MCE interrupts are supported. Thus MCE offset must be set to 0.
379 *
380 * If mask=1, the LVT entry does not generate interrupts while mask=0
381 * enables the vector. See also the BKDGs.
382 */
383
384 #define APIC_EILVT_LVTOFF_MCE 0
385 #define APIC_EILVT_LVTOFF_IBS 1
386
setup_APIC_eilvt(u8 lvt_off,u8 vector,u8 msg_type,u8 mask)387 static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask)
388 {
389 unsigned long reg = (lvt_off << 4) + APIC_EILVT0;
390 unsigned int v = (mask << 16) | (msg_type << 8) | vector;
391
392 apic_write(reg, v);
393 }
394
setup_APIC_eilvt_mce(u8 vector,u8 msg_type,u8 mask)395 u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask)
396 {
397 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask);
398 return APIC_EILVT_LVTOFF_MCE;
399 }
400
setup_APIC_eilvt_ibs(u8 vector,u8 msg_type,u8 mask)401 u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask)
402 {
403 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask);
404 return APIC_EILVT_LVTOFF_IBS;
405 }
406 EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs);
407
408 /*
409 * Program the next event, relative to now
410 */
lapic_next_event(unsigned long delta,struct clock_event_device * evt)411 static int lapic_next_event(unsigned long delta,
412 struct clock_event_device *evt)
413 {
414 apic_write(APIC_TMICT, delta);
415 return 0;
416 }
417
418 /*
419 * Setup the lapic timer in periodic or oneshot mode
420 */
lapic_timer_setup(enum clock_event_mode mode,struct clock_event_device * evt)421 static void lapic_timer_setup(enum clock_event_mode mode,
422 struct clock_event_device *evt)
423 {
424 unsigned long flags;
425 unsigned int v;
426
427 /* Lapic used as dummy for broadcast ? */
428 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
429 return;
430
431 local_irq_save(flags);
432
433 switch (mode) {
434 case CLOCK_EVT_MODE_PERIODIC:
435 case CLOCK_EVT_MODE_ONESHOT:
436 __setup_APIC_LVTT(calibration_result,
437 mode != CLOCK_EVT_MODE_PERIODIC, 1);
438 break;
439 case CLOCK_EVT_MODE_UNUSED:
440 case CLOCK_EVT_MODE_SHUTDOWN:
441 v = apic_read(APIC_LVTT);
442 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
443 apic_write(APIC_LVTT, v);
444 apic_write(APIC_TMICT, 0xffffffff);
445 break;
446 case CLOCK_EVT_MODE_RESUME:
447 /* Nothing to do here */
448 break;
449 }
450
451 local_irq_restore(flags);
452 }
453
454 /*
455 * Local APIC timer broadcast function
456 */
lapic_timer_broadcast(const struct cpumask * mask)457 static void lapic_timer_broadcast(const struct cpumask *mask)
458 {
459 #ifdef CONFIG_SMP
460 send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
461 #endif
462 }
463
464 /*
465 * Setup the local APIC timer for this CPU. Copy the initilized values
466 * of the boot CPU and register the clock event in the framework.
467 */
setup_APIC_timer(void)468 static void __cpuinit setup_APIC_timer(void)
469 {
470 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
471
472 memcpy(levt, &lapic_clockevent, sizeof(*levt));
473 levt->cpumask = cpumask_of(smp_processor_id());
474
475 clockevents_register_device(levt);
476 }
477
478 /*
479 * In this functions we calibrate APIC bus clocks to the external timer.
480 *
481 * We want to do the calibration only once since we want to have local timer
482 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
483 * frequency.
484 *
485 * This was previously done by reading the PIT/HPET and waiting for a wrap
486 * around to find out, that a tick has elapsed. I have a box, where the PIT
487 * readout is broken, so it never gets out of the wait loop again. This was
488 * also reported by others.
489 *
490 * Monitoring the jiffies value is inaccurate and the clockevents
491 * infrastructure allows us to do a simple substitution of the interrupt
492 * handler.
493 *
494 * The calibration routine also uses the pm_timer when possible, as the PIT
495 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
496 * back to normal later in the boot process).
497 */
498
499 #define LAPIC_CAL_LOOPS (HZ/10)
500
501 static __initdata int lapic_cal_loops = -1;
502 static __initdata long lapic_cal_t1, lapic_cal_t2;
503 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
504 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
505 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
506
507 /*
508 * Temporary interrupt handler.
509 */
lapic_cal_handler(struct clock_event_device * dev)510 static void __init lapic_cal_handler(struct clock_event_device *dev)
511 {
512 unsigned long long tsc = 0;
513 long tapic = apic_read(APIC_TMCCT);
514 unsigned long pm = acpi_pm_read_early();
515
516 if (cpu_has_tsc)
517 rdtscll(tsc);
518
519 switch (lapic_cal_loops++) {
520 case 0:
521 lapic_cal_t1 = tapic;
522 lapic_cal_tsc1 = tsc;
523 lapic_cal_pm1 = pm;
524 lapic_cal_j1 = jiffies;
525 break;
526
527 case LAPIC_CAL_LOOPS:
528 lapic_cal_t2 = tapic;
529 lapic_cal_tsc2 = tsc;
530 if (pm < lapic_cal_pm1)
531 pm += ACPI_PM_OVRRUN;
532 lapic_cal_pm2 = pm;
533 lapic_cal_j2 = jiffies;
534 break;
535 }
536 }
537
calibrate_by_pmtimer(long deltapm,long * delta)538 static int __init calibrate_by_pmtimer(long deltapm, long *delta)
539 {
540 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
541 const long pm_thresh = pm_100ms / 100;
542 unsigned long mult;
543 u64 res;
544
545 #ifndef CONFIG_X86_PM_TIMER
546 return -1;
547 #endif
548
549 apic_printk(APIC_VERBOSE, "... PM timer delta = %ld\n", deltapm);
550
551 /* Check, if the PM timer is available */
552 if (!deltapm)
553 return -1;
554
555 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
556
557 if (deltapm > (pm_100ms - pm_thresh) &&
558 deltapm < (pm_100ms + pm_thresh)) {
559 apic_printk(APIC_VERBOSE, "... PM timer result ok\n");
560 } else {
561 res = (((u64)deltapm) * mult) >> 22;
562 do_div(res, 1000000);
563 pr_warning("APIC calibration not consistent "
564 "with PM Timer: %ldms instead of 100ms\n",
565 (long)res);
566 /* Correct the lapic counter value */
567 res = (((u64)(*delta)) * pm_100ms);
568 do_div(res, deltapm);
569 pr_info("APIC delta adjusted to PM-Timer: "
570 "%lu (%ld)\n", (unsigned long)res, *delta);
571 *delta = (long)res;
572 }
573
574 return 0;
575 }
576
calibrate_APIC_clock(void)577 static int __init calibrate_APIC_clock(void)
578 {
579 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
580 void (*real_handler)(struct clock_event_device *dev);
581 unsigned long deltaj;
582 long delta;
583 int pm_referenced = 0;
584
585 local_irq_disable();
586
587 /* Replace the global interrupt handler */
588 real_handler = global_clock_event->event_handler;
589 global_clock_event->event_handler = lapic_cal_handler;
590
591 /*
592 * Setup the APIC counter to maximum. There is no way the lapic
593 * can underflow in the 100ms detection time frame
594 */
595 __setup_APIC_LVTT(0xffffffff, 0, 0);
596
597 /* Let the interrupts run */
598 local_irq_enable();
599
600 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
601 cpu_relax();
602
603 local_irq_disable();
604
605 /* Restore the real event handler */
606 global_clock_event->event_handler = real_handler;
607
608 /* Build delta t1-t2 as apic timer counts down */
609 delta = lapic_cal_t1 - lapic_cal_t2;
610 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
611
612 /* we trust the PM based calibration if possible */
613 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
614 &delta);
615
616 /* Calculate the scaled math multiplication factor */
617 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
618 lapic_clockevent.shift);
619 lapic_clockevent.max_delta_ns =
620 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
621 lapic_clockevent.min_delta_ns =
622 clockevent_delta2ns(0xF, &lapic_clockevent);
623
624 calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
625
626 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
627 apic_printk(APIC_VERBOSE, "..... mult: %ld\n", lapic_clockevent.mult);
628 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
629 calibration_result);
630
631 if (cpu_has_tsc) {
632 delta = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
633 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
634 "%ld.%04ld MHz.\n",
635 (delta / LAPIC_CAL_LOOPS) / (1000000 / HZ),
636 (delta / LAPIC_CAL_LOOPS) % (1000000 / HZ));
637 }
638
639 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
640 "%u.%04u MHz.\n",
641 calibration_result / (1000000 / HZ),
642 calibration_result % (1000000 / HZ));
643
644 /*
645 * Do a sanity check on the APIC calibration result
646 */
647 if (calibration_result < (1000000 / HZ)) {
648 local_irq_enable();
649 pr_warning("APIC frequency too slow, disabling apic timer\n");
650 return -1;
651 }
652
653 levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
654
655 /*
656 * PM timer calibration failed or not turned on
657 * so lets try APIC timer based calibration
658 */
659 if (!pm_referenced) {
660 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
661
662 /*
663 * Setup the apic timer manually
664 */
665 levt->event_handler = lapic_cal_handler;
666 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt);
667 lapic_cal_loops = -1;
668
669 /* Let the interrupts run */
670 local_irq_enable();
671
672 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
673 cpu_relax();
674
675 /* Stop the lapic timer */
676 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt);
677
678 /* Jiffies delta */
679 deltaj = lapic_cal_j2 - lapic_cal_j1;
680 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
681
682 /* Check, if the jiffies result is consistent */
683 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
684 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
685 else
686 levt->features |= CLOCK_EVT_FEAT_DUMMY;
687 } else
688 local_irq_enable();
689
690 if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
691 pr_warning("APIC timer disabled due to verification failure\n");
692 return -1;
693 }
694
695 return 0;
696 }
697
698 /*
699 * Setup the boot APIC
700 *
701 * Calibrate and verify the result.
702 */
setup_boot_APIC_clock(void)703 void __init setup_boot_APIC_clock(void)
704 {
705 /*
706 * The local apic timer can be disabled via the kernel
707 * commandline or from the CPU detection code. Register the lapic
708 * timer as a dummy clock event source on SMP systems, so the
709 * broadcast mechanism is used. On UP systems simply ignore it.
710 */
711 if (disable_apic_timer) {
712 pr_info("Disabling APIC timer\n");
713 /* No broadcast on UP ! */
714 if (num_possible_cpus() > 1) {
715 lapic_clockevent.mult = 1;
716 setup_APIC_timer();
717 }
718 return;
719 }
720
721 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
722 "calibrating APIC timer ...\n");
723
724 if (calibrate_APIC_clock()) {
725 /* No broadcast on UP ! */
726 if (num_possible_cpus() > 1)
727 setup_APIC_timer();
728 return;
729 }
730
731 /*
732 * If nmi_watchdog is set to IO_APIC, we need the
733 * PIT/HPET going. Otherwise register lapic as a dummy
734 * device.
735 */
736 if (nmi_watchdog != NMI_IO_APIC)
737 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
738 else
739 pr_warning("APIC timer registered as dummy,"
740 " due to nmi_watchdog=%d!\n", nmi_watchdog);
741
742 /* Setup the lapic or request the broadcast */
743 setup_APIC_timer();
744 }
745
setup_secondary_APIC_clock(void)746 void __cpuinit setup_secondary_APIC_clock(void)
747 {
748 setup_APIC_timer();
749 }
750
751 /*
752 * The guts of the apic timer interrupt
753 */
local_apic_timer_interrupt(void)754 static void local_apic_timer_interrupt(void)
755 {
756 int cpu = smp_processor_id();
757 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
758
759 /*
760 * Normally we should not be here till LAPIC has been initialized but
761 * in some cases like kdump, its possible that there is a pending LAPIC
762 * timer interrupt from previous kernel's context and is delivered in
763 * new kernel the moment interrupts are enabled.
764 *
765 * Interrupts are enabled early and LAPIC is setup much later, hence
766 * its possible that when we get here evt->event_handler is NULL.
767 * Check for event_handler being NULL and discard the interrupt as
768 * spurious.
769 */
770 if (!evt->event_handler) {
771 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu);
772 /* Switch it off */
773 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
774 return;
775 }
776
777 /*
778 * the NMI deadlock-detector uses this.
779 */
780 inc_irq_stat(apic_timer_irqs);
781
782 evt->event_handler(evt);
783 }
784
785 /*
786 * Local APIC timer interrupt. This is the most natural way for doing
787 * local interrupts, but local timer interrupts can be emulated by
788 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
789 *
790 * [ if a single-CPU system runs an SMP kernel then we call the local
791 * interrupt as well. Thus we cannot inline the local irq ... ]
792 */
smp_apic_timer_interrupt(struct pt_regs * regs)793 void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs)
794 {
795 struct pt_regs *old_regs = set_irq_regs(regs);
796
797 /*
798 * NOTE! We'd better ACK the irq immediately,
799 * because timer handling can be slow.
800 */
801 ack_APIC_irq();
802 /*
803 * update_process_times() expects us to have done irq_enter().
804 * Besides, if we don't timer interrupts ignore the global
805 * interrupt lock, which is the WrongThing (tm) to do.
806 */
807 exit_idle();
808 irq_enter();
809 local_apic_timer_interrupt();
810 irq_exit();
811
812 set_irq_regs(old_regs);
813 }
814
setup_profiling_timer(unsigned int multiplier)815 int setup_profiling_timer(unsigned int multiplier)
816 {
817 return -EINVAL;
818 }
819
820 /*
821 * Local APIC start and shutdown
822 */
823
824 /**
825 * clear_local_APIC - shutdown the local APIC
826 *
827 * This is called, when a CPU is disabled and before rebooting, so the state of
828 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
829 * leftovers during boot.
830 */
clear_local_APIC(void)831 void clear_local_APIC(void)
832 {
833 int maxlvt;
834 u32 v;
835
836 /* APIC hasn't been mapped yet */
837 if (!apic_phys)
838 return;
839
840 maxlvt = lapic_get_maxlvt();
841 /*
842 * Masking an LVT entry can trigger a local APIC error
843 * if the vector is zero. Mask LVTERR first to prevent this.
844 */
845 if (maxlvt >= 3) {
846 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
847 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
848 }
849 /*
850 * Careful: we have to set masks only first to deassert
851 * any level-triggered sources.
852 */
853 v = apic_read(APIC_LVTT);
854 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
855 v = apic_read(APIC_LVT0);
856 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
857 v = apic_read(APIC_LVT1);
858 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
859 if (maxlvt >= 4) {
860 v = apic_read(APIC_LVTPC);
861 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
862 }
863
864 /* lets not touch this if we didn't frob it */
865 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
866 if (maxlvt >= 5) {
867 v = apic_read(APIC_LVTTHMR);
868 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
869 }
870 #endif
871 /*
872 * Clean APIC state for other OSs:
873 */
874 apic_write(APIC_LVTT, APIC_LVT_MASKED);
875 apic_write(APIC_LVT0, APIC_LVT_MASKED);
876 apic_write(APIC_LVT1, APIC_LVT_MASKED);
877 if (maxlvt >= 3)
878 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
879 if (maxlvt >= 4)
880 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
881
882 /* Integrated APIC (!82489DX) ? */
883 if (lapic_is_integrated()) {
884 if (maxlvt > 3)
885 /* Clear ESR due to Pentium errata 3AP and 11AP */
886 apic_write(APIC_ESR, 0);
887 apic_read(APIC_ESR);
888 }
889 }
890
891 /**
892 * disable_local_APIC - clear and disable the local APIC
893 */
disable_local_APIC(void)894 void disable_local_APIC(void)
895 {
896 unsigned int value;
897
898 /* APIC hasn't been mapped yet */
899 if (!apic_phys)
900 return;
901
902 clear_local_APIC();
903
904 /*
905 * Disable APIC (implies clearing of registers
906 * for 82489DX!).
907 */
908 value = apic_read(APIC_SPIV);
909 value &= ~APIC_SPIV_APIC_ENABLED;
910 apic_write(APIC_SPIV, value);
911
912 #ifdef CONFIG_X86_32
913 /*
914 * When LAPIC was disabled by the BIOS and enabled by the kernel,
915 * restore the disabled state.
916 */
917 if (enabled_via_apicbase) {
918 unsigned int l, h;
919
920 rdmsr(MSR_IA32_APICBASE, l, h);
921 l &= ~MSR_IA32_APICBASE_ENABLE;
922 wrmsr(MSR_IA32_APICBASE, l, h);
923 }
924 #endif
925 }
926
927 /*
928 * If Linux enabled the LAPIC against the BIOS default disable it down before
929 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
930 * not power-off. Additionally clear all LVT entries before disable_local_APIC
931 * for the case where Linux didn't enable the LAPIC.
932 */
lapic_shutdown(void)933 void lapic_shutdown(void)
934 {
935 unsigned long flags;
936
937 if (!cpu_has_apic)
938 return;
939
940 local_irq_save(flags);
941
942 #ifdef CONFIG_X86_32
943 if (!enabled_via_apicbase)
944 clear_local_APIC();
945 else
946 #endif
947 disable_local_APIC();
948
949
950 local_irq_restore(flags);
951 }
952
953 /*
954 * This is to verify that we're looking at a real local APIC.
955 * Check these against your board if the CPUs aren't getting
956 * started for no apparent reason.
957 */
verify_local_APIC(void)958 int __init verify_local_APIC(void)
959 {
960 unsigned int reg0, reg1;
961
962 /*
963 * The version register is read-only in a real APIC.
964 */
965 reg0 = apic_read(APIC_LVR);
966 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
967 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
968 reg1 = apic_read(APIC_LVR);
969 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
970
971 /*
972 * The two version reads above should print the same
973 * numbers. If the second one is different, then we
974 * poke at a non-APIC.
975 */
976 if (reg1 != reg0)
977 return 0;
978
979 /*
980 * Check if the version looks reasonably.
981 */
982 reg1 = GET_APIC_VERSION(reg0);
983 if (reg1 == 0x00 || reg1 == 0xff)
984 return 0;
985 reg1 = lapic_get_maxlvt();
986 if (reg1 < 0x02 || reg1 == 0xff)
987 return 0;
988
989 /*
990 * The ID register is read/write in a real APIC.
991 */
992 reg0 = apic_read(APIC_ID);
993 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
994 apic_write(APIC_ID, reg0 ^ APIC_ID_MASK);
995 reg1 = apic_read(APIC_ID);
996 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
997 apic_write(APIC_ID, reg0);
998 if (reg1 != (reg0 ^ APIC_ID_MASK))
999 return 0;
1000
1001 /*
1002 * The next two are just to see if we have sane values.
1003 * They're only really relevant if we're in Virtual Wire
1004 * compatibility mode, but most boxes are anymore.
1005 */
1006 reg0 = apic_read(APIC_LVT0);
1007 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
1008 reg1 = apic_read(APIC_LVT1);
1009 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
1010
1011 return 1;
1012 }
1013
1014 /**
1015 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1016 */
sync_Arb_IDs(void)1017 void __init sync_Arb_IDs(void)
1018 {
1019 /*
1020 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1021 * needed on AMD.
1022 */
1023 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1024 return;
1025
1026 /*
1027 * Wait for idle.
1028 */
1029 apic_wait_icr_idle();
1030
1031 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
1032 apic_write(APIC_ICR, APIC_DEST_ALLINC |
1033 APIC_INT_LEVELTRIG | APIC_DM_INIT);
1034 }
1035
1036 /*
1037 * An initial setup of the virtual wire mode.
1038 */
init_bsp_APIC(void)1039 void __init init_bsp_APIC(void)
1040 {
1041 unsigned int value;
1042
1043 /*
1044 * Don't do the setup now if we have a SMP BIOS as the
1045 * through-I/O-APIC virtual wire mode might be active.
1046 */
1047 if (smp_found_config || !cpu_has_apic)
1048 return;
1049
1050 /*
1051 * Do not trust the local APIC being empty at bootup.
1052 */
1053 clear_local_APIC();
1054
1055 /*
1056 * Enable APIC.
1057 */
1058 value = apic_read(APIC_SPIV);
1059 value &= ~APIC_VECTOR_MASK;
1060 value |= APIC_SPIV_APIC_ENABLED;
1061
1062 #ifdef CONFIG_X86_32
1063 /* This bit is reserved on P4/Xeon and should be cleared */
1064 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
1065 (boot_cpu_data.x86 == 15))
1066 value &= ~APIC_SPIV_FOCUS_DISABLED;
1067 else
1068 #endif
1069 value |= APIC_SPIV_FOCUS_DISABLED;
1070 value |= SPURIOUS_APIC_VECTOR;
1071 apic_write(APIC_SPIV, value);
1072
1073 /*
1074 * Set up the virtual wire mode.
1075 */
1076 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1077 value = APIC_DM_NMI;
1078 if (!lapic_is_integrated()) /* 82489DX */
1079 value |= APIC_LVT_LEVEL_TRIGGER;
1080 apic_write(APIC_LVT1, value);
1081 }
1082
lapic_setup_esr(void)1083 static void __cpuinit lapic_setup_esr(void)
1084 {
1085 unsigned int oldvalue, value, maxlvt;
1086
1087 if (!lapic_is_integrated()) {
1088 pr_info("No ESR for 82489DX.\n");
1089 return;
1090 }
1091
1092 if (esr_disable) {
1093 /*
1094 * Something untraceable is creating bad interrupts on
1095 * secondary quads ... for the moment, just leave the
1096 * ESR disabled - we can't do anything useful with the
1097 * errors anyway - mbligh
1098 */
1099 pr_info("Leaving ESR disabled.\n");
1100 return;
1101 }
1102
1103 maxlvt = lapic_get_maxlvt();
1104 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1105 apic_write(APIC_ESR, 0);
1106 oldvalue = apic_read(APIC_ESR);
1107
1108 /* enables sending errors */
1109 value = ERROR_APIC_VECTOR;
1110 apic_write(APIC_LVTERR, value);
1111
1112 /*
1113 * spec says clear errors after enabling vector.
1114 */
1115 if (maxlvt > 3)
1116 apic_write(APIC_ESR, 0);
1117 value = apic_read(APIC_ESR);
1118 if (value != oldvalue)
1119 apic_printk(APIC_VERBOSE, "ESR value before enabling "
1120 "vector: 0x%08x after: 0x%08x\n",
1121 oldvalue, value);
1122 }
1123
1124
1125 /**
1126 * setup_local_APIC - setup the local APIC
1127 */
setup_local_APIC(void)1128 void __cpuinit setup_local_APIC(void)
1129 {
1130 unsigned int value;
1131 int i, j;
1132
1133 #ifdef CONFIG_X86_32
1134 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1135 if (lapic_is_integrated() && esr_disable) {
1136 apic_write(APIC_ESR, 0);
1137 apic_write(APIC_ESR, 0);
1138 apic_write(APIC_ESR, 0);
1139 apic_write(APIC_ESR, 0);
1140 }
1141 #endif
1142
1143 preempt_disable();
1144
1145 /*
1146 * Double-check whether this APIC is really registered.
1147 * This is meaningless in clustered apic mode, so we skip it.
1148 */
1149 if (!apic_id_registered())
1150 BUG();
1151
1152 /*
1153 * Intel recommends to set DFR, LDR and TPR before enabling
1154 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1155 * document number 292116). So here it goes...
1156 */
1157 init_apic_ldr();
1158
1159 /*
1160 * Set Task Priority to 'accept all'. We never change this
1161 * later on.
1162 */
1163 value = apic_read(APIC_TASKPRI);
1164 value &= ~APIC_TPRI_MASK;
1165 apic_write(APIC_TASKPRI, value);
1166
1167 /*
1168 * After a crash, we no longer service the interrupts and a pending
1169 * interrupt from previous kernel might still have ISR bit set.
1170 *
1171 * Most probably by now CPU has serviced that pending interrupt and
1172 * it might not have done the ack_APIC_irq() because it thought,
1173 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1174 * does not clear the ISR bit and cpu thinks it has already serivced
1175 * the interrupt. Hence a vector might get locked. It was noticed
1176 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1177 */
1178 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
1179 value = apic_read(APIC_ISR + i*0x10);
1180 for (j = 31; j >= 0; j--) {
1181 if (value & (1<<j))
1182 ack_APIC_irq();
1183 }
1184 }
1185
1186 /*
1187 * Now that we are all set up, enable the APIC
1188 */
1189 value = apic_read(APIC_SPIV);
1190 value &= ~APIC_VECTOR_MASK;
1191 /*
1192 * Enable APIC
1193 */
1194 value |= APIC_SPIV_APIC_ENABLED;
1195
1196 #ifdef CONFIG_X86_32
1197 /*
1198 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1199 * certain networking cards. If high frequency interrupts are
1200 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1201 * entry is masked/unmasked at a high rate as well then sooner or
1202 * later IOAPIC line gets 'stuck', no more interrupts are received
1203 * from the device. If focus CPU is disabled then the hang goes
1204 * away, oh well :-(
1205 *
1206 * [ This bug can be reproduced easily with a level-triggered
1207 * PCI Ne2000 networking cards and PII/PIII processors, dual
1208 * BX chipset. ]
1209 */
1210 /*
1211 * Actually disabling the focus CPU check just makes the hang less
1212 * frequent as it makes the interrupt distributon model be more
1213 * like LRU than MRU (the short-term load is more even across CPUs).
1214 * See also the comment in end_level_ioapic_irq(). --macro
1215 */
1216
1217 /*
1218 * - enable focus processor (bit==0)
1219 * - 64bit mode always use processor focus
1220 * so no need to set it
1221 */
1222 value &= ~APIC_SPIV_FOCUS_DISABLED;
1223 #endif
1224
1225 /*
1226 * Set spurious IRQ vector
1227 */
1228 value |= SPURIOUS_APIC_VECTOR;
1229 apic_write(APIC_SPIV, value);
1230
1231 /*
1232 * Set up LVT0, LVT1:
1233 *
1234 * set up through-local-APIC on the BP's LINT0. This is not
1235 * strictly necessary in pure symmetric-IO mode, but sometimes
1236 * we delegate interrupts to the 8259A.
1237 */
1238 /*
1239 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1240 */
1241 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1242 if (!smp_processor_id() && (pic_mode || !value)) {
1243 value = APIC_DM_EXTINT;
1244 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
1245 smp_processor_id());
1246 } else {
1247 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1248 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
1249 smp_processor_id());
1250 }
1251 apic_write(APIC_LVT0, value);
1252
1253 /*
1254 * only the BP should see the LINT1 NMI signal, obviously.
1255 */
1256 if (!smp_processor_id())
1257 value = APIC_DM_NMI;
1258 else
1259 value = APIC_DM_NMI | APIC_LVT_MASKED;
1260 if (!lapic_is_integrated()) /* 82489DX */
1261 value |= APIC_LVT_LEVEL_TRIGGER;
1262 apic_write(APIC_LVT1, value);
1263
1264 preempt_enable();
1265 }
1266
end_local_APIC_setup(void)1267 void __cpuinit end_local_APIC_setup(void)
1268 {
1269 lapic_setup_esr();
1270
1271 #ifdef CONFIG_X86_32
1272 {
1273 unsigned int value;
1274 /* Disable the local apic timer */
1275 value = apic_read(APIC_LVTT);
1276 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1277 apic_write(APIC_LVTT, value);
1278 }
1279 #endif
1280
1281 setup_apic_nmi_watchdog(NULL);
1282 apic_pm_activate();
1283 }
1284
1285 #ifdef HAVE_X2APIC
check_x2apic(void)1286 void check_x2apic(void)
1287 {
1288 int msr, msr2;
1289
1290 rdmsr(MSR_IA32_APICBASE, msr, msr2);
1291
1292 if (msr & X2APIC_ENABLE) {
1293 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
1294 x2apic_preenabled = x2apic = 1;
1295 apic_ops = &x2apic_ops;
1296 }
1297 }
1298
enable_x2apic(void)1299 void enable_x2apic(void)
1300 {
1301 int msr, msr2;
1302
1303 rdmsr(MSR_IA32_APICBASE, msr, msr2);
1304 if (!(msr & X2APIC_ENABLE)) {
1305 pr_info("Enabling x2apic\n");
1306 wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0);
1307 }
1308 }
1309
enable_IR_x2apic(void)1310 void __init enable_IR_x2apic(void)
1311 {
1312 #ifdef CONFIG_INTR_REMAP
1313 int ret;
1314 unsigned long flags;
1315
1316 if (!cpu_has_x2apic)
1317 return;
1318
1319 if (!x2apic_preenabled && disable_x2apic) {
1320 pr_info("Skipped enabling x2apic and Interrupt-remapping "
1321 "because of nox2apic\n");
1322 return;
1323 }
1324
1325 if (x2apic_preenabled && disable_x2apic)
1326 panic("Bios already enabled x2apic, can't enforce nox2apic");
1327
1328 if (!x2apic_preenabled && skip_ioapic_setup) {
1329 pr_info("Skipped enabling x2apic and Interrupt-remapping "
1330 "because of skipping io-apic setup\n");
1331 return;
1332 }
1333
1334 ret = dmar_table_init();
1335 if (ret) {
1336 pr_info("dmar_table_init() failed with %d:\n", ret);
1337
1338 if (x2apic_preenabled)
1339 panic("x2apic enabled by bios. But IR enabling failed");
1340 else
1341 pr_info("Not enabling x2apic,Intr-remapping\n");
1342 return;
1343 }
1344
1345 local_irq_save(flags);
1346 mask_8259A();
1347
1348 ret = save_mask_IO_APIC_setup();
1349 if (ret) {
1350 pr_info("Saving IO-APIC state failed: %d\n", ret);
1351 goto end;
1352 }
1353
1354 ret = enable_intr_remapping(1);
1355
1356 if (ret && x2apic_preenabled) {
1357 local_irq_restore(flags);
1358 panic("x2apic enabled by bios. But IR enabling failed");
1359 }
1360
1361 if (ret)
1362 goto end_restore;
1363
1364 if (!x2apic) {
1365 x2apic = 1;
1366 apic_ops = &x2apic_ops;
1367 enable_x2apic();
1368 }
1369
1370 end_restore:
1371 if (ret)
1372 /*
1373 * IR enabling failed
1374 */
1375 restore_IO_APIC_setup();
1376 else
1377 reinit_intr_remapped_IO_APIC(x2apic_preenabled);
1378
1379 end:
1380 unmask_8259A();
1381 local_irq_restore(flags);
1382
1383 if (!ret) {
1384 if (!x2apic_preenabled)
1385 pr_info("Enabled x2apic and interrupt-remapping\n");
1386 else
1387 pr_info("Enabled Interrupt-remapping\n");
1388 } else
1389 pr_err("Failed to enable Interrupt-remapping and x2apic\n");
1390 #else
1391 if (!cpu_has_x2apic)
1392 return;
1393
1394 if (x2apic_preenabled)
1395 panic("x2apic enabled prior OS handover,"
1396 " enable CONFIG_INTR_REMAP");
1397
1398 pr_info("Enable CONFIG_INTR_REMAP for enabling intr-remapping "
1399 " and x2apic\n");
1400 #endif
1401
1402 return;
1403 }
1404 #endif /* HAVE_X2APIC */
1405
1406 #ifdef CONFIG_X86_64
1407 /*
1408 * Detect and enable local APICs on non-SMP boards.
1409 * Original code written by Keir Fraser.
1410 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1411 * not correctly set up (usually the APIC timer won't work etc.)
1412 */
detect_init_APIC(void)1413 static int __init detect_init_APIC(void)
1414 {
1415 if (!cpu_has_apic) {
1416 pr_info("No local APIC present\n");
1417 return -1;
1418 }
1419
1420 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1421 boot_cpu_physical_apicid = 0;
1422 return 0;
1423 }
1424 #else
1425 /*
1426 * Detect and initialize APIC
1427 */
detect_init_APIC(void)1428 static int __init detect_init_APIC(void)
1429 {
1430 u32 h, l, features;
1431
1432 /* Disabled by kernel option? */
1433 if (disable_apic)
1434 return -1;
1435
1436 switch (boot_cpu_data.x86_vendor) {
1437 case X86_VENDOR_AMD:
1438 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1439 (boot_cpu_data.x86 >= 15))
1440 break;
1441 goto no_apic;
1442 case X86_VENDOR_INTEL:
1443 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1444 (boot_cpu_data.x86 == 5 && cpu_has_apic))
1445 break;
1446 goto no_apic;
1447 default:
1448 goto no_apic;
1449 }
1450
1451 if (!cpu_has_apic) {
1452 /*
1453 * Over-ride BIOS and try to enable the local APIC only if
1454 * "lapic" specified.
1455 */
1456 if (!force_enable_local_apic) {
1457 pr_info("Local APIC disabled by BIOS -- "
1458 "you can enable it with \"lapic\"\n");
1459 return -1;
1460 }
1461 /*
1462 * Some BIOSes disable the local APIC in the APIC_BASE
1463 * MSR. This can only be done in software for Intel P6 or later
1464 * and AMD K7 (Model > 1) or later.
1465 */
1466 rdmsr(MSR_IA32_APICBASE, l, h);
1467 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1468 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1469 l &= ~MSR_IA32_APICBASE_BASE;
1470 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
1471 wrmsr(MSR_IA32_APICBASE, l, h);
1472 enabled_via_apicbase = 1;
1473 }
1474 }
1475 /*
1476 * The APIC feature bit should now be enabled
1477 * in `cpuid'
1478 */
1479 features = cpuid_edx(1);
1480 if (!(features & (1 << X86_FEATURE_APIC))) {
1481 pr_warning("Could not enable APIC!\n");
1482 return -1;
1483 }
1484 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1485 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1486
1487 /* The BIOS may have set up the APIC at some other address */
1488 rdmsr(MSR_IA32_APICBASE, l, h);
1489 if (l & MSR_IA32_APICBASE_ENABLE)
1490 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1491
1492 pr_info("Found and enabled local APIC!\n");
1493
1494 apic_pm_activate();
1495
1496 return 0;
1497
1498 no_apic:
1499 pr_info("No local APIC present or hardware disabled\n");
1500 return -1;
1501 }
1502 #endif
1503
1504 #ifdef CONFIG_X86_64
early_init_lapic_mapping(void)1505 void __init early_init_lapic_mapping(void)
1506 {
1507 unsigned long phys_addr;
1508
1509 /*
1510 * If no local APIC can be found then go out
1511 * : it means there is no mpatable and MADT
1512 */
1513 if (!smp_found_config)
1514 return;
1515
1516 phys_addr = mp_lapic_addr;
1517
1518 set_fixmap_nocache(FIX_APIC_BASE, phys_addr);
1519 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1520 APIC_BASE, phys_addr);
1521
1522 /*
1523 * Fetch the APIC ID of the BSP in case we have a
1524 * default configuration (or the MP table is broken).
1525 */
1526 boot_cpu_physical_apicid = read_apic_id();
1527 }
1528 #endif
1529
1530 /**
1531 * init_apic_mappings - initialize APIC mappings
1532 */
init_apic_mappings(void)1533 void __init init_apic_mappings(void)
1534 {
1535 #ifdef HAVE_X2APIC
1536 if (x2apic) {
1537 boot_cpu_physical_apicid = read_apic_id();
1538 return;
1539 }
1540 #endif
1541
1542 /*
1543 * If no local APIC can be found then set up a fake all
1544 * zeroes page to simulate the local APIC and another
1545 * one for the IO-APIC.
1546 */
1547 if (!smp_found_config && detect_init_APIC()) {
1548 apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
1549 apic_phys = __pa(apic_phys);
1550 } else
1551 apic_phys = mp_lapic_addr;
1552
1553 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
1554 apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n",
1555 APIC_BASE, apic_phys);
1556
1557 /*
1558 * Fetch the APIC ID of the BSP in case we have a
1559 * default configuration (or the MP table is broken).
1560 */
1561 if (boot_cpu_physical_apicid == -1U)
1562 boot_cpu_physical_apicid = read_apic_id();
1563 }
1564
1565 /*
1566 * This initializes the IO-APIC and APIC hardware if this is
1567 * a UP kernel.
1568 */
1569 int apic_version[MAX_APICS];
1570
APIC_init_uniprocessor(void)1571 int __init APIC_init_uniprocessor(void)
1572 {
1573 #ifdef CONFIG_X86_64
1574 if (disable_apic) {
1575 pr_info("Apic disabled\n");
1576 return -1;
1577 }
1578 if (!cpu_has_apic) {
1579 disable_apic = 1;
1580 pr_info("Apic disabled by BIOS\n");
1581 return -1;
1582 }
1583 #else
1584 if (!smp_found_config && !cpu_has_apic)
1585 return -1;
1586
1587 /*
1588 * Complain if the BIOS pretends there is one.
1589 */
1590 if (!cpu_has_apic &&
1591 APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
1592 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
1593 boot_cpu_physical_apicid);
1594 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1595 return -1;
1596 }
1597 #endif
1598
1599 #ifdef HAVE_X2APIC
1600 enable_IR_x2apic();
1601 #endif
1602 #ifdef CONFIG_X86_64
1603 setup_apic_routing();
1604 #endif
1605
1606 verify_local_APIC();
1607 connect_bsp_APIC();
1608
1609 #ifdef CONFIG_X86_64
1610 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
1611 #else
1612 /*
1613 * Hack: In case of kdump, after a crash, kernel might be booting
1614 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1615 * might be zero if read from MP tables. Get it from LAPIC.
1616 */
1617 # ifdef CONFIG_CRASH_DUMP
1618 boot_cpu_physical_apicid = read_apic_id();
1619 # endif
1620 #endif
1621 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1622 setup_local_APIC();
1623
1624 #ifdef CONFIG_X86_64
1625 /*
1626 * Now enable IO-APICs, actually call clear_IO_APIC
1627 * We need clear_IO_APIC before enabling vector on BP
1628 */
1629 if (!skip_ioapic_setup && nr_ioapics)
1630 enable_IO_APIC();
1631 #endif
1632
1633 #ifdef CONFIG_X86_IO_APIC
1634 if (!smp_found_config || skip_ioapic_setup || !nr_ioapics)
1635 #endif
1636 localise_nmi_watchdog();
1637 end_local_APIC_setup();
1638
1639 #ifdef CONFIG_X86_IO_APIC
1640 if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
1641 setup_IO_APIC();
1642 # ifdef CONFIG_X86_64
1643 else
1644 nr_ioapics = 0;
1645 # endif
1646 #endif
1647
1648 #ifdef CONFIG_X86_64
1649 setup_boot_APIC_clock();
1650 check_nmi_watchdog();
1651 #else
1652 setup_boot_clock();
1653 #endif
1654
1655 return 0;
1656 }
1657
1658 /*
1659 * Local APIC interrupts
1660 */
1661
1662 /*
1663 * This interrupt should _never_ happen with our APIC/SMP architecture
1664 */
smp_spurious_interrupt(struct pt_regs * regs)1665 void smp_spurious_interrupt(struct pt_regs *regs)
1666 {
1667 u32 v;
1668
1669 exit_idle();
1670 irq_enter();
1671 /*
1672 * Check if this really is a spurious interrupt and ACK it
1673 * if it is a vectored one. Just in case...
1674 * Spurious interrupts should not be ACKed.
1675 */
1676 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1677 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1678 ack_APIC_irq();
1679
1680 inc_irq_stat(irq_spurious_count);
1681
1682 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1683 pr_info("spurious APIC interrupt on CPU#%d, "
1684 "should never happen.\n", smp_processor_id());
1685 irq_exit();
1686 }
1687
1688 /*
1689 * This interrupt should never happen with our APIC/SMP architecture
1690 */
smp_error_interrupt(struct pt_regs * regs)1691 void smp_error_interrupt(struct pt_regs *regs)
1692 {
1693 u32 v, v1;
1694
1695 exit_idle();
1696 irq_enter();
1697 /* First tickle the hardware, only then report what went on. -- REW */
1698 v = apic_read(APIC_ESR);
1699 apic_write(APIC_ESR, 0);
1700 v1 = apic_read(APIC_ESR);
1701 ack_APIC_irq();
1702 atomic_inc(&irq_err_count);
1703
1704 /*
1705 * Here is what the APIC error bits mean:
1706 * 0: Send CS error
1707 * 1: Receive CS error
1708 * 2: Send accept error
1709 * 3: Receive accept error
1710 * 4: Reserved
1711 * 5: Send illegal vector
1712 * 6: Received illegal vector
1713 * 7: Illegal register address
1714 */
1715 pr_debug("APIC error on CPU%d: %02x(%02x)\n",
1716 smp_processor_id(), v , v1);
1717 irq_exit();
1718 }
1719
1720 /**
1721 * connect_bsp_APIC - attach the APIC to the interrupt system
1722 */
connect_bsp_APIC(void)1723 void __init connect_bsp_APIC(void)
1724 {
1725 #ifdef CONFIG_X86_32
1726 if (pic_mode) {
1727 /*
1728 * Do not trust the local APIC being empty at bootup.
1729 */
1730 clear_local_APIC();
1731 /*
1732 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1733 * local APIC to INT and NMI lines.
1734 */
1735 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
1736 "enabling APIC mode.\n");
1737 outb(0x70, 0x22);
1738 outb(0x01, 0x23);
1739 }
1740 #endif
1741 enable_apic_mode();
1742 }
1743
1744 /**
1745 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1746 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1747 *
1748 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1749 * APIC is disabled.
1750 */
disconnect_bsp_APIC(int virt_wire_setup)1751 void disconnect_bsp_APIC(int virt_wire_setup)
1752 {
1753 unsigned int value;
1754
1755 #ifdef CONFIG_X86_32
1756 if (pic_mode) {
1757 /*
1758 * Put the board back into PIC mode (has an effect only on
1759 * certain older boards). Note that APIC interrupts, including
1760 * IPIs, won't work beyond this point! The only exception are
1761 * INIT IPIs.
1762 */
1763 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
1764 "entering PIC mode.\n");
1765 outb(0x70, 0x22);
1766 outb(0x00, 0x23);
1767 return;
1768 }
1769 #endif
1770
1771 /* Go back to Virtual Wire compatibility mode */
1772
1773 /* For the spurious interrupt use vector F, and enable it */
1774 value = apic_read(APIC_SPIV);
1775 value &= ~APIC_VECTOR_MASK;
1776 value |= APIC_SPIV_APIC_ENABLED;
1777 value |= 0xf;
1778 apic_write(APIC_SPIV, value);
1779
1780 if (!virt_wire_setup) {
1781 /*
1782 * For LVT0 make it edge triggered, active high,
1783 * external and enabled
1784 */
1785 value = apic_read(APIC_LVT0);
1786 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1787 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1788 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1789 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1790 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
1791 apic_write(APIC_LVT0, value);
1792 } else {
1793 /* Disable LVT0 */
1794 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1795 }
1796
1797 /*
1798 * For LVT1 make it edge triggered, active high,
1799 * nmi and enabled
1800 */
1801 value = apic_read(APIC_LVT1);
1802 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1803 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1804 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1805 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1806 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
1807 apic_write(APIC_LVT1, value);
1808 }
1809
generic_processor_info(int apicid,int version)1810 void __cpuinit generic_processor_info(int apicid, int version)
1811 {
1812 int cpu;
1813
1814 /*
1815 * Validate version
1816 */
1817 if (version == 0x0) {
1818 pr_warning("BIOS bug, APIC version is 0 for CPU#%d! "
1819 "fixing up to 0x10. (tell your hw vendor)\n",
1820 version);
1821 version = 0x10;
1822 }
1823 apic_version[apicid] = version;
1824
1825 if (num_processors >= nr_cpu_ids) {
1826 int max = nr_cpu_ids;
1827 int thiscpu = max + disabled_cpus;
1828
1829 pr_warning(
1830 "ACPI: NR_CPUS/possible_cpus limit of %i reached."
1831 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
1832
1833 disabled_cpus++;
1834 return;
1835 }
1836
1837 num_processors++;
1838 cpu = cpumask_next_zero(-1, cpu_present_mask);
1839
1840 if (version != apic_version[boot_cpu_physical_apicid])
1841 WARN_ONCE(1,
1842 "ACPI: apic version mismatch, bootcpu: %x cpu %d: %x\n",
1843 apic_version[boot_cpu_physical_apicid], cpu, version);
1844
1845 physid_set(apicid, phys_cpu_present_map);
1846 if (apicid == boot_cpu_physical_apicid) {
1847 /*
1848 * x86_bios_cpu_apicid is required to have processors listed
1849 * in same order as logical cpu numbers. Hence the first
1850 * entry is BSP, and so on.
1851 */
1852 cpu = 0;
1853 }
1854 if (apicid > max_physical_apicid)
1855 max_physical_apicid = apicid;
1856
1857 #ifdef CONFIG_X86_32
1858 /*
1859 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1860 * but we need to work other dependencies like SMP_SUSPEND etc
1861 * before this can be done without some confusion.
1862 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1863 * - Ashok Raj <ashok.raj@intel.com>
1864 */
1865 if (max_physical_apicid >= 8) {
1866 switch (boot_cpu_data.x86_vendor) {
1867 case X86_VENDOR_INTEL:
1868 if (!APIC_XAPIC(version)) {
1869 def_to_bigsmp = 0;
1870 break;
1871 }
1872 /* If P4 and above fall through */
1873 case X86_VENDOR_AMD:
1874 def_to_bigsmp = 1;
1875 }
1876 }
1877 #endif
1878
1879 #if defined(CONFIG_X86_SMP) || defined(CONFIG_X86_64)
1880 /* are we being called early in kernel startup? */
1881 if (early_per_cpu_ptr(x86_cpu_to_apicid)) {
1882 u16 *cpu_to_apicid = early_per_cpu_ptr(x86_cpu_to_apicid);
1883 u16 *bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
1884
1885 cpu_to_apicid[cpu] = apicid;
1886 bios_cpu_apicid[cpu] = apicid;
1887 } else {
1888 per_cpu(x86_cpu_to_apicid, cpu) = apicid;
1889 per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
1890 }
1891 #endif
1892
1893 set_cpu_possible(cpu, true);
1894 set_cpu_present(cpu, true);
1895 }
1896
1897 #ifdef CONFIG_X86_64
hard_smp_processor_id(void)1898 int hard_smp_processor_id(void)
1899 {
1900 return read_apic_id();
1901 }
1902 #endif
1903
1904 /*
1905 * Power management
1906 */
1907 #ifdef CONFIG_PM
1908
1909 static struct {
1910 /*
1911 * 'active' is true if the local APIC was enabled by us and
1912 * not the BIOS; this signifies that we are also responsible
1913 * for disabling it before entering apm/acpi suspend
1914 */
1915 int active;
1916 /* r/w apic fields */
1917 unsigned int apic_id;
1918 unsigned int apic_taskpri;
1919 unsigned int apic_ldr;
1920 unsigned int apic_dfr;
1921 unsigned int apic_spiv;
1922 unsigned int apic_lvtt;
1923 unsigned int apic_lvtpc;
1924 unsigned int apic_lvt0;
1925 unsigned int apic_lvt1;
1926 unsigned int apic_lvterr;
1927 unsigned int apic_tmict;
1928 unsigned int apic_tdcr;
1929 unsigned int apic_thmr;
1930 } apic_pm_state;
1931
lapic_suspend(struct sys_device * dev,pm_message_t state)1932 static int lapic_suspend(struct sys_device *dev, pm_message_t state)
1933 {
1934 unsigned long flags;
1935 int maxlvt;
1936
1937 if (!apic_pm_state.active)
1938 return 0;
1939
1940 maxlvt = lapic_get_maxlvt();
1941
1942 apic_pm_state.apic_id = apic_read(APIC_ID);
1943 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
1944 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
1945 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
1946 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
1947 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
1948 if (maxlvt >= 4)
1949 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
1950 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
1951 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
1952 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
1953 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
1954 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
1955 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1956 if (maxlvt >= 5)
1957 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
1958 #endif
1959
1960 local_irq_save(flags);
1961 disable_local_APIC();
1962 local_irq_restore(flags);
1963 return 0;
1964 }
1965
lapic_resume(struct sys_device * dev)1966 static int lapic_resume(struct sys_device *dev)
1967 {
1968 unsigned int l, h;
1969 unsigned long flags;
1970 int maxlvt;
1971
1972 if (!apic_pm_state.active)
1973 return 0;
1974
1975 maxlvt = lapic_get_maxlvt();
1976
1977 local_irq_save(flags);
1978
1979 #ifdef HAVE_X2APIC
1980 if (x2apic)
1981 enable_x2apic();
1982 else
1983 #endif
1984 {
1985 /*
1986 * Make sure the APICBASE points to the right address
1987 *
1988 * FIXME! This will be wrong if we ever support suspend on
1989 * SMP! We'll need to do this as part of the CPU restore!
1990 */
1991 rdmsr(MSR_IA32_APICBASE, l, h);
1992 l &= ~MSR_IA32_APICBASE_BASE;
1993 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
1994 wrmsr(MSR_IA32_APICBASE, l, h);
1995 }
1996
1997 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
1998 apic_write(APIC_ID, apic_pm_state.apic_id);
1999 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
2000 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
2001 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
2002 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
2003 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
2004 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
2005 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2006 if (maxlvt >= 5)
2007 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
2008 #endif
2009 if (maxlvt >= 4)
2010 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
2011 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
2012 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
2013 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
2014 apic_write(APIC_ESR, 0);
2015 apic_read(APIC_ESR);
2016 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
2017 apic_write(APIC_ESR, 0);
2018 apic_read(APIC_ESR);
2019
2020 local_irq_restore(flags);
2021
2022 return 0;
2023 }
2024
2025 /*
2026 * This device has no shutdown method - fully functioning local APICs
2027 * are needed on every CPU up until machine_halt/restart/poweroff.
2028 */
2029
2030 static struct sysdev_class lapic_sysclass = {
2031 .name = "lapic",
2032 .resume = lapic_resume,
2033 .suspend = lapic_suspend,
2034 };
2035
2036 static struct sys_device device_lapic = {
2037 .id = 0,
2038 .cls = &lapic_sysclass,
2039 };
2040
apic_pm_activate(void)2041 static void __cpuinit apic_pm_activate(void)
2042 {
2043 apic_pm_state.active = 1;
2044 }
2045
init_lapic_sysfs(void)2046 static int __init init_lapic_sysfs(void)
2047 {
2048 int error;
2049
2050 if (!cpu_has_apic)
2051 return 0;
2052 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2053
2054 error = sysdev_class_register(&lapic_sysclass);
2055 if (!error)
2056 error = sysdev_register(&device_lapic);
2057 return error;
2058 }
2059 device_initcall(init_lapic_sysfs);
2060
2061 #else /* CONFIG_PM */
2062
apic_pm_activate(void)2063 static void apic_pm_activate(void) { }
2064
2065 #endif /* CONFIG_PM */
2066
2067 #ifdef CONFIG_X86_64
2068 /*
2069 * apic_is_clustered_box() -- Check if we can expect good TSC
2070 *
2071 * Thus far, the major user of this is IBM's Summit2 series:
2072 *
2073 * Clustered boxes may have unsynced TSC problems if they are
2074 * multi-chassis. Use available data to take a good guess.
2075 * If in doubt, go HPET.
2076 */
apic_is_clustered_box(void)2077 __cpuinit int apic_is_clustered_box(void)
2078 {
2079 int i, clusters, zeros;
2080 unsigned id;
2081 u16 *bios_cpu_apicid;
2082 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
2083
2084 /*
2085 * there is not this kind of box with AMD CPU yet.
2086 * Some AMD box with quadcore cpu and 8 sockets apicid
2087 * will be [4, 0x23] or [8, 0x27] could be thought to
2088 * vsmp box still need checking...
2089 */
2090 if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box())
2091 return 0;
2092
2093 bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
2094 bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
2095
2096 for (i = 0; i < nr_cpu_ids; i++) {
2097 /* are we being called early in kernel startup? */
2098 if (bios_cpu_apicid) {
2099 id = bios_cpu_apicid[i];
2100 } else if (i < nr_cpu_ids) {
2101 if (cpu_present(i))
2102 id = per_cpu(x86_bios_cpu_apicid, i);
2103 else
2104 continue;
2105 } else
2106 break;
2107
2108 if (id != BAD_APICID)
2109 __set_bit(APIC_CLUSTERID(id), clustermap);
2110 }
2111
2112 /* Problem: Partially populated chassis may not have CPUs in some of
2113 * the APIC clusters they have been allocated. Only present CPUs have
2114 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2115 * Since clusters are allocated sequentially, count zeros only if
2116 * they are bounded by ones.
2117 */
2118 clusters = 0;
2119 zeros = 0;
2120 for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
2121 if (test_bit(i, clustermap)) {
2122 clusters += 1 + zeros;
2123 zeros = 0;
2124 } else
2125 ++zeros;
2126 }
2127
2128 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2129 * not guaranteed to be synced between boards
2130 */
2131 if (is_vsmp_box() && clusters > 1)
2132 return 1;
2133
2134 /*
2135 * If clusters > 2, then should be multi-chassis.
2136 * May have to revisit this when multi-core + hyperthreaded CPUs come
2137 * out, but AFAIK this will work even for them.
2138 */
2139 return (clusters > 2);
2140 }
2141 #endif
2142
2143 /*
2144 * APIC command line parameters
2145 */
setup_disableapic(char * arg)2146 static int __init setup_disableapic(char *arg)
2147 {
2148 disable_apic = 1;
2149 setup_clear_cpu_cap(X86_FEATURE_APIC);
2150 return 0;
2151 }
2152 early_param("disableapic", setup_disableapic);
2153
2154 /* same as disableapic, for compatibility */
setup_nolapic(char * arg)2155 static int __init setup_nolapic(char *arg)
2156 {
2157 return setup_disableapic(arg);
2158 }
2159 early_param("nolapic", setup_nolapic);
2160
parse_lapic_timer_c2_ok(char * arg)2161 static int __init parse_lapic_timer_c2_ok(char *arg)
2162 {
2163 local_apic_timer_c2_ok = 1;
2164 return 0;
2165 }
2166 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
2167
parse_disable_apic_timer(char * arg)2168 static int __init parse_disable_apic_timer(char *arg)
2169 {
2170 disable_apic_timer = 1;
2171 return 0;
2172 }
2173 early_param("noapictimer", parse_disable_apic_timer);
2174
parse_nolapic_timer(char * arg)2175 static int __init parse_nolapic_timer(char *arg)
2176 {
2177 disable_apic_timer = 1;
2178 return 0;
2179 }
2180 early_param("nolapic_timer", parse_nolapic_timer);
2181
apic_set_verbosity(char * arg)2182 static int __init apic_set_verbosity(char *arg)
2183 {
2184 if (!arg) {
2185 #ifdef CONFIG_X86_64
2186 skip_ioapic_setup = 0;
2187 return 0;
2188 #endif
2189 return -EINVAL;
2190 }
2191
2192 if (strcmp("debug", arg) == 0)
2193 apic_verbosity = APIC_DEBUG;
2194 else if (strcmp("verbose", arg) == 0)
2195 apic_verbosity = APIC_VERBOSE;
2196 else {
2197 pr_warning("APIC Verbosity level %s not recognised"
2198 " use apic=verbose or apic=debug\n", arg);
2199 return -EINVAL;
2200 }
2201
2202 return 0;
2203 }
2204 early_param("apic", apic_set_verbosity);
2205
lapic_insert_resource(void)2206 static int __init lapic_insert_resource(void)
2207 {
2208 if (!apic_phys)
2209 return -1;
2210
2211 /* Put local APIC into the resource map. */
2212 lapic_resource.start = apic_phys;
2213 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
2214 insert_resource(&iomem_resource, &lapic_resource);
2215
2216 return 0;
2217 }
2218
2219 /*
2220 * need call insert after e820_reserve_resources()
2221 * that is using request_resource
2222 */
2223 late_initcall(lapic_insert_resource);
2224