1 /*
2 * PowerPC64 port by Mike Corrigan and Dave Engebretsen
3 * {mikejc|engebret}@us.ibm.com
4 *
5 * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
6 *
7 * SMP scalability work:
8 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
9 *
10 * Module name: htab.c
11 *
12 * Description:
13 * PowerPC Hashed Page Table functions
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
19 */
20
21 #undef DEBUG
22 #undef DEBUG_LOW
23
24 #include <linux/spinlock.h>
25 #include <linux/errno.h>
26 #include <linux/sched.h>
27 #include <linux/proc_fs.h>
28 #include <linux/stat.h>
29 #include <linux/sysctl.h>
30 #include <linux/ctype.h>
31 #include <linux/cache.h>
32 #include <linux/init.h>
33 #include <linux/signal.h>
34 #include <linux/lmb.h>
35
36 #include <asm/processor.h>
37 #include <asm/pgtable.h>
38 #include <asm/mmu.h>
39 #include <asm/mmu_context.h>
40 #include <asm/page.h>
41 #include <asm/types.h>
42 #include <asm/system.h>
43 #include <asm/uaccess.h>
44 #include <asm/machdep.h>
45 #include <asm/prom.h>
46 #include <asm/abs_addr.h>
47 #include <asm/tlbflush.h>
48 #include <asm/io.h>
49 #include <asm/eeh.h>
50 #include <asm/tlb.h>
51 #include <asm/cacheflush.h>
52 #include <asm/cputable.h>
53 #include <asm/sections.h>
54 #include <asm/spu.h>
55 #include <asm/udbg.h>
56
57 #ifdef DEBUG
58 #define DBG(fmt...) udbg_printf(fmt)
59 #else
60 #define DBG(fmt...)
61 #endif
62
63 #ifdef DEBUG_LOW
64 #define DBG_LOW(fmt...) udbg_printf(fmt)
65 #else
66 #define DBG_LOW(fmt...)
67 #endif
68
69 #define KB (1024)
70 #define MB (1024*KB)
71 #define GB (1024L*MB)
72
73 /*
74 * Note: pte --> Linux PTE
75 * HPTE --> PowerPC Hashed Page Table Entry
76 *
77 * Execution context:
78 * htab_initialize is called with the MMU off (of course), but
79 * the kernel has been copied down to zero so it can directly
80 * reference global data. At this point it is very difficult
81 * to print debug info.
82 *
83 */
84
85 #ifdef CONFIG_U3_DART
86 extern unsigned long dart_tablebase;
87 #endif /* CONFIG_U3_DART */
88
89 static unsigned long _SDR1;
90 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
91
92 struct hash_pte *htab_address;
93 unsigned long htab_size_bytes;
94 unsigned long htab_hash_mask;
95 int mmu_linear_psize = MMU_PAGE_4K;
96 int mmu_virtual_psize = MMU_PAGE_4K;
97 int mmu_vmalloc_psize = MMU_PAGE_4K;
98 #ifdef CONFIG_SPARSEMEM_VMEMMAP
99 int mmu_vmemmap_psize = MMU_PAGE_4K;
100 #endif
101 int mmu_io_psize = MMU_PAGE_4K;
102 int mmu_kernel_ssize = MMU_SEGSIZE_256M;
103 int mmu_highuser_ssize = MMU_SEGSIZE_256M;
104 u16 mmu_slb_size = 64;
105 #ifdef CONFIG_HUGETLB_PAGE
106 unsigned int HPAGE_SHIFT;
107 #endif
108 #ifdef CONFIG_PPC_64K_PAGES
109 int mmu_ci_restrictions;
110 #endif
111 #ifdef CONFIG_DEBUG_PAGEALLOC
112 static u8 *linear_map_hash_slots;
113 static unsigned long linear_map_hash_count;
114 static DEFINE_SPINLOCK(linear_map_hash_lock);
115 #endif /* CONFIG_DEBUG_PAGEALLOC */
116
117 /* There are definitions of page sizes arrays to be used when none
118 * is provided by the firmware.
119 */
120
121 /* Pre-POWER4 CPUs (4k pages only)
122 */
123 static struct mmu_psize_def mmu_psize_defaults_old[] = {
124 [MMU_PAGE_4K] = {
125 .shift = 12,
126 .sllp = 0,
127 .penc = 0,
128 .avpnm = 0,
129 .tlbiel = 0,
130 },
131 };
132
133 /* POWER4, GPUL, POWER5
134 *
135 * Support for 16Mb large pages
136 */
137 static struct mmu_psize_def mmu_psize_defaults_gp[] = {
138 [MMU_PAGE_4K] = {
139 .shift = 12,
140 .sllp = 0,
141 .penc = 0,
142 .avpnm = 0,
143 .tlbiel = 1,
144 },
145 [MMU_PAGE_16M] = {
146 .shift = 24,
147 .sllp = SLB_VSID_L,
148 .penc = 0,
149 .avpnm = 0x1UL,
150 .tlbiel = 0,
151 },
152 };
153
htab_convert_pte_flags(unsigned long pteflags)154 static unsigned long htab_convert_pte_flags(unsigned long pteflags)
155 {
156 unsigned long rflags = pteflags & 0x1fa;
157
158 /* _PAGE_EXEC -> NOEXEC */
159 if ((pteflags & _PAGE_EXEC) == 0)
160 rflags |= HPTE_R_N;
161
162 /* PP bits. PAGE_USER is already PP bit 0x2, so we only
163 * need to add in 0x1 if it's a read-only user page
164 */
165 if ((pteflags & _PAGE_USER) && !((pteflags & _PAGE_RW) &&
166 (pteflags & _PAGE_DIRTY)))
167 rflags |= 1;
168
169 /* Always add C */
170 return rflags | HPTE_R_C;
171 }
172
htab_bolt_mapping(unsigned long vstart,unsigned long vend,unsigned long pstart,unsigned long prot,int psize,int ssize)173 int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
174 unsigned long pstart, unsigned long prot,
175 int psize, int ssize)
176 {
177 unsigned long vaddr, paddr;
178 unsigned int step, shift;
179 int ret = 0;
180
181 shift = mmu_psize_defs[psize].shift;
182 step = 1 << shift;
183
184 prot = htab_convert_pte_flags(prot);
185
186 DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n",
187 vstart, vend, pstart, prot, psize, ssize);
188
189 for (vaddr = vstart, paddr = pstart; vaddr < vend;
190 vaddr += step, paddr += step) {
191 unsigned long hash, hpteg;
192 unsigned long vsid = get_kernel_vsid(vaddr, ssize);
193 unsigned long va = hpt_va(vaddr, vsid, ssize);
194 unsigned long tprot = prot;
195
196 /* Make kernel text executable */
197 if (overlaps_kernel_text(vaddr, vaddr + step))
198 tprot &= ~HPTE_R_N;
199
200 hash = hpt_hash(va, shift, ssize);
201 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
202
203 BUG_ON(!ppc_md.hpte_insert);
204 ret = ppc_md.hpte_insert(hpteg, va, paddr, tprot,
205 HPTE_V_BOLTED, psize, ssize);
206
207 if (ret < 0)
208 break;
209 #ifdef CONFIG_DEBUG_PAGEALLOC
210 if ((paddr >> PAGE_SHIFT) < linear_map_hash_count)
211 linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80;
212 #endif /* CONFIG_DEBUG_PAGEALLOC */
213 }
214 return ret < 0 ? ret : 0;
215 }
216
217 #ifdef CONFIG_MEMORY_HOTPLUG
htab_remove_mapping(unsigned long vstart,unsigned long vend,int psize,int ssize)218 static int htab_remove_mapping(unsigned long vstart, unsigned long vend,
219 int psize, int ssize)
220 {
221 unsigned long vaddr;
222 unsigned int step, shift;
223
224 shift = mmu_psize_defs[psize].shift;
225 step = 1 << shift;
226
227 if (!ppc_md.hpte_removebolted) {
228 printk(KERN_WARNING "Platform doesn't implement "
229 "hpte_removebolted\n");
230 return -EINVAL;
231 }
232
233 for (vaddr = vstart; vaddr < vend; vaddr += step)
234 ppc_md.hpte_removebolted(vaddr, psize, ssize);
235
236 return 0;
237 }
238 #endif /* CONFIG_MEMORY_HOTPLUG */
239
htab_dt_scan_seg_sizes(unsigned long node,const char * uname,int depth,void * data)240 static int __init htab_dt_scan_seg_sizes(unsigned long node,
241 const char *uname, int depth,
242 void *data)
243 {
244 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
245 u32 *prop;
246 unsigned long size = 0;
247
248 /* We are scanning "cpu" nodes only */
249 if (type == NULL || strcmp(type, "cpu") != 0)
250 return 0;
251
252 prop = (u32 *)of_get_flat_dt_prop(node, "ibm,processor-segment-sizes",
253 &size);
254 if (prop == NULL)
255 return 0;
256 for (; size >= 4; size -= 4, ++prop) {
257 if (prop[0] == 40) {
258 DBG("1T segment support detected\n");
259 cur_cpu_spec->cpu_features |= CPU_FTR_1T_SEGMENT;
260 return 1;
261 }
262 }
263 cur_cpu_spec->cpu_features &= ~CPU_FTR_NO_SLBIE_B;
264 return 0;
265 }
266
htab_init_seg_sizes(void)267 static void __init htab_init_seg_sizes(void)
268 {
269 of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL);
270 }
271
htab_dt_scan_page_sizes(unsigned long node,const char * uname,int depth,void * data)272 static int __init htab_dt_scan_page_sizes(unsigned long node,
273 const char *uname, int depth,
274 void *data)
275 {
276 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
277 u32 *prop;
278 unsigned long size = 0;
279
280 /* We are scanning "cpu" nodes only */
281 if (type == NULL || strcmp(type, "cpu") != 0)
282 return 0;
283
284 prop = (u32 *)of_get_flat_dt_prop(node,
285 "ibm,segment-page-sizes", &size);
286 if (prop != NULL) {
287 DBG("Page sizes from device-tree:\n");
288 size /= 4;
289 cur_cpu_spec->cpu_features &= ~(CPU_FTR_16M_PAGE);
290 while(size > 0) {
291 unsigned int shift = prop[0];
292 unsigned int slbenc = prop[1];
293 unsigned int lpnum = prop[2];
294 unsigned int lpenc = 0;
295 struct mmu_psize_def *def;
296 int idx = -1;
297
298 size -= 3; prop += 3;
299 while(size > 0 && lpnum) {
300 if (prop[0] == shift)
301 lpenc = prop[1];
302 prop += 2; size -= 2;
303 lpnum--;
304 }
305 switch(shift) {
306 case 0xc:
307 idx = MMU_PAGE_4K;
308 break;
309 case 0x10:
310 idx = MMU_PAGE_64K;
311 break;
312 case 0x14:
313 idx = MMU_PAGE_1M;
314 break;
315 case 0x18:
316 idx = MMU_PAGE_16M;
317 cur_cpu_spec->cpu_features |= CPU_FTR_16M_PAGE;
318 break;
319 case 0x22:
320 idx = MMU_PAGE_16G;
321 break;
322 }
323 if (idx < 0)
324 continue;
325 def = &mmu_psize_defs[idx];
326 def->shift = shift;
327 if (shift <= 23)
328 def->avpnm = 0;
329 else
330 def->avpnm = (1 << (shift - 23)) - 1;
331 def->sllp = slbenc;
332 def->penc = lpenc;
333 /* We don't know for sure what's up with tlbiel, so
334 * for now we only set it for 4K and 64K pages
335 */
336 if (idx == MMU_PAGE_4K || idx == MMU_PAGE_64K)
337 def->tlbiel = 1;
338 else
339 def->tlbiel = 0;
340
341 DBG(" %d: shift=%02x, sllp=%04x, avpnm=%08x, "
342 "tlbiel=%d, penc=%d\n",
343 idx, shift, def->sllp, def->avpnm, def->tlbiel,
344 def->penc);
345 }
346 return 1;
347 }
348 return 0;
349 }
350
351 #ifdef CONFIG_HUGETLB_PAGE
352 /* Scan for 16G memory blocks that have been set aside for huge pages
353 * and reserve those blocks for 16G huge pages.
354 */
htab_dt_scan_hugepage_blocks(unsigned long node,const char * uname,int depth,void * data)355 static int __init htab_dt_scan_hugepage_blocks(unsigned long node,
356 const char *uname, int depth,
357 void *data) {
358 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
359 unsigned long *addr_prop;
360 u32 *page_count_prop;
361 unsigned int expected_pages;
362 long unsigned int phys_addr;
363 long unsigned int block_size;
364
365 /* We are scanning "memory" nodes only */
366 if (type == NULL || strcmp(type, "memory") != 0)
367 return 0;
368
369 /* This property is the log base 2 of the number of virtual pages that
370 * will represent this memory block. */
371 page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL);
372 if (page_count_prop == NULL)
373 return 0;
374 expected_pages = (1 << page_count_prop[0]);
375 addr_prop = of_get_flat_dt_prop(node, "reg", NULL);
376 if (addr_prop == NULL)
377 return 0;
378 phys_addr = addr_prop[0];
379 block_size = addr_prop[1];
380 if (block_size != (16 * GB))
381 return 0;
382 printk(KERN_INFO "Huge page(16GB) memory: "
383 "addr = 0x%lX size = 0x%lX pages = %d\n",
384 phys_addr, block_size, expected_pages);
385 if (phys_addr + (16 * GB) <= lmb_end_of_DRAM()) {
386 lmb_reserve(phys_addr, block_size * expected_pages);
387 add_gpage(phys_addr, block_size, expected_pages);
388 }
389 return 0;
390 }
391 #endif /* CONFIG_HUGETLB_PAGE */
392
htab_init_page_sizes(void)393 static void __init htab_init_page_sizes(void)
394 {
395 int rc;
396
397 /* Default to 4K pages only */
398 memcpy(mmu_psize_defs, mmu_psize_defaults_old,
399 sizeof(mmu_psize_defaults_old));
400
401 /*
402 * Try to find the available page sizes in the device-tree
403 */
404 rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL);
405 if (rc != 0) /* Found */
406 goto found;
407
408 /*
409 * Not in the device-tree, let's fallback on known size
410 * list for 16M capable GP & GR
411 */
412 if (cpu_has_feature(CPU_FTR_16M_PAGE))
413 memcpy(mmu_psize_defs, mmu_psize_defaults_gp,
414 sizeof(mmu_psize_defaults_gp));
415 found:
416 #ifndef CONFIG_DEBUG_PAGEALLOC
417 /*
418 * Pick a size for the linear mapping. Currently, we only support
419 * 16M, 1M and 4K which is the default
420 */
421 if (mmu_psize_defs[MMU_PAGE_16M].shift)
422 mmu_linear_psize = MMU_PAGE_16M;
423 else if (mmu_psize_defs[MMU_PAGE_1M].shift)
424 mmu_linear_psize = MMU_PAGE_1M;
425 #endif /* CONFIG_DEBUG_PAGEALLOC */
426
427 #ifdef CONFIG_PPC_64K_PAGES
428 /*
429 * Pick a size for the ordinary pages. Default is 4K, we support
430 * 64K for user mappings and vmalloc if supported by the processor.
431 * We only use 64k for ioremap if the processor
432 * (and firmware) support cache-inhibited large pages.
433 * If not, we use 4k and set mmu_ci_restrictions so that
434 * hash_page knows to switch processes that use cache-inhibited
435 * mappings to 4k pages.
436 */
437 if (mmu_psize_defs[MMU_PAGE_64K].shift) {
438 mmu_virtual_psize = MMU_PAGE_64K;
439 mmu_vmalloc_psize = MMU_PAGE_64K;
440 if (mmu_linear_psize == MMU_PAGE_4K)
441 mmu_linear_psize = MMU_PAGE_64K;
442 if (cpu_has_feature(CPU_FTR_CI_LARGE_PAGE)) {
443 /*
444 * Don't use 64k pages for ioremap on pSeries, since
445 * that would stop us accessing the HEA ethernet.
446 */
447 if (!machine_is(pseries))
448 mmu_io_psize = MMU_PAGE_64K;
449 } else
450 mmu_ci_restrictions = 1;
451 }
452 #endif /* CONFIG_PPC_64K_PAGES */
453
454 #ifdef CONFIG_SPARSEMEM_VMEMMAP
455 /* We try to use 16M pages for vmemmap if that is supported
456 * and we have at least 1G of RAM at boot
457 */
458 if (mmu_psize_defs[MMU_PAGE_16M].shift &&
459 lmb_phys_mem_size() >= 0x40000000)
460 mmu_vmemmap_psize = MMU_PAGE_16M;
461 else if (mmu_psize_defs[MMU_PAGE_64K].shift)
462 mmu_vmemmap_psize = MMU_PAGE_64K;
463 else
464 mmu_vmemmap_psize = MMU_PAGE_4K;
465 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
466
467 printk(KERN_DEBUG "Page orders: linear mapping = %d, "
468 "virtual = %d, io = %d"
469 #ifdef CONFIG_SPARSEMEM_VMEMMAP
470 ", vmemmap = %d"
471 #endif
472 "\n",
473 mmu_psize_defs[mmu_linear_psize].shift,
474 mmu_psize_defs[mmu_virtual_psize].shift,
475 mmu_psize_defs[mmu_io_psize].shift
476 #ifdef CONFIG_SPARSEMEM_VMEMMAP
477 ,mmu_psize_defs[mmu_vmemmap_psize].shift
478 #endif
479 );
480
481 #ifdef CONFIG_HUGETLB_PAGE
482 /* Reserve 16G huge page memory sections for huge pages */
483 of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL);
484
485 /* Set default large page size. Currently, we pick 16M or 1M depending
486 * on what is available
487 */
488 if (mmu_psize_defs[MMU_PAGE_16M].shift)
489 HPAGE_SHIFT = mmu_psize_defs[MMU_PAGE_16M].shift;
490 /* With 4k/4level pagetables, we can't (for now) cope with a
491 * huge page size < PMD_SIZE */
492 else if (mmu_psize_defs[MMU_PAGE_1M].shift)
493 HPAGE_SHIFT = mmu_psize_defs[MMU_PAGE_1M].shift;
494 #endif /* CONFIG_HUGETLB_PAGE */
495 }
496
htab_dt_scan_pftsize(unsigned long node,const char * uname,int depth,void * data)497 static int __init htab_dt_scan_pftsize(unsigned long node,
498 const char *uname, int depth,
499 void *data)
500 {
501 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
502 u32 *prop;
503
504 /* We are scanning "cpu" nodes only */
505 if (type == NULL || strcmp(type, "cpu") != 0)
506 return 0;
507
508 prop = (u32 *)of_get_flat_dt_prop(node, "ibm,pft-size", NULL);
509 if (prop != NULL) {
510 /* pft_size[0] is the NUMA CEC cookie */
511 ppc64_pft_size = prop[1];
512 return 1;
513 }
514 return 0;
515 }
516
htab_get_table_size(void)517 static unsigned long __init htab_get_table_size(void)
518 {
519 unsigned long mem_size, rnd_mem_size, pteg_count;
520
521 /* If hash size isn't already provided by the platform, we try to
522 * retrieve it from the device-tree. If it's not there neither, we
523 * calculate it now based on the total RAM size
524 */
525 if (ppc64_pft_size == 0)
526 of_scan_flat_dt(htab_dt_scan_pftsize, NULL);
527 if (ppc64_pft_size)
528 return 1UL << ppc64_pft_size;
529
530 /* round mem_size up to next power of 2 */
531 mem_size = lmb_phys_mem_size();
532 rnd_mem_size = 1UL << __ilog2(mem_size);
533 if (rnd_mem_size < mem_size)
534 rnd_mem_size <<= 1;
535
536 /* # pages / 2 */
537 pteg_count = max(rnd_mem_size >> (12 + 1), 1UL << 11);
538
539 return pteg_count << 7;
540 }
541
542 #ifdef CONFIG_MEMORY_HOTPLUG
create_section_mapping(unsigned long start,unsigned long end)543 void create_section_mapping(unsigned long start, unsigned long end)
544 {
545 BUG_ON(htab_bolt_mapping(start, end, __pa(start),
546 pgprot_val(PAGE_KERNEL), mmu_linear_psize,
547 mmu_kernel_ssize));
548 }
549
remove_section_mapping(unsigned long start,unsigned long end)550 int remove_section_mapping(unsigned long start, unsigned long end)
551 {
552 return htab_remove_mapping(start, end, mmu_linear_psize,
553 mmu_kernel_ssize);
554 }
555 #endif /* CONFIG_MEMORY_HOTPLUG */
556
make_bl(unsigned int * insn_addr,void * func)557 static inline void make_bl(unsigned int *insn_addr, void *func)
558 {
559 unsigned long funcp = *((unsigned long *)func);
560 int offset = funcp - (unsigned long)insn_addr;
561
562 *insn_addr = (unsigned int)(0x48000001 | (offset & 0x03fffffc));
563 flush_icache_range((unsigned long)insn_addr, 4+
564 (unsigned long)insn_addr);
565 }
566
htab_finish_init(void)567 static void __init htab_finish_init(void)
568 {
569 extern unsigned int *htab_call_hpte_insert1;
570 extern unsigned int *htab_call_hpte_insert2;
571 extern unsigned int *htab_call_hpte_remove;
572 extern unsigned int *htab_call_hpte_updatepp;
573
574 #ifdef CONFIG_PPC_HAS_HASH_64K
575 extern unsigned int *ht64_call_hpte_insert1;
576 extern unsigned int *ht64_call_hpte_insert2;
577 extern unsigned int *ht64_call_hpte_remove;
578 extern unsigned int *ht64_call_hpte_updatepp;
579
580 make_bl(ht64_call_hpte_insert1, ppc_md.hpte_insert);
581 make_bl(ht64_call_hpte_insert2, ppc_md.hpte_insert);
582 make_bl(ht64_call_hpte_remove, ppc_md.hpte_remove);
583 make_bl(ht64_call_hpte_updatepp, ppc_md.hpte_updatepp);
584 #endif /* CONFIG_PPC_HAS_HASH_64K */
585
586 make_bl(htab_call_hpte_insert1, ppc_md.hpte_insert);
587 make_bl(htab_call_hpte_insert2, ppc_md.hpte_insert);
588 make_bl(htab_call_hpte_remove, ppc_md.hpte_remove);
589 make_bl(htab_call_hpte_updatepp, ppc_md.hpte_updatepp);
590 }
591
htab_initialize(void)592 void __init htab_initialize(void)
593 {
594 unsigned long table;
595 unsigned long pteg_count;
596 unsigned long prot;
597 unsigned long base = 0, size = 0, limit;
598 int i;
599
600 DBG(" -> htab_initialize()\n");
601
602 /* Initialize segment sizes */
603 htab_init_seg_sizes();
604
605 /* Initialize page sizes */
606 htab_init_page_sizes();
607
608 if (cpu_has_feature(CPU_FTR_1T_SEGMENT)) {
609 mmu_kernel_ssize = MMU_SEGSIZE_1T;
610 mmu_highuser_ssize = MMU_SEGSIZE_1T;
611 printk(KERN_INFO "Using 1TB segments\n");
612 }
613
614 /*
615 * Calculate the required size of the htab. We want the number of
616 * PTEGs to equal one half the number of real pages.
617 */
618 htab_size_bytes = htab_get_table_size();
619 pteg_count = htab_size_bytes >> 7;
620
621 htab_hash_mask = pteg_count - 1;
622
623 if (firmware_has_feature(FW_FEATURE_LPAR)) {
624 /* Using a hypervisor which owns the htab */
625 htab_address = NULL;
626 _SDR1 = 0;
627 } else {
628 /* Find storage for the HPT. Must be contiguous in
629 * the absolute address space. On cell we want it to be
630 * in the first 2 Gig so we can use it for IOMMU hacks.
631 */
632 if (machine_is(cell))
633 limit = 0x80000000;
634 else
635 limit = 0;
636
637 table = lmb_alloc_base(htab_size_bytes, htab_size_bytes, limit);
638
639 DBG("Hash table allocated at %lx, size: %lx\n", table,
640 htab_size_bytes);
641
642 htab_address = abs_to_virt(table);
643
644 /* htab absolute addr + encoded htabsize */
645 _SDR1 = table + __ilog2(pteg_count) - 11;
646
647 /* Initialize the HPT with no entries */
648 memset((void *)table, 0, htab_size_bytes);
649
650 /* Set SDR1 */
651 mtspr(SPRN_SDR1, _SDR1);
652 }
653
654 prot = pgprot_val(PAGE_KERNEL);
655
656 #ifdef CONFIG_DEBUG_PAGEALLOC
657 linear_map_hash_count = lmb_end_of_DRAM() >> PAGE_SHIFT;
658 linear_map_hash_slots = __va(lmb_alloc_base(linear_map_hash_count,
659 1, lmb.rmo_size));
660 memset(linear_map_hash_slots, 0, linear_map_hash_count);
661 #endif /* CONFIG_DEBUG_PAGEALLOC */
662
663 /* On U3 based machines, we need to reserve the DART area and
664 * _NOT_ map it to avoid cache paradoxes as it's remapped non
665 * cacheable later on
666 */
667
668 /* create bolted the linear mapping in the hash table */
669 for (i=0; i < lmb.memory.cnt; i++) {
670 base = (unsigned long)__va(lmb.memory.region[i].base);
671 size = lmb.memory.region[i].size;
672
673 DBG("creating mapping for region: %lx..%lx (prot: %x)\n",
674 base, size, prot);
675
676 #ifdef CONFIG_U3_DART
677 /* Do not map the DART space. Fortunately, it will be aligned
678 * in such a way that it will not cross two lmb regions and
679 * will fit within a single 16Mb page.
680 * The DART space is assumed to be a full 16Mb region even if
681 * we only use 2Mb of that space. We will use more of it later
682 * for AGP GART. We have to use a full 16Mb large page.
683 */
684 DBG("DART base: %lx\n", dart_tablebase);
685
686 if (dart_tablebase != 0 && dart_tablebase >= base
687 && dart_tablebase < (base + size)) {
688 unsigned long dart_table_end = dart_tablebase + 16 * MB;
689 if (base != dart_tablebase)
690 BUG_ON(htab_bolt_mapping(base, dart_tablebase,
691 __pa(base), prot,
692 mmu_linear_psize,
693 mmu_kernel_ssize));
694 if ((base + size) > dart_table_end)
695 BUG_ON(htab_bolt_mapping(dart_tablebase+16*MB,
696 base + size,
697 __pa(dart_table_end),
698 prot,
699 mmu_linear_psize,
700 mmu_kernel_ssize));
701 continue;
702 }
703 #endif /* CONFIG_U3_DART */
704 BUG_ON(htab_bolt_mapping(base, base + size, __pa(base),
705 prot, mmu_linear_psize, mmu_kernel_ssize));
706 }
707
708 /*
709 * If we have a memory_limit and we've allocated TCEs then we need to
710 * explicitly map the TCE area at the top of RAM. We also cope with the
711 * case that the TCEs start below memory_limit.
712 * tce_alloc_start/end are 16MB aligned so the mapping should work
713 * for either 4K or 16MB pages.
714 */
715 if (tce_alloc_start) {
716 tce_alloc_start = (unsigned long)__va(tce_alloc_start);
717 tce_alloc_end = (unsigned long)__va(tce_alloc_end);
718
719 if (base + size >= tce_alloc_start)
720 tce_alloc_start = base + size + 1;
721
722 BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end,
723 __pa(tce_alloc_start), prot,
724 mmu_linear_psize, mmu_kernel_ssize));
725 }
726
727 htab_finish_init();
728
729 DBG(" <- htab_initialize()\n");
730 }
731 #undef KB
732 #undef MB
733
htab_initialize_secondary(void)734 void htab_initialize_secondary(void)
735 {
736 if (!firmware_has_feature(FW_FEATURE_LPAR))
737 mtspr(SPRN_SDR1, _SDR1);
738 }
739
740 /*
741 * Called by asm hashtable.S for doing lazy icache flush
742 */
hash_page_do_lazy_icache(unsigned int pp,pte_t pte,int trap)743 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
744 {
745 struct page *page;
746
747 if (!pfn_valid(pte_pfn(pte)))
748 return pp;
749
750 page = pte_page(pte);
751
752 /* page is dirty */
753 if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) {
754 if (trap == 0x400) {
755 __flush_dcache_icache(page_address(page));
756 set_bit(PG_arch_1, &page->flags);
757 } else
758 pp |= HPTE_R_N;
759 }
760 return pp;
761 }
762
763 #ifdef CONFIG_PPC_MM_SLICES
get_paca_psize(unsigned long addr)764 unsigned int get_paca_psize(unsigned long addr)
765 {
766 unsigned long index, slices;
767
768 if (addr < SLICE_LOW_TOP) {
769 slices = get_paca()->context.low_slices_psize;
770 index = GET_LOW_SLICE_INDEX(addr);
771 } else {
772 slices = get_paca()->context.high_slices_psize;
773 index = GET_HIGH_SLICE_INDEX(addr);
774 }
775 return (slices >> (index * 4)) & 0xF;
776 }
777
778 #else
get_paca_psize(unsigned long addr)779 unsigned int get_paca_psize(unsigned long addr)
780 {
781 return get_paca()->context.user_psize;
782 }
783 #endif
784
785 /*
786 * Demote a segment to using 4k pages.
787 * For now this makes the whole process use 4k pages.
788 */
789 #ifdef CONFIG_PPC_64K_PAGES
demote_segment_4k(struct mm_struct * mm,unsigned long addr)790 void demote_segment_4k(struct mm_struct *mm, unsigned long addr)
791 {
792 if (get_slice_psize(mm, addr) == MMU_PAGE_4K)
793 return;
794 slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K);
795 #ifdef CONFIG_SPU_BASE
796 spu_flush_all_slbs(mm);
797 #endif
798 if (get_paca_psize(addr) != MMU_PAGE_4K) {
799 get_paca()->context = mm->context;
800 slb_flush_and_rebolt();
801 }
802 }
803 #endif /* CONFIG_PPC_64K_PAGES */
804
805 #ifdef CONFIG_PPC_SUBPAGE_PROT
806 /*
807 * This looks up a 2-bit protection code for a 4k subpage of a 64k page.
808 * Userspace sets the subpage permissions using the subpage_prot system call.
809 *
810 * Result is 0: full permissions, _PAGE_RW: read-only,
811 * _PAGE_USER or _PAGE_USER|_PAGE_RW: no access.
812 */
subpage_protection(pgd_t * pgdir,unsigned long ea)813 static int subpage_protection(pgd_t *pgdir, unsigned long ea)
814 {
815 struct subpage_prot_table *spt = pgd_subpage_prot(pgdir);
816 u32 spp = 0;
817 u32 **sbpm, *sbpp;
818
819 if (ea >= spt->maxaddr)
820 return 0;
821 if (ea < 0x100000000) {
822 /* addresses below 4GB use spt->low_prot */
823 sbpm = spt->low_prot;
824 } else {
825 sbpm = spt->protptrs[ea >> SBP_L3_SHIFT];
826 if (!sbpm)
827 return 0;
828 }
829 sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)];
830 if (!sbpp)
831 return 0;
832 spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)];
833
834 /* extract 2-bit bitfield for this 4k subpage */
835 spp >>= 30 - 2 * ((ea >> 12) & 0xf);
836
837 /* turn 0,1,2,3 into combination of _PAGE_USER and _PAGE_RW */
838 spp = ((spp & 2) ? _PAGE_USER : 0) | ((spp & 1) ? _PAGE_RW : 0);
839 return spp;
840 }
841
842 #else /* CONFIG_PPC_SUBPAGE_PROT */
subpage_protection(pgd_t * pgdir,unsigned long ea)843 static inline int subpage_protection(pgd_t *pgdir, unsigned long ea)
844 {
845 return 0;
846 }
847 #endif
848
849 /* Result code is:
850 * 0 - handled
851 * 1 - normal page fault
852 * -1 - critical hash insertion error
853 * -2 - access not permitted by subpage protection mechanism
854 */
hash_page(unsigned long ea,unsigned long access,unsigned long trap)855 int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
856 {
857 void *pgdir;
858 unsigned long vsid;
859 struct mm_struct *mm;
860 pte_t *ptep;
861 cpumask_t tmp;
862 int rc, user_region = 0, local = 0;
863 int psize, ssize;
864
865 DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
866 ea, access, trap);
867
868 if ((ea & ~REGION_MASK) >= PGTABLE_RANGE) {
869 DBG_LOW(" out of pgtable range !\n");
870 return 1;
871 }
872
873 /* Get region & vsid */
874 switch (REGION_ID(ea)) {
875 case USER_REGION_ID:
876 user_region = 1;
877 mm = current->mm;
878 if (! mm) {
879 DBG_LOW(" user region with no mm !\n");
880 return 1;
881 }
882 psize = get_slice_psize(mm, ea);
883 ssize = user_segment_size(ea);
884 vsid = get_vsid(mm->context.id, ea, ssize);
885 break;
886 case VMALLOC_REGION_ID:
887 mm = &init_mm;
888 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
889 if (ea < VMALLOC_END)
890 psize = mmu_vmalloc_psize;
891 else
892 psize = mmu_io_psize;
893 ssize = mmu_kernel_ssize;
894 break;
895 default:
896 /* Not a valid range
897 * Send the problem up to do_page_fault
898 */
899 return 1;
900 }
901 DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid);
902
903 /* Get pgdir */
904 pgdir = mm->pgd;
905 if (pgdir == NULL)
906 return 1;
907
908 /* Check CPU locality */
909 tmp = cpumask_of_cpu(smp_processor_id());
910 if (user_region && cpus_equal(mm->cpu_vm_mask, tmp))
911 local = 1;
912
913 #ifdef CONFIG_HUGETLB_PAGE
914 /* Handle hugepage regions */
915 if (HPAGE_SHIFT && mmu_huge_psizes[psize]) {
916 DBG_LOW(" -> huge page !\n");
917 return hash_huge_page(mm, access, ea, vsid, local, trap);
918 }
919 #endif /* CONFIG_HUGETLB_PAGE */
920
921 #ifndef CONFIG_PPC_64K_PAGES
922 /* If we use 4K pages and our psize is not 4K, then we are hitting
923 * a special driver mapping, we need to align the address before
924 * we fetch the PTE
925 */
926 if (psize != MMU_PAGE_4K)
927 ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
928 #endif /* CONFIG_PPC_64K_PAGES */
929
930 /* Get PTE and page size from page tables */
931 ptep = find_linux_pte(pgdir, ea);
932 if (ptep == NULL || !pte_present(*ptep)) {
933 DBG_LOW(" no PTE !\n");
934 return 1;
935 }
936
937 #ifndef CONFIG_PPC_64K_PAGES
938 DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep));
939 #else
940 DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep),
941 pte_val(*(ptep + PTRS_PER_PTE)));
942 #endif
943 /* Pre-check access permissions (will be re-checked atomically
944 * in __hash_page_XX but this pre-check is a fast path
945 */
946 if (access & ~pte_val(*ptep)) {
947 DBG_LOW(" no access !\n");
948 return 1;
949 }
950
951 /* Do actual hashing */
952 #ifdef CONFIG_PPC_64K_PAGES
953 /* If _PAGE_4K_PFN is set, make sure this is a 4k segment */
954 if ((pte_val(*ptep) & _PAGE_4K_PFN) && psize == MMU_PAGE_64K) {
955 demote_segment_4k(mm, ea);
956 psize = MMU_PAGE_4K;
957 }
958
959 /* If this PTE is non-cacheable and we have restrictions on
960 * using non cacheable large pages, then we switch to 4k
961 */
962 if (mmu_ci_restrictions && psize == MMU_PAGE_64K &&
963 (pte_val(*ptep) & _PAGE_NO_CACHE)) {
964 if (user_region) {
965 demote_segment_4k(mm, ea);
966 psize = MMU_PAGE_4K;
967 } else if (ea < VMALLOC_END) {
968 /*
969 * some driver did a non-cacheable mapping
970 * in vmalloc space, so switch vmalloc
971 * to 4k pages
972 */
973 printk(KERN_ALERT "Reducing vmalloc segment "
974 "to 4kB pages because of "
975 "non-cacheable mapping\n");
976 psize = mmu_vmalloc_psize = MMU_PAGE_4K;
977 #ifdef CONFIG_SPU_BASE
978 spu_flush_all_slbs(mm);
979 #endif
980 }
981 }
982 if (user_region) {
983 if (psize != get_paca_psize(ea)) {
984 get_paca()->context = mm->context;
985 slb_flush_and_rebolt();
986 }
987 } else if (get_paca()->vmalloc_sllp !=
988 mmu_psize_defs[mmu_vmalloc_psize].sllp) {
989 get_paca()->vmalloc_sllp =
990 mmu_psize_defs[mmu_vmalloc_psize].sllp;
991 slb_vmalloc_update();
992 }
993 #endif /* CONFIG_PPC_64K_PAGES */
994
995 #ifdef CONFIG_PPC_HAS_HASH_64K
996 if (psize == MMU_PAGE_64K)
997 rc = __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize);
998 else
999 #endif /* CONFIG_PPC_HAS_HASH_64K */
1000 {
1001 int spp = subpage_protection(pgdir, ea);
1002 if (access & spp)
1003 rc = -2;
1004 else
1005 rc = __hash_page_4K(ea, access, vsid, ptep, trap,
1006 local, ssize, spp);
1007 }
1008
1009 #ifndef CONFIG_PPC_64K_PAGES
1010 DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep));
1011 #else
1012 DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep),
1013 pte_val(*(ptep + PTRS_PER_PTE)));
1014 #endif
1015 DBG_LOW(" -> rc=%d\n", rc);
1016 return rc;
1017 }
1018 EXPORT_SYMBOL_GPL(hash_page);
1019
hash_preload(struct mm_struct * mm,unsigned long ea,unsigned long access,unsigned long trap)1020 void hash_preload(struct mm_struct *mm, unsigned long ea,
1021 unsigned long access, unsigned long trap)
1022 {
1023 unsigned long vsid;
1024 void *pgdir;
1025 pte_t *ptep;
1026 cpumask_t mask;
1027 unsigned long flags;
1028 int local = 0;
1029 int ssize;
1030
1031 BUG_ON(REGION_ID(ea) != USER_REGION_ID);
1032
1033 #ifdef CONFIG_PPC_MM_SLICES
1034 /* We only prefault standard pages for now */
1035 if (unlikely(get_slice_psize(mm, ea) != mm->context.user_psize))
1036 return;
1037 #endif
1038
1039 DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
1040 " trap=%lx\n", mm, mm->pgd, ea, access, trap);
1041
1042 /* Get Linux PTE if available */
1043 pgdir = mm->pgd;
1044 if (pgdir == NULL)
1045 return;
1046 ptep = find_linux_pte(pgdir, ea);
1047 if (!ptep)
1048 return;
1049
1050 #ifdef CONFIG_PPC_64K_PAGES
1051 /* If either _PAGE_4K_PFN or _PAGE_NO_CACHE is set (and we are on
1052 * a 64K kernel), then we don't preload, hash_page() will take
1053 * care of it once we actually try to access the page.
1054 * That way we don't have to duplicate all of the logic for segment
1055 * page size demotion here
1056 */
1057 if (pte_val(*ptep) & (_PAGE_4K_PFN | _PAGE_NO_CACHE))
1058 return;
1059 #endif /* CONFIG_PPC_64K_PAGES */
1060
1061 /* Get VSID */
1062 ssize = user_segment_size(ea);
1063 vsid = get_vsid(mm->context.id, ea, ssize);
1064
1065 /* Hash doesn't like irqs */
1066 local_irq_save(flags);
1067
1068 /* Is that local to this CPU ? */
1069 mask = cpumask_of_cpu(smp_processor_id());
1070 if (cpus_equal(mm->cpu_vm_mask, mask))
1071 local = 1;
1072
1073 /* Hash it in */
1074 #ifdef CONFIG_PPC_HAS_HASH_64K
1075 if (mm->context.user_psize == MMU_PAGE_64K)
1076 __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize);
1077 else
1078 #endif /* CONFIG_PPC_HAS_HASH_64K */
1079 __hash_page_4K(ea, access, vsid, ptep, trap, local, ssize,
1080 subpage_protection(pgdir, ea));
1081
1082 local_irq_restore(flags);
1083 }
1084
1085 /* WARNING: This is called from hash_low_64.S, if you change this prototype,
1086 * do not forget to update the assembly call site !
1087 */
flush_hash_page(unsigned long va,real_pte_t pte,int psize,int ssize,int local)1088 void flush_hash_page(unsigned long va, real_pte_t pte, int psize, int ssize,
1089 int local)
1090 {
1091 unsigned long hash, index, shift, hidx, slot;
1092
1093 DBG_LOW("flush_hash_page(va=%016x)\n", va);
1094 pte_iterate_hashed_subpages(pte, psize, va, index, shift) {
1095 hash = hpt_hash(va, shift, ssize);
1096 hidx = __rpte_to_hidx(pte, index);
1097 if (hidx & _PTEIDX_SECONDARY)
1098 hash = ~hash;
1099 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1100 slot += hidx & _PTEIDX_GROUP_IX;
1101 DBG_LOW(" sub %d: hash=%x, hidx=%x\n", index, slot, hidx);
1102 ppc_md.hpte_invalidate(slot, va, psize, ssize, local);
1103 } pte_iterate_hashed_end();
1104 }
1105
flush_hash_range(unsigned long number,int local)1106 void flush_hash_range(unsigned long number, int local)
1107 {
1108 if (ppc_md.flush_hash_range)
1109 ppc_md.flush_hash_range(number, local);
1110 else {
1111 int i;
1112 struct ppc64_tlb_batch *batch =
1113 &__get_cpu_var(ppc64_tlb_batch);
1114
1115 for (i = 0; i < number; i++)
1116 flush_hash_page(batch->vaddr[i], batch->pte[i],
1117 batch->psize, batch->ssize, local);
1118 }
1119 }
1120
1121 /*
1122 * low_hash_fault is called when we the low level hash code failed
1123 * to instert a PTE due to an hypervisor error
1124 */
low_hash_fault(struct pt_regs * regs,unsigned long address,int rc)1125 void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc)
1126 {
1127 if (user_mode(regs)) {
1128 #ifdef CONFIG_PPC_SUBPAGE_PROT
1129 if (rc == -2)
1130 _exception(SIGSEGV, regs, SEGV_ACCERR, address);
1131 else
1132 #endif
1133 _exception(SIGBUS, regs, BUS_ADRERR, address);
1134 } else
1135 bad_page_fault(regs, address, SIGBUS);
1136 }
1137
1138 #ifdef CONFIG_DEBUG_PAGEALLOC
kernel_map_linear_page(unsigned long vaddr,unsigned long lmi)1139 static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi)
1140 {
1141 unsigned long hash, hpteg;
1142 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1143 unsigned long va = hpt_va(vaddr, vsid, mmu_kernel_ssize);
1144 unsigned long mode = htab_convert_pte_flags(PAGE_KERNEL);
1145 int ret;
1146
1147 hash = hpt_hash(va, PAGE_SHIFT, mmu_kernel_ssize);
1148 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
1149
1150 ret = ppc_md.hpte_insert(hpteg, va, __pa(vaddr),
1151 mode, HPTE_V_BOLTED,
1152 mmu_linear_psize, mmu_kernel_ssize);
1153 BUG_ON (ret < 0);
1154 spin_lock(&linear_map_hash_lock);
1155 BUG_ON(linear_map_hash_slots[lmi] & 0x80);
1156 linear_map_hash_slots[lmi] = ret | 0x80;
1157 spin_unlock(&linear_map_hash_lock);
1158 }
1159
kernel_unmap_linear_page(unsigned long vaddr,unsigned long lmi)1160 static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi)
1161 {
1162 unsigned long hash, hidx, slot;
1163 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1164 unsigned long va = hpt_va(vaddr, vsid, mmu_kernel_ssize);
1165
1166 hash = hpt_hash(va, PAGE_SHIFT, mmu_kernel_ssize);
1167 spin_lock(&linear_map_hash_lock);
1168 BUG_ON(!(linear_map_hash_slots[lmi] & 0x80));
1169 hidx = linear_map_hash_slots[lmi] & 0x7f;
1170 linear_map_hash_slots[lmi] = 0;
1171 spin_unlock(&linear_map_hash_lock);
1172 if (hidx & _PTEIDX_SECONDARY)
1173 hash = ~hash;
1174 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1175 slot += hidx & _PTEIDX_GROUP_IX;
1176 ppc_md.hpte_invalidate(slot, va, mmu_linear_psize, mmu_kernel_ssize, 0);
1177 }
1178
kernel_map_pages(struct page * page,int numpages,int enable)1179 void kernel_map_pages(struct page *page, int numpages, int enable)
1180 {
1181 unsigned long flags, vaddr, lmi;
1182 int i;
1183
1184 local_irq_save(flags);
1185 for (i = 0; i < numpages; i++, page++) {
1186 vaddr = (unsigned long)page_address(page);
1187 lmi = __pa(vaddr) >> PAGE_SHIFT;
1188 if (lmi >= linear_map_hash_count)
1189 continue;
1190 if (enable)
1191 kernel_map_linear_page(vaddr, lmi);
1192 else
1193 kernel_unmap_linear_page(vaddr, lmi);
1194 }
1195 local_irq_restore(flags);
1196 }
1197 #endif /* CONFIG_DEBUG_PAGEALLOC */
1198