1 /*
2 * Libata driver for the highpoint 37x and 30x UDMA66 ATA controllers.
3 *
4 * This driver is heavily based upon:
5 *
6 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
7 *
8 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
9 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
10 * Portions Copyright (C) 2003 Red Hat Inc
11 * Portions Copyright (C) 2005-2007 MontaVista Software, Inc.
12 *
13 * TODO
14 * Look into engine reset on timeout errors. Should not be required.
15 */
16
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/pci.h>
20 #include <linux/init.h>
21 #include <linux/blkdev.h>
22 #include <linux/delay.h>
23 #include <scsi/scsi_host.h>
24 #include <linux/libata.h>
25
26 #define DRV_NAME "pata_hpt37x"
27 #define DRV_VERSION "0.6.11"
28
29 struct hpt_clock {
30 u8 xfer_speed;
31 u32 timing;
32 };
33
34 struct hpt_chip {
35 const char *name;
36 unsigned int base;
37 struct hpt_clock const *clocks[4];
38 };
39
40 /* key for bus clock timings
41 * bit
42 * 0:3 data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
43 * DMA. cycles = value + 1
44 * 4:8 data_low_time. active time of DIOW_/DIOR_ for PIO and MW
45 * DMA. cycles = value + 1
46 * 9:12 cmd_high_time. inactive time of DIOW_/DIOR_ during task file
47 * register access.
48 * 13:17 cmd_low_time. active time of DIOW_/DIOR_ during task file
49 * register access.
50 * 18:21 udma_cycle_time. clock freq and clock cycles for UDMA xfer.
51 * during task file register access.
52 * 22:24 pre_high_time. time to initialize 1st cycle for PIO and MW DMA
53 * xfer.
54 * 25:27 cmd_pre_high_time. time to initialize 1st PIO cycle for task
55 * register access.
56 * 28 UDMA enable
57 * 29 DMA enable
58 * 30 PIO_MST enable. if set, the chip is in bus master mode during
59 * PIO.
60 * 31 FIFO enable.
61 */
62
63 static struct hpt_clock hpt37x_timings_33[] = {
64 { XFER_UDMA_6, 0x12446231 }, /* 0x12646231 ?? */
65 { XFER_UDMA_5, 0x12446231 },
66 { XFER_UDMA_4, 0x12446231 },
67 { XFER_UDMA_3, 0x126c6231 },
68 { XFER_UDMA_2, 0x12486231 },
69 { XFER_UDMA_1, 0x124c6233 },
70 { XFER_UDMA_0, 0x12506297 },
71
72 { XFER_MW_DMA_2, 0x22406c31 },
73 { XFER_MW_DMA_1, 0x22406c33 },
74 { XFER_MW_DMA_0, 0x22406c97 },
75
76 { XFER_PIO_4, 0x06414e31 },
77 { XFER_PIO_3, 0x06414e42 },
78 { XFER_PIO_2, 0x06414e53 },
79 { XFER_PIO_1, 0x06814e93 },
80 { XFER_PIO_0, 0x06814ea7 }
81 };
82
83 static struct hpt_clock hpt37x_timings_50[] = {
84 { XFER_UDMA_6, 0x12848242 },
85 { XFER_UDMA_5, 0x12848242 },
86 { XFER_UDMA_4, 0x12ac8242 },
87 { XFER_UDMA_3, 0x128c8242 },
88 { XFER_UDMA_2, 0x120c8242 },
89 { XFER_UDMA_1, 0x12148254 },
90 { XFER_UDMA_0, 0x121882ea },
91
92 { XFER_MW_DMA_2, 0x22808242 },
93 { XFER_MW_DMA_1, 0x22808254 },
94 { XFER_MW_DMA_0, 0x228082ea },
95
96 { XFER_PIO_4, 0x0a81f442 },
97 { XFER_PIO_3, 0x0a81f443 },
98 { XFER_PIO_2, 0x0a81f454 },
99 { XFER_PIO_1, 0x0ac1f465 },
100 { XFER_PIO_0, 0x0ac1f48a }
101 };
102
103 static struct hpt_clock hpt37x_timings_66[] = {
104 { XFER_UDMA_6, 0x1c869c62 },
105 { XFER_UDMA_5, 0x1cae9c62 }, /* 0x1c8a9c62 */
106 { XFER_UDMA_4, 0x1c8a9c62 },
107 { XFER_UDMA_3, 0x1c8e9c62 },
108 { XFER_UDMA_2, 0x1c929c62 },
109 { XFER_UDMA_1, 0x1c9a9c62 },
110 { XFER_UDMA_0, 0x1c829c62 },
111
112 { XFER_MW_DMA_2, 0x2c829c62 },
113 { XFER_MW_DMA_1, 0x2c829c66 },
114 { XFER_MW_DMA_0, 0x2c829d2e },
115
116 { XFER_PIO_4, 0x0c829c62 },
117 { XFER_PIO_3, 0x0c829c84 },
118 { XFER_PIO_2, 0x0c829ca6 },
119 { XFER_PIO_1, 0x0d029d26 },
120 { XFER_PIO_0, 0x0d029d5e }
121 };
122
123
124 static const struct hpt_chip hpt370 = {
125 "HPT370",
126 48,
127 {
128 hpt37x_timings_33,
129 NULL,
130 NULL,
131 NULL
132 }
133 };
134
135 static const struct hpt_chip hpt370a = {
136 "HPT370A",
137 48,
138 {
139 hpt37x_timings_33,
140 NULL,
141 hpt37x_timings_50,
142 NULL
143 }
144 };
145
146 static const struct hpt_chip hpt372 = {
147 "HPT372",
148 55,
149 {
150 hpt37x_timings_33,
151 NULL,
152 hpt37x_timings_50,
153 hpt37x_timings_66
154 }
155 };
156
157 static const struct hpt_chip hpt302 = {
158 "HPT302",
159 66,
160 {
161 hpt37x_timings_33,
162 NULL,
163 hpt37x_timings_50,
164 hpt37x_timings_66
165 }
166 };
167
168 static const struct hpt_chip hpt371 = {
169 "HPT371",
170 66,
171 {
172 hpt37x_timings_33,
173 NULL,
174 hpt37x_timings_50,
175 hpt37x_timings_66
176 }
177 };
178
179 static const struct hpt_chip hpt372a = {
180 "HPT372A",
181 66,
182 {
183 hpt37x_timings_33,
184 NULL,
185 hpt37x_timings_50,
186 hpt37x_timings_66
187 }
188 };
189
190 static const struct hpt_chip hpt374 = {
191 "HPT374",
192 48,
193 {
194 hpt37x_timings_33,
195 NULL,
196 NULL,
197 NULL
198 }
199 };
200
201 /**
202 * hpt37x_find_mode - reset the hpt37x bus
203 * @ap: ATA port
204 * @speed: transfer mode
205 *
206 * Return the 32bit register programming information for this channel
207 * that matches the speed provided.
208 */
209
hpt37x_find_mode(struct ata_port * ap,int speed)210 static u32 hpt37x_find_mode(struct ata_port *ap, int speed)
211 {
212 struct hpt_clock *clocks = ap->host->private_data;
213
214 while(clocks->xfer_speed) {
215 if (clocks->xfer_speed == speed)
216 return clocks->timing;
217 clocks++;
218 }
219 BUG();
220 return 0xffffffffU; /* silence compiler warning */
221 }
222
hpt_dma_blacklisted(const struct ata_device * dev,char * modestr,const char * list[])223 static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr, const char *list[])
224 {
225 unsigned char model_num[ATA_ID_PROD_LEN + 1];
226 int i = 0;
227
228 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
229
230 while (list[i] != NULL) {
231 if (!strcmp(list[i], model_num)) {
232 printk(KERN_WARNING DRV_NAME ": %s is not supported for %s.\n",
233 modestr, list[i]);
234 return 1;
235 }
236 i++;
237 }
238 return 0;
239 }
240
241 static const char *bad_ata33[] = {
242 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
243 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
244 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
245 "Maxtor 90510D4",
246 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
247 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
248 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
249 NULL
250 };
251
252 static const char *bad_ata100_5[] = {
253 "IBM-DTLA-307075",
254 "IBM-DTLA-307060",
255 "IBM-DTLA-307045",
256 "IBM-DTLA-307030",
257 "IBM-DTLA-307020",
258 "IBM-DTLA-307015",
259 "IBM-DTLA-305040",
260 "IBM-DTLA-305030",
261 "IBM-DTLA-305020",
262 "IC35L010AVER07-0",
263 "IC35L020AVER07-0",
264 "IC35L030AVER07-0",
265 "IC35L040AVER07-0",
266 "IC35L060AVER07-0",
267 "WDC AC310200R",
268 NULL
269 };
270
271 /**
272 * hpt370_filter - mode selection filter
273 * @adev: ATA device
274 *
275 * Block UDMA on devices that cause trouble with this controller.
276 */
277
hpt370_filter(struct ata_device * adev,unsigned long mask)278 static unsigned long hpt370_filter(struct ata_device *adev, unsigned long mask)
279 {
280 if (adev->class == ATA_DEV_ATA) {
281 if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33))
282 mask &= ~ATA_MASK_UDMA;
283 if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5))
284 mask &= ~(0xE0 << ATA_SHIFT_UDMA);
285 }
286 return ata_bmdma_mode_filter(adev, mask);
287 }
288
289 /**
290 * hpt370a_filter - mode selection filter
291 * @adev: ATA device
292 *
293 * Block UDMA on devices that cause trouble with this controller.
294 */
295
hpt370a_filter(struct ata_device * adev,unsigned long mask)296 static unsigned long hpt370a_filter(struct ata_device *adev, unsigned long mask)
297 {
298 if (adev->class == ATA_DEV_ATA) {
299 if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5))
300 mask &= ~(0xE0 << ATA_SHIFT_UDMA);
301 }
302 return ata_bmdma_mode_filter(adev, mask);
303 }
304
305 /**
306 * hpt37x_pre_reset - reset the hpt37x bus
307 * @link: ATA link to reset
308 * @deadline: deadline jiffies for the operation
309 *
310 * Perform the initial reset handling for the 370/372 and 374 func 0
311 */
312
hpt37x_pre_reset(struct ata_link * link,unsigned long deadline)313 static int hpt37x_pre_reset(struct ata_link *link, unsigned long deadline)
314 {
315 u8 scr2, ata66;
316 struct ata_port *ap = link->ap;
317 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
318 static const struct pci_bits hpt37x_enable_bits[] = {
319 { 0x50, 1, 0x04, 0x04 },
320 { 0x54, 1, 0x04, 0x04 }
321 };
322 if (!pci_test_config_bits(pdev, &hpt37x_enable_bits[ap->port_no]))
323 return -ENOENT;
324
325 pci_read_config_byte(pdev, 0x5B, &scr2);
326 pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01);
327 /* Cable register now active */
328 pci_read_config_byte(pdev, 0x5A, &ata66);
329 /* Restore state */
330 pci_write_config_byte(pdev, 0x5B, scr2);
331
332 if (ata66 & (2 >> ap->port_no))
333 ap->cbl = ATA_CBL_PATA40;
334 else
335 ap->cbl = ATA_CBL_PATA80;
336
337 /* Reset the state machine */
338 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
339 udelay(100);
340
341 return ata_sff_prereset(link, deadline);
342 }
343
hpt374_fn1_pre_reset(struct ata_link * link,unsigned long deadline)344 static int hpt374_fn1_pre_reset(struct ata_link *link, unsigned long deadline)
345 {
346 static const struct pci_bits hpt37x_enable_bits[] = {
347 { 0x50, 1, 0x04, 0x04 },
348 { 0x54, 1, 0x04, 0x04 }
349 };
350 u16 mcr3;
351 u8 ata66;
352 struct ata_port *ap = link->ap;
353 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
354 unsigned int mcrbase = 0x50 + 4 * ap->port_no;
355
356 if (!pci_test_config_bits(pdev, &hpt37x_enable_bits[ap->port_no]))
357 return -ENOENT;
358
359 /* Do the extra channel work */
360 pci_read_config_word(pdev, mcrbase + 2, &mcr3);
361 /* Set bit 15 of 0x52 to enable TCBLID as input
362 */
363 pci_write_config_word(pdev, mcrbase + 2, mcr3 | 0x8000);
364 pci_read_config_byte(pdev, 0x5A, &ata66);
365 /* Reset TCBLID/FCBLID to output */
366 pci_write_config_word(pdev, mcrbase + 2, mcr3);
367
368 if (ata66 & (2 >> ap->port_no))
369 ap->cbl = ATA_CBL_PATA40;
370 else
371 ap->cbl = ATA_CBL_PATA80;
372
373 /* Reset the state machine */
374 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
375 udelay(100);
376
377 return ata_sff_prereset(link, deadline);
378 }
379
380 /**
381 * hpt370_set_piomode - PIO setup
382 * @ap: ATA interface
383 * @adev: device on the interface
384 *
385 * Perform PIO mode setup.
386 */
387
hpt370_set_piomode(struct ata_port * ap,struct ata_device * adev)388 static void hpt370_set_piomode(struct ata_port *ap, struct ata_device *adev)
389 {
390 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
391 u32 addr1, addr2;
392 u32 reg;
393 u32 mode;
394 u8 fast;
395
396 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
397 addr2 = 0x51 + 4 * ap->port_no;
398
399 /* Fast interrupt prediction disable, hold off interrupt disable */
400 pci_read_config_byte(pdev, addr2, &fast);
401 fast &= ~0x02;
402 fast |= 0x01;
403 pci_write_config_byte(pdev, addr2, fast);
404
405 pci_read_config_dword(pdev, addr1, ®);
406 mode = hpt37x_find_mode(ap, adev->pio_mode);
407 mode &= ~0x8000000; /* No FIFO in PIO */
408 mode &= ~0x30070000; /* Leave config bits alone */
409 reg &= 0x30070000; /* Strip timing bits */
410 pci_write_config_dword(pdev, addr1, reg | mode);
411 }
412
413 /**
414 * hpt370_set_dmamode - DMA timing setup
415 * @ap: ATA interface
416 * @adev: Device being configured
417 *
418 * Set up the channel for MWDMA or UDMA modes. Much the same as with
419 * PIO, load the mode number and then set MWDMA or UDMA flag.
420 */
421
hpt370_set_dmamode(struct ata_port * ap,struct ata_device * adev)422 static void hpt370_set_dmamode(struct ata_port *ap, struct ata_device *adev)
423 {
424 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
425 u32 addr1, addr2;
426 u32 reg;
427 u32 mode;
428 u8 fast;
429
430 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
431 addr2 = 0x51 + 4 * ap->port_no;
432
433 /* Fast interrupt prediction disable, hold off interrupt disable */
434 pci_read_config_byte(pdev, addr2, &fast);
435 fast &= ~0x02;
436 fast |= 0x01;
437 pci_write_config_byte(pdev, addr2, fast);
438
439 pci_read_config_dword(pdev, addr1, ®);
440 mode = hpt37x_find_mode(ap, adev->dma_mode);
441 mode |= 0x8000000; /* FIFO in MWDMA or UDMA */
442 mode &= ~0xC0000000; /* Leave config bits alone */
443 reg &= 0xC0000000; /* Strip timing bits */
444 pci_write_config_dword(pdev, addr1, reg | mode);
445 }
446
447 /**
448 * hpt370_bmdma_start - DMA engine begin
449 * @qc: ATA command
450 *
451 * The 370 and 370A want us to reset the DMA engine each time we
452 * use it. The 372 and later are fine.
453 */
454
hpt370_bmdma_start(struct ata_queued_cmd * qc)455 static void hpt370_bmdma_start(struct ata_queued_cmd *qc)
456 {
457 struct ata_port *ap = qc->ap;
458 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
459 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
460 udelay(10);
461 ata_bmdma_start(qc);
462 }
463
464 /**
465 * hpt370_bmdma_end - DMA engine stop
466 * @qc: ATA command
467 *
468 * Work around the HPT370 DMA engine.
469 */
470
hpt370_bmdma_stop(struct ata_queued_cmd * qc)471 static void hpt370_bmdma_stop(struct ata_queued_cmd *qc)
472 {
473 struct ata_port *ap = qc->ap;
474 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
475 u8 dma_stat = ioread8(ap->ioaddr.bmdma_addr + 2);
476 u8 dma_cmd;
477 void __iomem *bmdma = ap->ioaddr.bmdma_addr;
478
479 if (dma_stat & 0x01) {
480 udelay(20);
481 dma_stat = ioread8(bmdma + 2);
482 }
483 if (dma_stat & 0x01) {
484 /* Clear the engine */
485 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
486 udelay(10);
487 /* Stop DMA */
488 dma_cmd = ioread8(bmdma );
489 iowrite8(dma_cmd & 0xFE, bmdma);
490 /* Clear Error */
491 dma_stat = ioread8(bmdma + 2);
492 iowrite8(dma_stat | 0x06 , bmdma + 2);
493 /* Clear the engine */
494 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
495 udelay(10);
496 }
497 ata_bmdma_stop(qc);
498 }
499
500 /**
501 * hpt372_set_piomode - PIO setup
502 * @ap: ATA interface
503 * @adev: device on the interface
504 *
505 * Perform PIO mode setup.
506 */
507
hpt372_set_piomode(struct ata_port * ap,struct ata_device * adev)508 static void hpt372_set_piomode(struct ata_port *ap, struct ata_device *adev)
509 {
510 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
511 u32 addr1, addr2;
512 u32 reg;
513 u32 mode;
514 u8 fast;
515
516 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
517 addr2 = 0x51 + 4 * ap->port_no;
518
519 /* Fast interrupt prediction disable, hold off interrupt disable */
520 pci_read_config_byte(pdev, addr2, &fast);
521 fast &= ~0x07;
522 pci_write_config_byte(pdev, addr2, fast);
523
524 pci_read_config_dword(pdev, addr1, ®);
525 mode = hpt37x_find_mode(ap, adev->pio_mode);
526
527 printk("Find mode for %d reports %X\n", adev->pio_mode, mode);
528 mode &= ~0x80000000; /* No FIFO in PIO */
529 mode &= ~0x30070000; /* Leave config bits alone */
530 reg &= 0x30070000; /* Strip timing bits */
531 pci_write_config_dword(pdev, addr1, reg | mode);
532 }
533
534 /**
535 * hpt372_set_dmamode - DMA timing setup
536 * @ap: ATA interface
537 * @adev: Device being configured
538 *
539 * Set up the channel for MWDMA or UDMA modes. Much the same as with
540 * PIO, load the mode number and then set MWDMA or UDMA flag.
541 */
542
hpt372_set_dmamode(struct ata_port * ap,struct ata_device * adev)543 static void hpt372_set_dmamode(struct ata_port *ap, struct ata_device *adev)
544 {
545 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
546 u32 addr1, addr2;
547 u32 reg;
548 u32 mode;
549 u8 fast;
550
551 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
552 addr2 = 0x51 + 4 * ap->port_no;
553
554 /* Fast interrupt prediction disable, hold off interrupt disable */
555 pci_read_config_byte(pdev, addr2, &fast);
556 fast &= ~0x07;
557 pci_write_config_byte(pdev, addr2, fast);
558
559 pci_read_config_dword(pdev, addr1, ®);
560 mode = hpt37x_find_mode(ap, adev->dma_mode);
561 printk("Find mode for DMA %d reports %X\n", adev->dma_mode, mode);
562 mode &= ~0xC0000000; /* Leave config bits alone */
563 mode |= 0x80000000; /* FIFO in MWDMA or UDMA */
564 reg &= 0xC0000000; /* Strip timing bits */
565 pci_write_config_dword(pdev, addr1, reg | mode);
566 }
567
568 /**
569 * hpt37x_bmdma_end - DMA engine stop
570 * @qc: ATA command
571 *
572 * Clean up after the HPT372 and later DMA engine
573 */
574
hpt37x_bmdma_stop(struct ata_queued_cmd * qc)575 static void hpt37x_bmdma_stop(struct ata_queued_cmd *qc)
576 {
577 struct ata_port *ap = qc->ap;
578 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
579 int mscreg = 0x50 + 4 * ap->port_no;
580 u8 bwsr_stat, msc_stat;
581
582 pci_read_config_byte(pdev, 0x6A, &bwsr_stat);
583 pci_read_config_byte(pdev, mscreg, &msc_stat);
584 if (bwsr_stat & (1 << ap->port_no))
585 pci_write_config_byte(pdev, mscreg, msc_stat | 0x30);
586 ata_bmdma_stop(qc);
587 }
588
589
590 static struct scsi_host_template hpt37x_sht = {
591 ATA_BMDMA_SHT(DRV_NAME),
592 };
593
594 /*
595 * Configuration for HPT370
596 */
597
598 static struct ata_port_operations hpt370_port_ops = {
599 .inherits = &ata_bmdma_port_ops,
600
601 .bmdma_start = hpt370_bmdma_start,
602 .bmdma_stop = hpt370_bmdma_stop,
603
604 .mode_filter = hpt370_filter,
605 .set_piomode = hpt370_set_piomode,
606 .set_dmamode = hpt370_set_dmamode,
607 .prereset = hpt37x_pre_reset,
608 };
609
610 /*
611 * Configuration for HPT370A. Close to 370 but less filters
612 */
613
614 static struct ata_port_operations hpt370a_port_ops = {
615 .inherits = &hpt370_port_ops,
616 .mode_filter = hpt370a_filter,
617 };
618
619 /*
620 * Configuration for HPT372, HPT371, HPT302. Slightly different PIO
621 * and DMA mode setting functionality.
622 */
623
624 static struct ata_port_operations hpt372_port_ops = {
625 .inherits = &ata_bmdma_port_ops,
626
627 .bmdma_stop = hpt37x_bmdma_stop,
628
629 .set_piomode = hpt372_set_piomode,
630 .set_dmamode = hpt372_set_dmamode,
631 .prereset = hpt37x_pre_reset,
632 };
633
634 /*
635 * Configuration for HPT374. Mode setting works like 372 and friends
636 * but we have a different cable detection procedure for function 1.
637 */
638
639 static struct ata_port_operations hpt374_fn1_port_ops = {
640 .inherits = &hpt372_port_ops,
641 .prereset = hpt374_fn1_pre_reset,
642 };
643
644 /**
645 * htp37x_clock_slot - Turn timing to PC clock entry
646 * @freq: Reported frequency timing
647 * @base: Base timing
648 *
649 * Turn the timing data intoa clock slot (0 for 33, 1 for 40, 2 for 50
650 * and 3 for 66Mhz)
651 */
652
hpt37x_clock_slot(unsigned int freq,unsigned int base)653 static int hpt37x_clock_slot(unsigned int freq, unsigned int base)
654 {
655 unsigned int f = (base * freq) / 192; /* Mhz */
656 if (f < 40)
657 return 0; /* 33Mhz slot */
658 if (f < 45)
659 return 1; /* 40Mhz slot */
660 if (f < 55)
661 return 2; /* 50Mhz slot */
662 return 3; /* 60Mhz slot */
663 }
664
665 /**
666 * hpt37x_calibrate_dpll - Calibrate the DPLL loop
667 * @dev: PCI device
668 *
669 * Perform a calibration cycle on the HPT37x DPLL. Returns 1 if this
670 * succeeds
671 */
672
hpt37x_calibrate_dpll(struct pci_dev * dev)673 static int hpt37x_calibrate_dpll(struct pci_dev *dev)
674 {
675 u8 reg5b;
676 u32 reg5c;
677 int tries;
678
679 for(tries = 0; tries < 0x5000; tries++) {
680 udelay(50);
681 pci_read_config_byte(dev, 0x5b, ®5b);
682 if (reg5b & 0x80) {
683 /* See if it stays set */
684 for(tries = 0; tries < 0x1000; tries ++) {
685 pci_read_config_byte(dev, 0x5b, ®5b);
686 /* Failed ? */
687 if ((reg5b & 0x80) == 0)
688 return 0;
689 }
690 /* Turn off tuning, we have the DPLL set */
691 pci_read_config_dword(dev, 0x5c, ®5c);
692 pci_write_config_dword(dev, 0x5c, reg5c & ~ 0x100);
693 return 1;
694 }
695 }
696 /* Never went stable */
697 return 0;
698 }
699
hpt374_read_freq(struct pci_dev * pdev)700 static u32 hpt374_read_freq(struct pci_dev *pdev)
701 {
702 u32 freq;
703 unsigned long io_base = pci_resource_start(pdev, 4);
704 if (PCI_FUNC(pdev->devfn) & 1) {
705 struct pci_dev *pdev_0;
706
707 pdev_0 = pci_get_slot(pdev->bus, pdev->devfn - 1);
708 /* Someone hot plugged the controller on us ? */
709 if (pdev_0 == NULL)
710 return 0;
711 io_base = pci_resource_start(pdev_0, 4);
712 freq = inl(io_base + 0x90);
713 pci_dev_put(pdev_0);
714 } else
715 freq = inl(io_base + 0x90);
716 return freq;
717 }
718
719 /**
720 * hpt37x_init_one - Initialise an HPT37X/302
721 * @dev: PCI device
722 * @id: Entry in match table
723 *
724 * Initialise an HPT37x device. There are some interesting complications
725 * here. Firstly the chip may report 366 and be one of several variants.
726 * Secondly all the timings depend on the clock for the chip which we must
727 * detect and look up
728 *
729 * This is the known chip mappings. It may be missing a couple of later
730 * releases.
731 *
732 * Chip version PCI Rev Notes
733 * HPT366 4 (HPT366) 0 Other driver
734 * HPT366 4 (HPT366) 1 Other driver
735 * HPT368 4 (HPT366) 2 Other driver
736 * HPT370 4 (HPT366) 3 UDMA100
737 * HPT370A 4 (HPT366) 4 UDMA100
738 * HPT372 4 (HPT366) 5 UDMA133 (1)
739 * HPT372N 4 (HPT366) 6 Other driver
740 * HPT372A 5 (HPT372) 1 UDMA133 (1)
741 * HPT372N 5 (HPT372) 2 Other driver
742 * HPT302 6 (HPT302) 1 UDMA133
743 * HPT302N 6 (HPT302) 2 Other driver
744 * HPT371 7 (HPT371) * UDMA133
745 * HPT374 8 (HPT374) * UDMA133 4 channel
746 * HPT372N 9 (HPT372N) * Other driver
747 *
748 * (1) UDMA133 support depends on the bus clock
749 */
750
hpt37x_init_one(struct pci_dev * dev,const struct pci_device_id * id)751 static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
752 {
753 /* HPT370 - UDMA100 */
754 static const struct ata_port_info info_hpt370 = {
755 .flags = ATA_FLAG_SLAVE_POSS,
756 .pio_mask = 0x1f,
757 .mwdma_mask = 0x07,
758 .udma_mask = ATA_UDMA5,
759 .port_ops = &hpt370_port_ops
760 };
761 /* HPT370A - UDMA100 */
762 static const struct ata_port_info info_hpt370a = {
763 .flags = ATA_FLAG_SLAVE_POSS,
764 .pio_mask = 0x1f,
765 .mwdma_mask = 0x07,
766 .udma_mask = ATA_UDMA5,
767 .port_ops = &hpt370a_port_ops
768 };
769 /* HPT370 - UDMA100 */
770 static const struct ata_port_info info_hpt370_33 = {
771 .flags = ATA_FLAG_SLAVE_POSS,
772 .pio_mask = 0x1f,
773 .mwdma_mask = 0x07,
774 .udma_mask = ATA_UDMA5,
775 .port_ops = &hpt370_port_ops
776 };
777 /* HPT370A - UDMA100 */
778 static const struct ata_port_info info_hpt370a_33 = {
779 .flags = ATA_FLAG_SLAVE_POSS,
780 .pio_mask = 0x1f,
781 .mwdma_mask = 0x07,
782 .udma_mask = ATA_UDMA5,
783 .port_ops = &hpt370a_port_ops
784 };
785 /* HPT371, 372 and friends - UDMA133 */
786 static const struct ata_port_info info_hpt372 = {
787 .flags = ATA_FLAG_SLAVE_POSS,
788 .pio_mask = 0x1f,
789 .mwdma_mask = 0x07,
790 .udma_mask = ATA_UDMA6,
791 .port_ops = &hpt372_port_ops
792 };
793 /* HPT374 - UDMA100, function 1 uses different prereset method */
794 static const struct ata_port_info info_hpt374_fn0 = {
795 .flags = ATA_FLAG_SLAVE_POSS,
796 .pio_mask = 0x1f,
797 .mwdma_mask = 0x07,
798 .udma_mask = ATA_UDMA5,
799 .port_ops = &hpt372_port_ops
800 };
801 static const struct ata_port_info info_hpt374_fn1 = {
802 .flags = ATA_FLAG_SLAVE_POSS,
803 .pio_mask = 0x1f,
804 .mwdma_mask = 0x07,
805 .udma_mask = ATA_UDMA5,
806 .port_ops = &hpt374_fn1_port_ops
807 };
808
809 static const int MHz[4] = { 33, 40, 50, 66 };
810 void *private_data = NULL;
811 const struct ata_port_info *ppi[] = { NULL, NULL };
812
813 u8 irqmask;
814 u32 class_rev;
815 u8 mcr1;
816 u32 freq;
817 int prefer_dpll = 1;
818
819 unsigned long iobase = pci_resource_start(dev, 4);
820
821 const struct hpt_chip *chip_table;
822 int clock_slot;
823 int rc;
824
825 rc = pcim_enable_device(dev);
826 if (rc)
827 return rc;
828
829 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
830 class_rev &= 0xFF;
831
832 if (dev->device == PCI_DEVICE_ID_TTI_HPT366) {
833 /* May be a later chip in disguise. Check */
834 /* Older chips are in the HPT366 driver. Ignore them */
835 if (class_rev < 3)
836 return -ENODEV;
837 /* N series chips have their own driver. Ignore */
838 if (class_rev == 6)
839 return -ENODEV;
840
841 switch(class_rev) {
842 case 3:
843 ppi[0] = &info_hpt370;
844 chip_table = &hpt370;
845 prefer_dpll = 0;
846 break;
847 case 4:
848 ppi[0] = &info_hpt370a;
849 chip_table = &hpt370a;
850 prefer_dpll = 0;
851 break;
852 case 5:
853 ppi[0] = &info_hpt372;
854 chip_table = &hpt372;
855 break;
856 default:
857 printk(KERN_ERR "pata_hpt37x: Unknown HPT366 subtype please report (%d).\n", class_rev);
858 return -ENODEV;
859 }
860 } else {
861 switch(dev->device) {
862 case PCI_DEVICE_ID_TTI_HPT372:
863 /* 372N if rev >= 2*/
864 if (class_rev >= 2)
865 return -ENODEV;
866 ppi[0] = &info_hpt372;
867 chip_table = &hpt372a;
868 break;
869 case PCI_DEVICE_ID_TTI_HPT302:
870 /* 302N if rev > 1 */
871 if (class_rev > 1)
872 return -ENODEV;
873 ppi[0] = &info_hpt372;
874 /* Check this */
875 chip_table = &hpt302;
876 break;
877 case PCI_DEVICE_ID_TTI_HPT371:
878 if (class_rev > 1)
879 return -ENODEV;
880 ppi[0] = &info_hpt372;
881 chip_table = &hpt371;
882 /* Single channel device, master is not present
883 but the BIOS (or us for non x86) must mark it
884 absent */
885 pci_read_config_byte(dev, 0x50, &mcr1);
886 mcr1 &= ~0x04;
887 pci_write_config_byte(dev, 0x50, mcr1);
888 break;
889 case PCI_DEVICE_ID_TTI_HPT374:
890 chip_table = &hpt374;
891 if (!(PCI_FUNC(dev->devfn) & 1))
892 *ppi = &info_hpt374_fn0;
893 else
894 *ppi = &info_hpt374_fn1;
895 break;
896 default:
897 printk(KERN_ERR "pata_hpt37x: PCI table is bogus please report (%d).\n", dev->device);
898 return -ENODEV;
899 }
900 }
901 /* Ok so this is a chip we support */
902
903 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
904 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
905 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
906 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
907
908 pci_read_config_byte(dev, 0x5A, &irqmask);
909 irqmask &= ~0x10;
910 pci_write_config_byte(dev, 0x5a, irqmask);
911
912 /*
913 * default to pci clock. make sure MA15/16 are set to output
914 * to prevent drives having problems with 40-pin cables. Needed
915 * for some drives such as IBM-DTLA which will not enter ready
916 * state on reset when PDIAG is a input.
917 */
918
919 pci_write_config_byte(dev, 0x5b, 0x23);
920
921 /*
922 * HighPoint does this for HPT372A.
923 * NOTE: This register is only writeable via I/O space.
924 */
925 if (chip_table == &hpt372a)
926 outb(0x0e, iobase + 0x9c);
927
928 /* Some devices do not let this value be accessed via PCI space
929 according to the old driver. In addition we must use the value
930 from FN 0 on the HPT374 */
931
932 if (chip_table == &hpt374) {
933 freq = hpt374_read_freq(dev);
934 if (freq == 0)
935 return -ENODEV;
936 } else
937 freq = inl(iobase + 0x90);
938
939 if ((freq >> 12) != 0xABCDE) {
940 int i;
941 u8 sr;
942 u32 total = 0;
943
944 printk(KERN_WARNING "pata_hpt37x: BIOS has not set timing clocks.\n");
945
946 /* This is the process the HPT371 BIOS is reported to use */
947 for(i = 0; i < 128; i++) {
948 pci_read_config_byte(dev, 0x78, &sr);
949 total += sr & 0x1FF;
950 udelay(15);
951 }
952 freq = total / 128;
953 }
954 freq &= 0x1FF;
955
956 /*
957 * Turn the frequency check into a band and then find a timing
958 * table to match it.
959 */
960
961 clock_slot = hpt37x_clock_slot(freq, chip_table->base);
962 if (chip_table->clocks[clock_slot] == NULL || prefer_dpll) {
963 /*
964 * We need to try PLL mode instead
965 *
966 * For non UDMA133 capable devices we should
967 * use a 50MHz DPLL by choice
968 */
969 unsigned int f_low, f_high;
970 int dpll, adjust;
971
972 /* Compute DPLL */
973 dpll = (ppi[0]->udma_mask & 0xC0) ? 3 : 2;
974
975 f_low = (MHz[clock_slot] * 48) / MHz[dpll];
976 f_high = f_low + 2;
977 if (clock_slot > 1)
978 f_high += 2;
979
980 /* Select the DPLL clock. */
981 pci_write_config_byte(dev, 0x5b, 0x21);
982 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100);
983
984 for(adjust = 0; adjust < 8; adjust++) {
985 if (hpt37x_calibrate_dpll(dev))
986 break;
987 /* See if it'll settle at a fractionally different clock */
988 if (adjust & 1)
989 f_low -= adjust >> 1;
990 else
991 f_high += adjust >> 1;
992 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100);
993 }
994 if (adjust == 8) {
995 printk(KERN_ERR "pata_hpt37x: DPLL did not stabilize!\n");
996 return -ENODEV;
997 }
998 if (dpll == 3)
999 private_data = (void *)hpt37x_timings_66;
1000 else
1001 private_data = (void *)hpt37x_timings_50;
1002
1003 printk(KERN_INFO "pata_hpt37x: bus clock %dMHz, using %dMHz DPLL.\n",
1004 MHz[clock_slot], MHz[dpll]);
1005 } else {
1006 private_data = (void *)chip_table->clocks[clock_slot];
1007 /*
1008 * Perform a final fixup. Note that we will have used the
1009 * DPLL on the HPT372 which means we don't have to worry
1010 * about lack of UDMA133 support on lower clocks
1011 */
1012
1013 if (clock_slot < 2 && ppi[0] == &info_hpt370)
1014 ppi[0] = &info_hpt370_33;
1015 if (clock_slot < 2 && ppi[0] == &info_hpt370a)
1016 ppi[0] = &info_hpt370a_33;
1017 printk(KERN_INFO "pata_hpt37x: %s using %dMHz bus clock.\n",
1018 chip_table->name, MHz[clock_slot]);
1019 }
1020
1021 /* Now kick off ATA set up */
1022 return ata_pci_sff_init_one(dev, ppi, &hpt37x_sht, private_data);
1023 }
1024
1025 static const struct pci_device_id hpt37x[] = {
1026 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
1027 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), },
1028 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), },
1029 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), },
1030 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), },
1031
1032 { },
1033 };
1034
1035 static struct pci_driver hpt37x_pci_driver = {
1036 .name = DRV_NAME,
1037 .id_table = hpt37x,
1038 .probe = hpt37x_init_one,
1039 .remove = ata_pci_remove_one
1040 };
1041
hpt37x_init(void)1042 static int __init hpt37x_init(void)
1043 {
1044 return pci_register_driver(&hpt37x_pci_driver);
1045 }
1046
hpt37x_exit(void)1047 static void __exit hpt37x_exit(void)
1048 {
1049 pci_unregister_driver(&hpt37x_pci_driver);
1050 }
1051
1052 MODULE_AUTHOR("Alan Cox");
1053 MODULE_DESCRIPTION("low-level driver for the Highpoint HPT37x/30x");
1054 MODULE_LICENSE("GPL");
1055 MODULE_DEVICE_TABLE(pci, hpt37x);
1056 MODULE_VERSION(DRV_VERSION);
1057
1058 module_init(hpt37x_init);
1059 module_exit(hpt37x_exit);
1060