• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1 /*
2  *	linux/arch/mips/dec/kn02-irq.c
3  *
4  *	DECstation 5000/200 (KN02) Control and Status Register
5  *	interrupts.
6  *
7  *	Copyright (c) 2002, 2003, 2005  Maciej W. Rozycki
8  *
9  *	This program is free software; you can redistribute it and/or
10  *	modify it under the terms of the GNU General Public License
11  *	as published by the Free Software Foundation; either version
12  *	2 of the License, or (at your option) any later version.
13  */
14 
15 #include <linux/init.h>
16 #include <linux/irq.h>
17 #include <linux/types.h>
18 
19 #include <asm/dec/kn02.h>
20 
21 
22 /*
23  * Bits 7:0 of the Control Register are write-only -- the
24  * corresponding bits of the Status Register have a different
25  * meaning.  Hence we use a cache.  It speeds up things a bit
26  * as well.
27  *
28  * There is no default value -- it has to be initialized.
29  */
30 u32 cached_kn02_csr;
31 
32 
33 static int kn02_irq_base;
34 
35 
unmask_kn02_irq(unsigned int irq)36 static inline void unmask_kn02_irq(unsigned int irq)
37 {
38 	volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
39 						       KN02_CSR);
40 
41 	cached_kn02_csr |= (1 << (irq - kn02_irq_base + 16));
42 	*csr = cached_kn02_csr;
43 }
44 
mask_kn02_irq(unsigned int irq)45 static inline void mask_kn02_irq(unsigned int irq)
46 {
47 	volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
48 						       KN02_CSR);
49 
50 	cached_kn02_csr &= ~(1 << (irq - kn02_irq_base + 16));
51 	*csr = cached_kn02_csr;
52 }
53 
ack_kn02_irq(unsigned int irq)54 static void ack_kn02_irq(unsigned int irq)
55 {
56 	mask_kn02_irq(irq);
57 	iob();
58 }
59 
60 static struct irq_chip kn02_irq_type = {
61 	.name = "KN02-CSR",
62 	.ack = ack_kn02_irq,
63 	.mask = mask_kn02_irq,
64 	.mask_ack = ack_kn02_irq,
65 	.unmask = unmask_kn02_irq,
66 };
67 
68 
init_kn02_irqs(int base)69 void __init init_kn02_irqs(int base)
70 {
71 	volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
72 						       KN02_CSR);
73 	int i;
74 
75 	/* Mask interrupts. */
76 	cached_kn02_csr &= ~KN02_CSR_IOINTEN;
77 	*csr = cached_kn02_csr;
78 	iob();
79 
80 	for (i = base; i < base + KN02_IRQ_LINES; i++)
81 		set_irq_chip_and_handler(i, &kn02_irq_type, handle_level_irq);
82 
83 	kn02_irq_base = base;
84 }
85