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1 /*
2  *  arch/powerpc/kernel/mpic.c
3  *
4  *  Driver for interrupt controllers following the OpenPIC standard, the
5  *  common implementation beeing IBM's MPIC. This driver also can deal
6  *  with various broken implementations of this HW.
7  *
8  *  Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
9  *
10  *  This file is subject to the terms and conditions of the GNU General Public
11  *  License.  See the file COPYING in the main directory of this archive
12  *  for more details.
13  */
14 
15 #undef DEBUG
16 #undef DEBUG_IPI
17 #undef DEBUG_IRQ
18 #undef DEBUG_LOW
19 
20 #include <linux/types.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/irq.h>
24 #include <linux/smp.h>
25 #include <linux/interrupt.h>
26 #include <linux/bootmem.h>
27 #include <linux/spinlock.h>
28 #include <linux/pci.h>
29 
30 #include <asm/ptrace.h>
31 #include <asm/signal.h>
32 #include <asm/io.h>
33 #include <asm/pgtable.h>
34 #include <asm/irq.h>
35 #include <asm/machdep.h>
36 #include <asm/mpic.h>
37 #include <asm/smp.h>
38 
39 #include "mpic.h"
40 
41 #ifdef DEBUG
42 #define DBG(fmt...) printk(fmt)
43 #else
44 #define DBG(fmt...)
45 #endif
46 
47 static struct mpic *mpics;
48 static struct mpic *mpic_primary;
49 static DEFINE_SPINLOCK(mpic_lock);
50 
51 #ifdef CONFIG_PPC32	/* XXX for now */
52 #ifdef CONFIG_IRQ_ALL_CPUS
53 #define distribute_irqs	(1)
54 #else
55 #define distribute_irqs	(0)
56 #endif
57 #endif
58 
59 #ifdef CONFIG_MPIC_WEIRD
60 static u32 mpic_infos[][MPIC_IDX_END] = {
61 	[0] = {	/* Original OpenPIC compatible MPIC */
62 		MPIC_GREG_BASE,
63 		MPIC_GREG_FEATURE_0,
64 		MPIC_GREG_GLOBAL_CONF_0,
65 		MPIC_GREG_VENDOR_ID,
66 		MPIC_GREG_IPI_VECTOR_PRI_0,
67 		MPIC_GREG_IPI_STRIDE,
68 		MPIC_GREG_SPURIOUS,
69 		MPIC_GREG_TIMER_FREQ,
70 
71 		MPIC_TIMER_BASE,
72 		MPIC_TIMER_STRIDE,
73 		MPIC_TIMER_CURRENT_CNT,
74 		MPIC_TIMER_BASE_CNT,
75 		MPIC_TIMER_VECTOR_PRI,
76 		MPIC_TIMER_DESTINATION,
77 
78 		MPIC_CPU_BASE,
79 		MPIC_CPU_STRIDE,
80 		MPIC_CPU_IPI_DISPATCH_0,
81 		MPIC_CPU_IPI_DISPATCH_STRIDE,
82 		MPIC_CPU_CURRENT_TASK_PRI,
83 		MPIC_CPU_WHOAMI,
84 		MPIC_CPU_INTACK,
85 		MPIC_CPU_EOI,
86 		MPIC_CPU_MCACK,
87 
88 		MPIC_IRQ_BASE,
89 		MPIC_IRQ_STRIDE,
90 		MPIC_IRQ_VECTOR_PRI,
91 		MPIC_VECPRI_VECTOR_MASK,
92 		MPIC_VECPRI_POLARITY_POSITIVE,
93 		MPIC_VECPRI_POLARITY_NEGATIVE,
94 		MPIC_VECPRI_SENSE_LEVEL,
95 		MPIC_VECPRI_SENSE_EDGE,
96 		MPIC_VECPRI_POLARITY_MASK,
97 		MPIC_VECPRI_SENSE_MASK,
98 		MPIC_IRQ_DESTINATION
99 	},
100 	[1] = {	/* Tsi108/109 PIC */
101 		TSI108_GREG_BASE,
102 		TSI108_GREG_FEATURE_0,
103 		TSI108_GREG_GLOBAL_CONF_0,
104 		TSI108_GREG_VENDOR_ID,
105 		TSI108_GREG_IPI_VECTOR_PRI_0,
106 		TSI108_GREG_IPI_STRIDE,
107 		TSI108_GREG_SPURIOUS,
108 		TSI108_GREG_TIMER_FREQ,
109 
110 		TSI108_TIMER_BASE,
111 		TSI108_TIMER_STRIDE,
112 		TSI108_TIMER_CURRENT_CNT,
113 		TSI108_TIMER_BASE_CNT,
114 		TSI108_TIMER_VECTOR_PRI,
115 		TSI108_TIMER_DESTINATION,
116 
117 		TSI108_CPU_BASE,
118 		TSI108_CPU_STRIDE,
119 		TSI108_CPU_IPI_DISPATCH_0,
120 		TSI108_CPU_IPI_DISPATCH_STRIDE,
121 		TSI108_CPU_CURRENT_TASK_PRI,
122 		TSI108_CPU_WHOAMI,
123 		TSI108_CPU_INTACK,
124 		TSI108_CPU_EOI,
125 		TSI108_CPU_MCACK,
126 
127 		TSI108_IRQ_BASE,
128 		TSI108_IRQ_STRIDE,
129 		TSI108_IRQ_VECTOR_PRI,
130 		TSI108_VECPRI_VECTOR_MASK,
131 		TSI108_VECPRI_POLARITY_POSITIVE,
132 		TSI108_VECPRI_POLARITY_NEGATIVE,
133 		TSI108_VECPRI_SENSE_LEVEL,
134 		TSI108_VECPRI_SENSE_EDGE,
135 		TSI108_VECPRI_POLARITY_MASK,
136 		TSI108_VECPRI_SENSE_MASK,
137 		TSI108_IRQ_DESTINATION
138 	},
139 };
140 
141 #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
142 
143 #else /* CONFIG_MPIC_WEIRD */
144 
145 #define MPIC_INFO(name) MPIC_##name
146 
147 #endif /* CONFIG_MPIC_WEIRD */
148 
149 /*
150  * Register accessor functions
151  */
152 
153 
_mpic_read(enum mpic_reg_type type,struct mpic_reg_bank * rb,unsigned int reg)154 static inline u32 _mpic_read(enum mpic_reg_type type,
155 			     struct mpic_reg_bank *rb,
156 			     unsigned int reg)
157 {
158 	switch(type) {
159 #ifdef CONFIG_PPC_DCR
160 	case mpic_access_dcr:
161 		return dcr_read(rb->dhost, reg);
162 #endif
163 	case mpic_access_mmio_be:
164 		return in_be32(rb->base + (reg >> 2));
165 	case mpic_access_mmio_le:
166 	default:
167 		return in_le32(rb->base + (reg >> 2));
168 	}
169 }
170 
_mpic_write(enum mpic_reg_type type,struct mpic_reg_bank * rb,unsigned int reg,u32 value)171 static inline void _mpic_write(enum mpic_reg_type type,
172 			       struct mpic_reg_bank *rb,
173  			       unsigned int reg, u32 value)
174 {
175 	switch(type) {
176 #ifdef CONFIG_PPC_DCR
177 	case mpic_access_dcr:
178 		dcr_write(rb->dhost, reg, value);
179 		break;
180 #endif
181 	case mpic_access_mmio_be:
182 		out_be32(rb->base + (reg >> 2), value);
183 		break;
184 	case mpic_access_mmio_le:
185 	default:
186 		out_le32(rb->base + (reg >> 2), value);
187 		break;
188 	}
189 }
190 
_mpic_ipi_read(struct mpic * mpic,unsigned int ipi)191 static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
192 {
193 	enum mpic_reg_type type = mpic->reg_type;
194 	unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
195 			      (ipi * MPIC_INFO(GREG_IPI_STRIDE));
196 
197 	if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le)
198 		type = mpic_access_mmio_be;
199 	return _mpic_read(type, &mpic->gregs, offset);
200 }
201 
_mpic_ipi_write(struct mpic * mpic,unsigned int ipi,u32 value)202 static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
203 {
204 	unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
205 			      (ipi * MPIC_INFO(GREG_IPI_STRIDE));
206 
207 	_mpic_write(mpic->reg_type, &mpic->gregs, offset, value);
208 }
209 
_mpic_cpu_read(struct mpic * mpic,unsigned int reg)210 static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
211 {
212 	unsigned int cpu = 0;
213 
214 	if (mpic->flags & MPIC_PRIMARY)
215 		cpu = hard_smp_processor_id();
216 	return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg);
217 }
218 
_mpic_cpu_write(struct mpic * mpic,unsigned int reg,u32 value)219 static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)
220 {
221 	unsigned int cpu = 0;
222 
223 	if (mpic->flags & MPIC_PRIMARY)
224 		cpu = hard_smp_processor_id();
225 
226 	_mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value);
227 }
228 
_mpic_irq_read(struct mpic * mpic,unsigned int src_no,unsigned int reg)229 static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg)
230 {
231 	unsigned int	isu = src_no >> mpic->isu_shift;
232 	unsigned int	idx = src_no & mpic->isu_mask;
233 
234 #ifdef CONFIG_MPIC_BROKEN_REGREAD
235 	if (reg == 0)
236 		return mpic->isu_reg0_shadow[idx];
237 	else
238 #endif
239 		return _mpic_read(mpic->reg_type, &mpic->isus[isu],
240 				  reg + (idx * MPIC_INFO(IRQ_STRIDE)));
241 }
242 
_mpic_irq_write(struct mpic * mpic,unsigned int src_no,unsigned int reg,u32 value)243 static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
244 				   unsigned int reg, u32 value)
245 {
246 	unsigned int	isu = src_no >> mpic->isu_shift;
247 	unsigned int	idx = src_no & mpic->isu_mask;
248 
249 	_mpic_write(mpic->reg_type, &mpic->isus[isu],
250 		    reg + (idx * MPIC_INFO(IRQ_STRIDE)), value);
251 
252 #ifdef CONFIG_MPIC_BROKEN_REGREAD
253 	if (reg == 0)
254 		mpic->isu_reg0_shadow[idx] = value;
255 #endif
256 }
257 
258 #define mpic_read(b,r)		_mpic_read(mpic->reg_type,&(b),(r))
259 #define mpic_write(b,r,v)	_mpic_write(mpic->reg_type,&(b),(r),(v))
260 #define mpic_ipi_read(i)	_mpic_ipi_read(mpic,(i))
261 #define mpic_ipi_write(i,v)	_mpic_ipi_write(mpic,(i),(v))
262 #define mpic_cpu_read(i)	_mpic_cpu_read(mpic,(i))
263 #define mpic_cpu_write(i,v)	_mpic_cpu_write(mpic,(i),(v))
264 #define mpic_irq_read(s,r)	_mpic_irq_read(mpic,(s),(r))
265 #define mpic_irq_write(s,r,v)	_mpic_irq_write(mpic,(s),(r),(v))
266 
267 
268 /*
269  * Low level utility functions
270  */
271 
272 
_mpic_map_mmio(struct mpic * mpic,phys_addr_t phys_addr,struct mpic_reg_bank * rb,unsigned int offset,unsigned int size)273 static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr,
274 			   struct mpic_reg_bank *rb, unsigned int offset,
275 			   unsigned int size)
276 {
277 	rb->base = ioremap(phys_addr + offset, size);
278 	BUG_ON(rb->base == NULL);
279 }
280 
281 #ifdef CONFIG_PPC_DCR
_mpic_map_dcr(struct mpic * mpic,struct mpic_reg_bank * rb,unsigned int offset,unsigned int size)282 static void _mpic_map_dcr(struct mpic *mpic, struct mpic_reg_bank *rb,
283 			  unsigned int offset, unsigned int size)
284 {
285 	const u32 *dbasep;
286 
287 	dbasep = of_get_property(mpic->irqhost->of_node, "dcr-reg", NULL);
288 
289 	rb->dhost = dcr_map(mpic->irqhost->of_node, *dbasep + offset, size);
290 	BUG_ON(!DCR_MAP_OK(rb->dhost));
291 }
292 
mpic_map(struct mpic * mpic,phys_addr_t phys_addr,struct mpic_reg_bank * rb,unsigned int offset,unsigned int size)293 static inline void mpic_map(struct mpic *mpic, phys_addr_t phys_addr,
294 			    struct mpic_reg_bank *rb, unsigned int offset,
295 			    unsigned int size)
296 {
297 	if (mpic->flags & MPIC_USES_DCR)
298 		_mpic_map_dcr(mpic, rb, offset, size);
299 	else
300 		_mpic_map_mmio(mpic, phys_addr, rb, offset, size);
301 }
302 #else /* CONFIG_PPC_DCR */
303 #define mpic_map(m,p,b,o,s)	_mpic_map_mmio(m,p,b,o,s)
304 #endif /* !CONFIG_PPC_DCR */
305 
306 
307 
308 /* Check if we have one of those nice broken MPICs with a flipped endian on
309  * reads from IPI registers
310  */
mpic_test_broken_ipi(struct mpic * mpic)311 static void __init mpic_test_broken_ipi(struct mpic *mpic)
312 {
313 	u32 r;
314 
315 	mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK);
316 	r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0));
317 
318 	if (r == le32_to_cpu(MPIC_VECPRI_MASK)) {
319 		printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
320 		mpic->flags |= MPIC_BROKEN_IPI;
321 	}
322 }
323 
324 #ifdef CONFIG_MPIC_U3_HT_IRQS
325 
326 /* Test if an interrupt is sourced from HyperTransport (used on broken U3s)
327  * to force the edge setting on the MPIC and do the ack workaround.
328  */
mpic_is_ht_interrupt(struct mpic * mpic,unsigned int source)329 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
330 {
331 	if (source >= 128 || !mpic->fixups)
332 		return 0;
333 	return mpic->fixups[source].base != NULL;
334 }
335 
336 
mpic_ht_end_irq(struct mpic * mpic,unsigned int source)337 static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source)
338 {
339 	struct mpic_irq_fixup *fixup = &mpic->fixups[source];
340 
341 	if (fixup->applebase) {
342 		unsigned int soff = (fixup->index >> 3) & ~3;
343 		unsigned int mask = 1U << (fixup->index & 0x1f);
344 		writel(mask, fixup->applebase + soff);
345 	} else {
346 		spin_lock(&mpic->fixup_lock);
347 		writeb(0x11 + 2 * fixup->index, fixup->base + 2);
348 		writel(fixup->data, fixup->base + 4);
349 		spin_unlock(&mpic->fixup_lock);
350 	}
351 }
352 
mpic_startup_ht_interrupt(struct mpic * mpic,unsigned int source,unsigned int irqflags)353 static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,
354 				      unsigned int irqflags)
355 {
356 	struct mpic_irq_fixup *fixup = &mpic->fixups[source];
357 	unsigned long flags;
358 	u32 tmp;
359 
360 	if (fixup->base == NULL)
361 		return;
362 
363 	DBG("startup_ht_interrupt(0x%x, 0x%x) index: %d\n",
364 	    source, irqflags, fixup->index);
365 	spin_lock_irqsave(&mpic->fixup_lock, flags);
366 	/* Enable and configure */
367 	writeb(0x10 + 2 * fixup->index, fixup->base + 2);
368 	tmp = readl(fixup->base + 4);
369 	tmp &= ~(0x23U);
370 	if (irqflags & IRQ_LEVEL)
371 		tmp |= 0x22;
372 	writel(tmp, fixup->base + 4);
373 	spin_unlock_irqrestore(&mpic->fixup_lock, flags);
374 
375 #ifdef CONFIG_PM
376 	/* use the lowest bit inverted to the actual HW,
377 	 * set if this fixup was enabled, clear otherwise */
378 	mpic->save_data[source].fixup_data = tmp | 1;
379 #endif
380 }
381 
mpic_shutdown_ht_interrupt(struct mpic * mpic,unsigned int source,unsigned int irqflags)382 static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source,
383 				       unsigned int irqflags)
384 {
385 	struct mpic_irq_fixup *fixup = &mpic->fixups[source];
386 	unsigned long flags;
387 	u32 tmp;
388 
389 	if (fixup->base == NULL)
390 		return;
391 
392 	DBG("shutdown_ht_interrupt(0x%x, 0x%x)\n", source, irqflags);
393 
394 	/* Disable */
395 	spin_lock_irqsave(&mpic->fixup_lock, flags);
396 	writeb(0x10 + 2 * fixup->index, fixup->base + 2);
397 	tmp = readl(fixup->base + 4);
398 	tmp |= 1;
399 	writel(tmp, fixup->base + 4);
400 	spin_unlock_irqrestore(&mpic->fixup_lock, flags);
401 
402 #ifdef CONFIG_PM
403 	/* use the lowest bit inverted to the actual HW,
404 	 * set if this fixup was enabled, clear otherwise */
405 	mpic->save_data[source].fixup_data = tmp & ~1;
406 #endif
407 }
408 
409 #ifdef CONFIG_PCI_MSI
mpic_scan_ht_msi(struct mpic * mpic,u8 __iomem * devbase,unsigned int devfn)410 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
411 				    unsigned int devfn)
412 {
413 	u8 __iomem *base;
414 	u8 pos, flags;
415 	u64 addr = 0;
416 
417 	for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
418 	     pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
419 		u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
420 		if (id == PCI_CAP_ID_HT) {
421 			id = readb(devbase + pos + 3);
422 			if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING)
423 				break;
424 		}
425 	}
426 
427 	if (pos == 0)
428 		return;
429 
430 	base = devbase + pos;
431 
432 	flags = readb(base + HT_MSI_FLAGS);
433 	if (!(flags & HT_MSI_FLAGS_FIXED)) {
434 		addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK;
435 		addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32);
436 	}
437 
438 	printk(KERN_DEBUG "mpic:   - HT:%02x.%x %s MSI mapping found @ 0x%llx\n",
439 		PCI_SLOT(devfn), PCI_FUNC(devfn),
440 		flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr);
441 
442 	if (!(flags & HT_MSI_FLAGS_ENABLE))
443 		writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS);
444 }
445 #else
mpic_scan_ht_msi(struct mpic * mpic,u8 __iomem * devbase,unsigned int devfn)446 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
447 				    unsigned int devfn)
448 {
449 	return;
450 }
451 #endif
452 
mpic_scan_ht_pic(struct mpic * mpic,u8 __iomem * devbase,unsigned int devfn,u32 vdid)453 static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase,
454 				    unsigned int devfn, u32 vdid)
455 {
456 	int i, irq, n;
457 	u8 __iomem *base;
458 	u32 tmp;
459 	u8 pos;
460 
461 	for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
462 	     pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
463 		u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
464 		if (id == PCI_CAP_ID_HT) {
465 			id = readb(devbase + pos + 3);
466 			if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ)
467 				break;
468 		}
469 	}
470 	if (pos == 0)
471 		return;
472 
473 	base = devbase + pos;
474 	writeb(0x01, base + 2);
475 	n = (readl(base + 4) >> 16) & 0xff;
476 
477 	printk(KERN_INFO "mpic:   - HT:%02x.%x [0x%02x] vendor %04x device %04x"
478 	       " has %d irqs\n",
479 	       devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1);
480 
481 	for (i = 0; i <= n; i++) {
482 		writeb(0x10 + 2 * i, base + 2);
483 		tmp = readl(base + 4);
484 		irq = (tmp >> 16) & 0xff;
485 		DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp);
486 		/* mask it , will be unmasked later */
487 		tmp |= 0x1;
488 		writel(tmp, base + 4);
489 		mpic->fixups[irq].index = i;
490 		mpic->fixups[irq].base = base;
491 		/* Apple HT PIC has a non-standard way of doing EOIs */
492 		if ((vdid & 0xffff) == 0x106b)
493 			mpic->fixups[irq].applebase = devbase + 0x60;
494 		else
495 			mpic->fixups[irq].applebase = NULL;
496 		writeb(0x11 + 2 * i, base + 2);
497 		mpic->fixups[irq].data = readl(base + 4) | 0x80000000;
498 	}
499 }
500 
501 
mpic_scan_ht_pics(struct mpic * mpic)502 static void __init mpic_scan_ht_pics(struct mpic *mpic)
503 {
504 	unsigned int devfn;
505 	u8 __iomem *cfgspace;
506 
507 	printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n");
508 
509 	/* Allocate fixups array */
510 	mpic->fixups = alloc_bootmem(128 * sizeof(struct mpic_irq_fixup));
511 	BUG_ON(mpic->fixups == NULL);
512 	memset(mpic->fixups, 0, 128 * sizeof(struct mpic_irq_fixup));
513 
514 	/* Init spinlock */
515 	spin_lock_init(&mpic->fixup_lock);
516 
517 	/* Map U3 config space. We assume all IO-APICs are on the primary bus
518 	 * so we only need to map 64kB.
519 	 */
520 	cfgspace = ioremap(0xf2000000, 0x10000);
521 	BUG_ON(cfgspace == NULL);
522 
523 	/* Now we scan all slots. We do a very quick scan, we read the header
524 	 * type, vendor ID and device ID only, that's plenty enough
525 	 */
526 	for (devfn = 0; devfn < 0x100; devfn++) {
527 		u8 __iomem *devbase = cfgspace + (devfn << 8);
528 		u8 hdr_type = readb(devbase + PCI_HEADER_TYPE);
529 		u32 l = readl(devbase + PCI_VENDOR_ID);
530 		u16 s;
531 
532 		DBG("devfn %x, l: %x\n", devfn, l);
533 
534 		/* If no device, skip */
535 		if (l == 0xffffffff || l == 0x00000000 ||
536 		    l == 0x0000ffff || l == 0xffff0000)
537 			goto next;
538 		/* Check if is supports capability lists */
539 		s = readw(devbase + PCI_STATUS);
540 		if (!(s & PCI_STATUS_CAP_LIST))
541 			goto next;
542 
543 		mpic_scan_ht_pic(mpic, devbase, devfn, l);
544 		mpic_scan_ht_msi(mpic, devbase, devfn);
545 
546 	next:
547 		/* next device, if function 0 */
548 		if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0)
549 			devfn += 7;
550 	}
551 }
552 
553 #else /* CONFIG_MPIC_U3_HT_IRQS */
554 
mpic_is_ht_interrupt(struct mpic * mpic,unsigned int source)555 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
556 {
557 	return 0;
558 }
559 
mpic_scan_ht_pics(struct mpic * mpic)560 static void __init mpic_scan_ht_pics(struct mpic *mpic)
561 {
562 }
563 
564 #endif /* CONFIG_MPIC_U3_HT_IRQS */
565 
566 #ifdef CONFIG_SMP
irq_choose_cpu(unsigned int virt_irq)567 static int irq_choose_cpu(unsigned int virt_irq)
568 {
569 	cpumask_t mask = irq_desc[virt_irq].affinity;
570 	int cpuid;
571 
572 	if (cpus_equal(mask, CPU_MASK_ALL)) {
573 		static int irq_rover;
574 		static DEFINE_SPINLOCK(irq_rover_lock);
575 		unsigned long flags;
576 
577 		/* Round-robin distribution... */
578 	do_round_robin:
579 		spin_lock_irqsave(&irq_rover_lock, flags);
580 
581 		while (!cpu_online(irq_rover)) {
582 			if (++irq_rover >= NR_CPUS)
583 				irq_rover = 0;
584 		}
585 		cpuid = irq_rover;
586 		do {
587 			if (++irq_rover >= NR_CPUS)
588 				irq_rover = 0;
589 		} while (!cpu_online(irq_rover));
590 
591 		spin_unlock_irqrestore(&irq_rover_lock, flags);
592 	} else {
593 		cpumask_t tmp;
594 
595 		cpus_and(tmp, cpu_online_map, mask);
596 
597 		if (cpus_empty(tmp))
598 			goto do_round_robin;
599 
600 		cpuid = first_cpu(tmp);
601 	}
602 
603 	return get_hard_smp_processor_id(cpuid);
604 }
605 #else
irq_choose_cpu(unsigned int virt_irq)606 static int irq_choose_cpu(unsigned int virt_irq)
607 {
608 	return hard_smp_processor_id();
609 }
610 #endif
611 
612 #define mpic_irq_to_hw(virq)	((unsigned int)irq_map[virq].hwirq)
613 
614 /* Find an mpic associated with a given linux interrupt */
mpic_find(unsigned int irq,unsigned int * is_ipi)615 static struct mpic *mpic_find(unsigned int irq, unsigned int *is_ipi)
616 {
617 	unsigned int src = mpic_irq_to_hw(irq);
618 	struct mpic *mpic;
619 
620 	if (irq < NUM_ISA_INTERRUPTS)
621 		return NULL;
622 
623 	mpic = irq_desc[irq].chip_data;
624 
625 	if (is_ipi)
626 		*is_ipi = (src >= mpic->ipi_vecs[0] &&
627 			   src <= mpic->ipi_vecs[3]);
628 
629 	return mpic;
630 }
631 
632 /* Convert a cpu mask from logical to physical cpu numbers. */
mpic_physmask(u32 cpumask)633 static inline u32 mpic_physmask(u32 cpumask)
634 {
635 	int i;
636 	u32 mask = 0;
637 
638 	for (i = 0; i < NR_CPUS; ++i, cpumask >>= 1)
639 		mask |= (cpumask & 1) << get_hard_smp_processor_id(i);
640 	return mask;
641 }
642 
643 #ifdef CONFIG_SMP
644 /* Get the mpic structure from the IPI number */
mpic_from_ipi(unsigned int ipi)645 static inline struct mpic * mpic_from_ipi(unsigned int ipi)
646 {
647 	return irq_desc[ipi].chip_data;
648 }
649 #endif
650 
651 /* Get the mpic structure from the irq number */
mpic_from_irq(unsigned int irq)652 static inline struct mpic * mpic_from_irq(unsigned int irq)
653 {
654 	return irq_desc[irq].chip_data;
655 }
656 
657 /* Send an EOI */
mpic_eoi(struct mpic * mpic)658 static inline void mpic_eoi(struct mpic *mpic)
659 {
660 	mpic_cpu_write(MPIC_INFO(CPU_EOI), 0);
661 	(void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI));
662 }
663 
664 /*
665  * Linux descriptor level callbacks
666  */
667 
668 
mpic_unmask_irq(unsigned int irq)669 void mpic_unmask_irq(unsigned int irq)
670 {
671 	unsigned int loops = 100000;
672 	struct mpic *mpic = mpic_from_irq(irq);
673 	unsigned int src = mpic_irq_to_hw(irq);
674 
675 	DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, irq, src);
676 
677 	mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
678 		       mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) &
679 		       ~MPIC_VECPRI_MASK);
680 	/* make sure mask gets to controller before we return to user */
681 	do {
682 		if (!loops--) {
683 			printk(KERN_ERR "mpic_enable_irq timeout\n");
684 			break;
685 		}
686 	} while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK);
687 }
688 
mpic_mask_irq(unsigned int irq)689 void mpic_mask_irq(unsigned int irq)
690 {
691 	unsigned int loops = 100000;
692 	struct mpic *mpic = mpic_from_irq(irq);
693 	unsigned int src = mpic_irq_to_hw(irq);
694 
695 	DBG("%s: disable_irq: %d (src %d)\n", mpic->name, irq, src);
696 
697 	mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
698 		       mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
699 		       MPIC_VECPRI_MASK);
700 
701 	/* make sure mask gets to controller before we return to user */
702 	do {
703 		if (!loops--) {
704 			printk(KERN_ERR "mpic_enable_irq timeout\n");
705 			break;
706 		}
707 	} while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK));
708 }
709 
mpic_end_irq(unsigned int irq)710 void mpic_end_irq(unsigned int irq)
711 {
712 	struct mpic *mpic = mpic_from_irq(irq);
713 
714 #ifdef DEBUG_IRQ
715 	DBG("%s: end_irq: %d\n", mpic->name, irq);
716 #endif
717 	/* We always EOI on end_irq() even for edge interrupts since that
718 	 * should only lower the priority, the MPIC should have properly
719 	 * latched another edge interrupt coming in anyway
720 	 */
721 
722 	mpic_eoi(mpic);
723 }
724 
725 #ifdef CONFIG_MPIC_U3_HT_IRQS
726 
mpic_unmask_ht_irq(unsigned int irq)727 static void mpic_unmask_ht_irq(unsigned int irq)
728 {
729 	struct mpic *mpic = mpic_from_irq(irq);
730 	unsigned int src = mpic_irq_to_hw(irq);
731 
732 	mpic_unmask_irq(irq);
733 
734 	if (irq_desc[irq].status & IRQ_LEVEL)
735 		mpic_ht_end_irq(mpic, src);
736 }
737 
mpic_startup_ht_irq(unsigned int irq)738 static unsigned int mpic_startup_ht_irq(unsigned int irq)
739 {
740 	struct mpic *mpic = mpic_from_irq(irq);
741 	unsigned int src = mpic_irq_to_hw(irq);
742 
743 	mpic_unmask_irq(irq);
744 	mpic_startup_ht_interrupt(mpic, src, irq_desc[irq].status);
745 
746 	return 0;
747 }
748 
mpic_shutdown_ht_irq(unsigned int irq)749 static void mpic_shutdown_ht_irq(unsigned int irq)
750 {
751 	struct mpic *mpic = mpic_from_irq(irq);
752 	unsigned int src = mpic_irq_to_hw(irq);
753 
754 	mpic_shutdown_ht_interrupt(mpic, src, irq_desc[irq].status);
755 	mpic_mask_irq(irq);
756 }
757 
mpic_end_ht_irq(unsigned int irq)758 static void mpic_end_ht_irq(unsigned int irq)
759 {
760 	struct mpic *mpic = mpic_from_irq(irq);
761 	unsigned int src = mpic_irq_to_hw(irq);
762 
763 #ifdef DEBUG_IRQ
764 	DBG("%s: end_irq: %d\n", mpic->name, irq);
765 #endif
766 	/* We always EOI on end_irq() even for edge interrupts since that
767 	 * should only lower the priority, the MPIC should have properly
768 	 * latched another edge interrupt coming in anyway
769 	 */
770 
771 	if (irq_desc[irq].status & IRQ_LEVEL)
772 		mpic_ht_end_irq(mpic, src);
773 	mpic_eoi(mpic);
774 }
775 #endif /* !CONFIG_MPIC_U3_HT_IRQS */
776 
777 #ifdef CONFIG_SMP
778 
mpic_unmask_ipi(unsigned int irq)779 static void mpic_unmask_ipi(unsigned int irq)
780 {
781 	struct mpic *mpic = mpic_from_ipi(irq);
782 	unsigned int src = mpic_irq_to_hw(irq) - mpic->ipi_vecs[0];
783 
784 	DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, irq, src);
785 	mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK);
786 }
787 
mpic_mask_ipi(unsigned int irq)788 static void mpic_mask_ipi(unsigned int irq)
789 {
790 	/* NEVER disable an IPI... that's just plain wrong! */
791 }
792 
mpic_end_ipi(unsigned int irq)793 static void mpic_end_ipi(unsigned int irq)
794 {
795 	struct mpic *mpic = mpic_from_ipi(irq);
796 
797 	/*
798 	 * IPIs are marked IRQ_PER_CPU. This has the side effect of
799 	 * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from
800 	 * applying to them. We EOI them late to avoid re-entering.
801 	 * We mark IPI's with IRQF_DISABLED as they must run with
802 	 * irqs disabled.
803 	 */
804 	mpic_eoi(mpic);
805 }
806 
807 #endif /* CONFIG_SMP */
808 
mpic_set_affinity(unsigned int irq,const struct cpumask * cpumask)809 void mpic_set_affinity(unsigned int irq, const struct cpumask *cpumask)
810 {
811 	struct mpic *mpic = mpic_from_irq(irq);
812 	unsigned int src = mpic_irq_to_hw(irq);
813 
814 	if (mpic->flags & MPIC_SINGLE_DEST_CPU) {
815 		int cpuid = irq_choose_cpu(irq);
816 
817 		mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
818 	} else {
819 		cpumask_t tmp;
820 
821 		cpumask_and(&tmp, cpumask, cpu_online_mask);
822 
823 		mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION),
824 			       mpic_physmask(cpus_addr(tmp)[0]));
825 	}
826 }
827 
mpic_type_to_vecpri(struct mpic * mpic,unsigned int type)828 static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
829 {
830 	/* Now convert sense value */
831 	switch(type & IRQ_TYPE_SENSE_MASK) {
832 	case IRQ_TYPE_EDGE_RISING:
833 		return MPIC_INFO(VECPRI_SENSE_EDGE) |
834 		       MPIC_INFO(VECPRI_POLARITY_POSITIVE);
835 	case IRQ_TYPE_EDGE_FALLING:
836 	case IRQ_TYPE_EDGE_BOTH:
837 		return MPIC_INFO(VECPRI_SENSE_EDGE) |
838 		       MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
839 	case IRQ_TYPE_LEVEL_HIGH:
840 		return MPIC_INFO(VECPRI_SENSE_LEVEL) |
841 		       MPIC_INFO(VECPRI_POLARITY_POSITIVE);
842 	case IRQ_TYPE_LEVEL_LOW:
843 	default:
844 		return MPIC_INFO(VECPRI_SENSE_LEVEL) |
845 		       MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
846 	}
847 }
848 
mpic_set_irq_type(unsigned int virq,unsigned int flow_type)849 int mpic_set_irq_type(unsigned int virq, unsigned int flow_type)
850 {
851 	struct mpic *mpic = mpic_from_irq(virq);
852 	unsigned int src = mpic_irq_to_hw(virq);
853 	struct irq_desc *desc = get_irq_desc(virq);
854 	unsigned int vecpri, vold, vnew;
855 
856 	DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
857 	    mpic, virq, src, flow_type);
858 
859 	if (src >= mpic->irq_count)
860 		return -EINVAL;
861 
862 	if (flow_type == IRQ_TYPE_NONE)
863 		if (mpic->senses && src < mpic->senses_count)
864 			flow_type = mpic->senses[src];
865 	if (flow_type == IRQ_TYPE_NONE)
866 		flow_type = IRQ_TYPE_LEVEL_LOW;
867 
868 	desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
869 	desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
870 	if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
871 		desc->status |= IRQ_LEVEL;
872 
873 	if (mpic_is_ht_interrupt(mpic, src))
874 		vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
875 			MPIC_VECPRI_SENSE_EDGE;
876 	else
877 		vecpri = mpic_type_to_vecpri(mpic, flow_type);
878 
879 	vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
880 	vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |
881 			MPIC_INFO(VECPRI_SENSE_MASK));
882 	vnew |= vecpri;
883 	if (vold != vnew)
884 		mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew);
885 
886 	return 0;
887 }
888 
mpic_set_vector(unsigned int virq,unsigned int vector)889 void mpic_set_vector(unsigned int virq, unsigned int vector)
890 {
891 	struct mpic *mpic = mpic_from_irq(virq);
892 	unsigned int src = mpic_irq_to_hw(virq);
893 	unsigned int vecpri;
894 
895 	DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n",
896 	    mpic, virq, src, vector);
897 
898 	if (src >= mpic->irq_count)
899 		return;
900 
901 	vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
902 	vecpri = vecpri & ~MPIC_INFO(VECPRI_VECTOR_MASK);
903 	vecpri |= vector;
904 	mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
905 }
906 
907 static struct irq_chip mpic_irq_chip = {
908 	.mask		= mpic_mask_irq,
909 	.unmask		= mpic_unmask_irq,
910 	.eoi		= mpic_end_irq,
911 	.set_type	= mpic_set_irq_type,
912 };
913 
914 #ifdef CONFIG_SMP
915 static struct irq_chip mpic_ipi_chip = {
916 	.mask		= mpic_mask_ipi,
917 	.unmask		= mpic_unmask_ipi,
918 	.eoi		= mpic_end_ipi,
919 };
920 #endif /* CONFIG_SMP */
921 
922 #ifdef CONFIG_MPIC_U3_HT_IRQS
923 static struct irq_chip mpic_irq_ht_chip = {
924 	.startup	= mpic_startup_ht_irq,
925 	.shutdown	= mpic_shutdown_ht_irq,
926 	.mask		= mpic_mask_irq,
927 	.unmask		= mpic_unmask_ht_irq,
928 	.eoi		= mpic_end_ht_irq,
929 	.set_type	= mpic_set_irq_type,
930 };
931 #endif /* CONFIG_MPIC_U3_HT_IRQS */
932 
933 
mpic_host_match(struct irq_host * h,struct device_node * node)934 static int mpic_host_match(struct irq_host *h, struct device_node *node)
935 {
936 	/* Exact match, unless mpic node is NULL */
937 	return h->of_node == NULL || h->of_node == node;
938 }
939 
mpic_host_map(struct irq_host * h,unsigned int virq,irq_hw_number_t hw)940 static int mpic_host_map(struct irq_host *h, unsigned int virq,
941 			 irq_hw_number_t hw)
942 {
943 	struct mpic *mpic = h->host_data;
944 	struct irq_chip *chip;
945 
946 	DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw);
947 
948 	if (hw == mpic->spurious_vec)
949 		return -EINVAL;
950 	if (mpic->protected && test_bit(hw, mpic->protected))
951 		return -EINVAL;
952 
953 #ifdef CONFIG_SMP
954 	else if (hw >= mpic->ipi_vecs[0]) {
955 		WARN_ON(!(mpic->flags & MPIC_PRIMARY));
956 
957 		DBG("mpic: mapping as IPI\n");
958 		set_irq_chip_data(virq, mpic);
959 		set_irq_chip_and_handler(virq, &mpic->hc_ipi,
960 					 handle_percpu_irq);
961 		return 0;
962 	}
963 #endif /* CONFIG_SMP */
964 
965 	if (hw >= mpic->irq_count)
966 		return -EINVAL;
967 
968 	mpic_msi_reserve_hwirq(mpic, hw);
969 
970 	/* Default chip */
971 	chip = &mpic->hc_irq;
972 
973 #ifdef CONFIG_MPIC_U3_HT_IRQS
974 	/* Check for HT interrupts, override vecpri */
975 	if (mpic_is_ht_interrupt(mpic, hw))
976 		chip = &mpic->hc_ht_irq;
977 #endif /* CONFIG_MPIC_U3_HT_IRQS */
978 
979 	DBG("mpic: mapping to irq chip @%p\n", chip);
980 
981 	set_irq_chip_data(virq, mpic);
982 	set_irq_chip_and_handler(virq, chip, handle_fasteoi_irq);
983 
984 	/* Set default irq type */
985 	set_irq_type(virq, IRQ_TYPE_NONE);
986 
987 	return 0;
988 }
989 
mpic_host_xlate(struct irq_host * h,struct device_node * ct,u32 * intspec,unsigned int intsize,irq_hw_number_t * out_hwirq,unsigned int * out_flags)990 static int mpic_host_xlate(struct irq_host *h, struct device_node *ct,
991 			   u32 *intspec, unsigned int intsize,
992 			   irq_hw_number_t *out_hwirq, unsigned int *out_flags)
993 
994 {
995 	static unsigned char map_mpic_senses[4] = {
996 		IRQ_TYPE_EDGE_RISING,
997 		IRQ_TYPE_LEVEL_LOW,
998 		IRQ_TYPE_LEVEL_HIGH,
999 		IRQ_TYPE_EDGE_FALLING,
1000 	};
1001 
1002 	*out_hwirq = intspec[0];
1003 	if (intsize > 1) {
1004 		u32 mask = 0x3;
1005 
1006 		/* Apple invented a new race of encoding on machines with
1007 		 * an HT APIC. They encode, among others, the index within
1008 		 * the HT APIC. We don't care about it here since thankfully,
1009 		 * it appears that they have the APIC already properly
1010 		 * configured, and thus our current fixup code that reads the
1011 		 * APIC config works fine. However, we still need to mask out
1012 		 * bits in the specifier to make sure we only get bit 0 which
1013 		 * is the level/edge bit (the only sense bit exposed by Apple),
1014 		 * as their bit 1 means something else.
1015 		 */
1016 		if (machine_is(powermac))
1017 			mask = 0x1;
1018 		*out_flags = map_mpic_senses[intspec[1] & mask];
1019 	} else
1020 		*out_flags = IRQ_TYPE_NONE;
1021 
1022 	DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n",
1023 	    intsize, intspec[0], intspec[1], *out_hwirq, *out_flags);
1024 
1025 	return 0;
1026 }
1027 
1028 static struct irq_host_ops mpic_host_ops = {
1029 	.match = mpic_host_match,
1030 	.map = mpic_host_map,
1031 	.xlate = mpic_host_xlate,
1032 };
1033 
1034 /*
1035  * Exported functions
1036  */
1037 
mpic_alloc(struct device_node * node,phys_addr_t phys_addr,unsigned int flags,unsigned int isu_size,unsigned int irq_count,const char * name)1038 struct mpic * __init mpic_alloc(struct device_node *node,
1039 				phys_addr_t phys_addr,
1040 				unsigned int flags,
1041 				unsigned int isu_size,
1042 				unsigned int irq_count,
1043 				const char *name)
1044 {
1045 	struct mpic	*mpic;
1046 	u32		greg_feature;
1047 	const char	*vers;
1048 	int		i;
1049 	int		intvec_top;
1050 	u64		paddr = phys_addr;
1051 
1052 	mpic = alloc_bootmem(sizeof(struct mpic));
1053 	if (mpic == NULL)
1054 		return NULL;
1055 
1056 	memset(mpic, 0, sizeof(struct mpic));
1057 	mpic->name = name;
1058 
1059 	mpic->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR,
1060 				       isu_size, &mpic_host_ops,
1061 				       flags & MPIC_LARGE_VECTORS ? 2048 : 256);
1062 	if (mpic->irqhost == NULL)
1063 		return NULL;
1064 
1065 	mpic->irqhost->host_data = mpic;
1066 	mpic->hc_irq = mpic_irq_chip;
1067 	mpic->hc_irq.typename = name;
1068 	if (flags & MPIC_PRIMARY)
1069 		mpic->hc_irq.set_affinity = mpic_set_affinity;
1070 #ifdef CONFIG_MPIC_U3_HT_IRQS
1071 	mpic->hc_ht_irq = mpic_irq_ht_chip;
1072 	mpic->hc_ht_irq.typename = name;
1073 	if (flags & MPIC_PRIMARY)
1074 		mpic->hc_ht_irq.set_affinity = mpic_set_affinity;
1075 #endif /* CONFIG_MPIC_U3_HT_IRQS */
1076 
1077 #ifdef CONFIG_SMP
1078 	mpic->hc_ipi = mpic_ipi_chip;
1079 	mpic->hc_ipi.typename = name;
1080 #endif /* CONFIG_SMP */
1081 
1082 	mpic->flags = flags;
1083 	mpic->isu_size = isu_size;
1084 	mpic->irq_count = irq_count;
1085 	mpic->num_sources = 0; /* so far */
1086 
1087 	if (flags & MPIC_LARGE_VECTORS)
1088 		intvec_top = 2047;
1089 	else
1090 		intvec_top = 255;
1091 
1092 	mpic->timer_vecs[0] = intvec_top - 8;
1093 	mpic->timer_vecs[1] = intvec_top - 7;
1094 	mpic->timer_vecs[2] = intvec_top - 6;
1095 	mpic->timer_vecs[3] = intvec_top - 5;
1096 	mpic->ipi_vecs[0]   = intvec_top - 4;
1097 	mpic->ipi_vecs[1]   = intvec_top - 3;
1098 	mpic->ipi_vecs[2]   = intvec_top - 2;
1099 	mpic->ipi_vecs[3]   = intvec_top - 1;
1100 	mpic->spurious_vec  = intvec_top;
1101 
1102 	/* Check for "big-endian" in device-tree */
1103 	if (node && of_get_property(node, "big-endian", NULL) != NULL)
1104 		mpic->flags |= MPIC_BIG_ENDIAN;
1105 
1106 	/* Look for protected sources */
1107 	if (node) {
1108 		int psize;
1109 		unsigned int bits, mapsize;
1110 		const u32 *psrc =
1111 			of_get_property(node, "protected-sources", &psize);
1112 		if (psrc) {
1113 			psize /= 4;
1114 			bits = intvec_top + 1;
1115 			mapsize = BITS_TO_LONGS(bits) * sizeof(unsigned long);
1116 			mpic->protected = alloc_bootmem(mapsize);
1117 			BUG_ON(mpic->protected == NULL);
1118 			memset(mpic->protected, 0, mapsize);
1119 			for (i = 0; i < psize; i++) {
1120 				if (psrc[i] > intvec_top)
1121 					continue;
1122 				__set_bit(psrc[i], mpic->protected);
1123 			}
1124 		}
1125 	}
1126 
1127 #ifdef CONFIG_MPIC_WEIRD
1128 	mpic->hw_set = mpic_infos[MPIC_GET_REGSET(flags)];
1129 #endif
1130 
1131 	/* default register type */
1132 	mpic->reg_type = (flags & MPIC_BIG_ENDIAN) ?
1133 		mpic_access_mmio_be : mpic_access_mmio_le;
1134 
1135 	/* If no physical address is passed in, a device-node is mandatory */
1136 	BUG_ON(paddr == 0 && node == NULL);
1137 
1138 	/* If no physical address passed in, check if it's dcr based */
1139 	if (paddr == 0 && of_get_property(node, "dcr-reg", NULL) != NULL) {
1140 #ifdef CONFIG_PPC_DCR
1141 		mpic->flags |= MPIC_USES_DCR;
1142 		mpic->reg_type = mpic_access_dcr;
1143 #else
1144 		BUG();
1145 #endif /* CONFIG_PPC_DCR */
1146 	}
1147 
1148 	/* If the MPIC is not DCR based, and no physical address was passed
1149 	 * in, try to obtain one
1150 	 */
1151 	if (paddr == 0 && !(mpic->flags & MPIC_USES_DCR)) {
1152 		const u32 *reg = of_get_property(node, "reg", NULL);
1153 		BUG_ON(reg == NULL);
1154 		paddr = of_translate_address(node, reg);
1155 		BUG_ON(paddr == OF_BAD_ADDR);
1156 	}
1157 
1158 	/* Map the global registers */
1159 	mpic_map(mpic, paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000);
1160 	mpic_map(mpic, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
1161 
1162 	/* Reset */
1163 	if (flags & MPIC_WANTS_RESET) {
1164 		mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1165 			   mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1166 			   | MPIC_GREG_GCONF_RESET);
1167 		while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1168 		       & MPIC_GREG_GCONF_RESET)
1169 			mb();
1170 	}
1171 
1172 	if (flags & MPIC_ENABLE_MCK)
1173 		mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1174 			   mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1175 			   | MPIC_GREG_GCONF_MCK);
1176 
1177 	/* Read feature register, calculate num CPUs and, for non-ISU
1178 	 * MPICs, num sources as well. On ISU MPICs, sources are counted
1179 	 * as ISUs are added
1180 	 */
1181 	greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
1182 	mpic->num_cpus = ((greg_feature & MPIC_GREG_FEATURE_LAST_CPU_MASK)
1183 			  >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1;
1184 	if (isu_size == 0) {
1185 		if (flags & MPIC_BROKEN_FRR_NIRQS)
1186 			mpic->num_sources = mpic->irq_count;
1187 		else
1188 			mpic->num_sources =
1189 				((greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK)
1190 				 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1;
1191 	}
1192 
1193 	/* Map the per-CPU registers */
1194 	for (i = 0; i < mpic->num_cpus; i++) {
1195 		mpic_map(mpic, paddr, &mpic->cpuregs[i],
1196 			 MPIC_INFO(CPU_BASE) + i * MPIC_INFO(CPU_STRIDE),
1197 			 0x1000);
1198 	}
1199 
1200 	/* Initialize main ISU if none provided */
1201 	if (mpic->isu_size == 0) {
1202 		mpic->isu_size = mpic->num_sources;
1203 		mpic_map(mpic, paddr, &mpic->isus[0],
1204 			 MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1205 	}
1206 	mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
1207 	mpic->isu_mask = (1 << mpic->isu_shift) - 1;
1208 
1209 	/* Display version */
1210 	switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) {
1211 	case 1:
1212 		vers = "1.0";
1213 		break;
1214 	case 2:
1215 		vers = "1.2";
1216 		break;
1217 	case 3:
1218 		vers = "1.3";
1219 		break;
1220 	default:
1221 		vers = "<unknown>";
1222 		break;
1223 	}
1224 	printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx,"
1225 	       " max %d CPUs\n",
1226 	       name, vers, (unsigned long long)paddr, mpic->num_cpus);
1227 	printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n",
1228 	       mpic->isu_size, mpic->isu_shift, mpic->isu_mask);
1229 
1230 	mpic->next = mpics;
1231 	mpics = mpic;
1232 
1233 	if (flags & MPIC_PRIMARY) {
1234 		mpic_primary = mpic;
1235 		irq_set_default_host(mpic->irqhost);
1236 	}
1237 
1238 	return mpic;
1239 }
1240 
mpic_assign_isu(struct mpic * mpic,unsigned int isu_num,phys_addr_t paddr)1241 void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
1242 			    phys_addr_t paddr)
1243 {
1244 	unsigned int isu_first = isu_num * mpic->isu_size;
1245 
1246 	BUG_ON(isu_num >= MPIC_MAX_ISU);
1247 
1248 	mpic_map(mpic, paddr, &mpic->isus[isu_num], 0,
1249 		 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1250 	if ((isu_first + mpic->isu_size) > mpic->num_sources)
1251 		mpic->num_sources = isu_first + mpic->isu_size;
1252 }
1253 
mpic_set_default_senses(struct mpic * mpic,u8 * senses,int count)1254 void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count)
1255 {
1256 	mpic->senses = senses;
1257 	mpic->senses_count = count;
1258 }
1259 
mpic_init(struct mpic * mpic)1260 void __init mpic_init(struct mpic *mpic)
1261 {
1262 	int i;
1263 	int cpu;
1264 
1265 	BUG_ON(mpic->num_sources == 0);
1266 
1267 	printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);
1268 
1269 	/* Set current processor priority to max */
1270 	mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1271 
1272 	/* Initialize timers: just disable them all */
1273 	for (i = 0; i < 4; i++) {
1274 		mpic_write(mpic->tmregs,
1275 			   i * MPIC_INFO(TIMER_STRIDE) +
1276 			   MPIC_INFO(TIMER_DESTINATION), 0);
1277 		mpic_write(mpic->tmregs,
1278 			   i * MPIC_INFO(TIMER_STRIDE) +
1279 			   MPIC_INFO(TIMER_VECTOR_PRI),
1280 			   MPIC_VECPRI_MASK |
1281 			   (mpic->timer_vecs[0] + i));
1282 	}
1283 
1284 	/* Initialize IPIs to our reserved vectors and mark them disabled for now */
1285 	mpic_test_broken_ipi(mpic);
1286 	for (i = 0; i < 4; i++) {
1287 		mpic_ipi_write(i,
1288 			       MPIC_VECPRI_MASK |
1289 			       (10 << MPIC_VECPRI_PRIORITY_SHIFT) |
1290 			       (mpic->ipi_vecs[0] + i));
1291 	}
1292 
1293 	/* Initialize interrupt sources */
1294 	if (mpic->irq_count == 0)
1295 		mpic->irq_count = mpic->num_sources;
1296 
1297 	/* Do the HT PIC fixups on U3 broken mpic */
1298 	DBG("MPIC flags: %x\n", mpic->flags);
1299 	if ((mpic->flags & MPIC_U3_HT_IRQS) && (mpic->flags & MPIC_PRIMARY)) {
1300 		mpic_scan_ht_pics(mpic);
1301 		mpic_u3msi_init(mpic);
1302 	}
1303 
1304 	mpic_pasemi_msi_init(mpic);
1305 
1306 	if (mpic->flags & MPIC_PRIMARY)
1307 		cpu = hard_smp_processor_id();
1308 	else
1309 		cpu = 0;
1310 
1311 	for (i = 0; i < mpic->num_sources; i++) {
1312 		/* start with vector = source number, and masked */
1313 		u32 vecpri = MPIC_VECPRI_MASK | i |
1314 			(8 << MPIC_VECPRI_PRIORITY_SHIFT);
1315 
1316 		/* check if protected */
1317 		if (mpic->protected && test_bit(i, mpic->protected))
1318 			continue;
1319 		/* init hw */
1320 		mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
1321 		mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu);
1322 	}
1323 
1324 	/* Init spurious vector */
1325 	mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec);
1326 
1327 	/* Disable 8259 passthrough, if supported */
1328 	if (!(mpic->flags & MPIC_NO_PTHROU_DIS))
1329 		mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1330 			   mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1331 			   | MPIC_GREG_GCONF_8259_PTHROU_DIS);
1332 
1333 	if (mpic->flags & MPIC_NO_BIAS)
1334 		mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1335 			mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1336 			| MPIC_GREG_GCONF_NO_BIAS);
1337 
1338 	/* Set current processor priority to 0 */
1339 	mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1340 
1341 #ifdef CONFIG_PM
1342 	/* allocate memory to save mpic state */
1343 	mpic->save_data = alloc_bootmem(mpic->num_sources * sizeof(struct mpic_irq_save));
1344 	BUG_ON(mpic->save_data == NULL);
1345 #endif
1346 }
1347 
mpic_set_clk_ratio(struct mpic * mpic,u32 clock_ratio)1348 void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio)
1349 {
1350 	u32 v;
1351 
1352 	v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1353 	v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK;
1354 	v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio);
1355 	mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1356 }
1357 
mpic_set_serial_int(struct mpic * mpic,int enable)1358 void __init mpic_set_serial_int(struct mpic *mpic, int enable)
1359 {
1360 	unsigned long flags;
1361 	u32 v;
1362 
1363 	spin_lock_irqsave(&mpic_lock, flags);
1364 	v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1365 	if (enable)
1366 		v |= MPIC_GREG_GLOBAL_CONF_1_SIE;
1367 	else
1368 		v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE;
1369 	mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1370 	spin_unlock_irqrestore(&mpic_lock, flags);
1371 }
1372 
mpic_irq_set_priority(unsigned int irq,unsigned int pri)1373 void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
1374 {
1375 	unsigned int is_ipi;
1376 	struct mpic *mpic = mpic_find(irq, &is_ipi);
1377 	unsigned int src = mpic_irq_to_hw(irq);
1378 	unsigned long flags;
1379 	u32 reg;
1380 
1381 	if (!mpic)
1382 		return;
1383 
1384 	spin_lock_irqsave(&mpic_lock, flags);
1385 	if (is_ipi) {
1386 		reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) &
1387 			~MPIC_VECPRI_PRIORITY_MASK;
1388 		mpic_ipi_write(src - mpic->ipi_vecs[0],
1389 			       reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1390 	} else {
1391 		reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI))
1392 			& ~MPIC_VECPRI_PRIORITY_MASK;
1393 		mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
1394 			       reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1395 	}
1396 	spin_unlock_irqrestore(&mpic_lock, flags);
1397 }
1398 
mpic_setup_this_cpu(void)1399 void mpic_setup_this_cpu(void)
1400 {
1401 #ifdef CONFIG_SMP
1402 	struct mpic *mpic = mpic_primary;
1403 	unsigned long flags;
1404 	u32 msk = 1 << hard_smp_processor_id();
1405 	unsigned int i;
1406 
1407 	BUG_ON(mpic == NULL);
1408 
1409 	DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1410 
1411 	spin_lock_irqsave(&mpic_lock, flags);
1412 
1413  	/* let the mpic know we want intrs. default affinity is 0xffffffff
1414 	 * until changed via /proc. That's how it's done on x86. If we want
1415 	 * it differently, then we should make sure we also change the default
1416 	 * values of irq_desc[].affinity in irq.c.
1417  	 */
1418 	if (distribute_irqs) {
1419 	 	for (i = 0; i < mpic->num_sources ; i++)
1420 			mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1421 				mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk);
1422 	}
1423 
1424 	/* Set current processor priority to 0 */
1425 	mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1426 
1427 	spin_unlock_irqrestore(&mpic_lock, flags);
1428 #endif /* CONFIG_SMP */
1429 }
1430 
mpic_cpu_get_priority(void)1431 int mpic_cpu_get_priority(void)
1432 {
1433 	struct mpic *mpic = mpic_primary;
1434 
1435 	return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI));
1436 }
1437 
mpic_cpu_set_priority(int prio)1438 void mpic_cpu_set_priority(int prio)
1439 {
1440 	struct mpic *mpic = mpic_primary;
1441 
1442 	prio &= MPIC_CPU_TASKPRI_MASK;
1443 	mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio);
1444 }
1445 
mpic_teardown_this_cpu(int secondary)1446 void mpic_teardown_this_cpu(int secondary)
1447 {
1448 	struct mpic *mpic = mpic_primary;
1449 	unsigned long flags;
1450 	u32 msk = 1 << hard_smp_processor_id();
1451 	unsigned int i;
1452 
1453 	BUG_ON(mpic == NULL);
1454 
1455 	DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1456 	spin_lock_irqsave(&mpic_lock, flags);
1457 
1458 	/* let the mpic know we don't want intrs.  */
1459 	for (i = 0; i < mpic->num_sources ; i++)
1460 		mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1461 			mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk);
1462 
1463 	/* Set current processor priority to max */
1464 	mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1465 	/* We need to EOI the IPI since not all platforms reset the MPIC
1466 	 * on boot and new interrupts wouldn't get delivered otherwise.
1467 	 */
1468 	mpic_eoi(mpic);
1469 
1470 	spin_unlock_irqrestore(&mpic_lock, flags);
1471 }
1472 
1473 
mpic_send_ipi(unsigned int ipi_no,unsigned int cpu_mask)1474 void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask)
1475 {
1476 	struct mpic *mpic = mpic_primary;
1477 
1478 	BUG_ON(mpic == NULL);
1479 
1480 #ifdef DEBUG_IPI
1481 	DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no);
1482 #endif
1483 
1484 	mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) +
1485 		       ipi_no * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE),
1486 		       mpic_physmask(cpu_mask & cpus_addr(cpu_online_map)[0]));
1487 }
1488 
_mpic_get_one_irq(struct mpic * mpic,int reg)1489 static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg)
1490 {
1491 	u32 src;
1492 
1493 	src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK);
1494 #ifdef DEBUG_LOW
1495 	DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src);
1496 #endif
1497 	if (unlikely(src == mpic->spurious_vec)) {
1498 		if (mpic->flags & MPIC_SPV_EOI)
1499 			mpic_eoi(mpic);
1500 		return NO_IRQ;
1501 	}
1502 	if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1503 		if (printk_ratelimit())
1504 			printk(KERN_WARNING "%s: Got protected source %d !\n",
1505 			       mpic->name, (int)src);
1506 		mpic_eoi(mpic);
1507 		return NO_IRQ;
1508 	}
1509 
1510 	return irq_linear_revmap(mpic->irqhost, src);
1511 }
1512 
mpic_get_one_irq(struct mpic * mpic)1513 unsigned int mpic_get_one_irq(struct mpic *mpic)
1514 {
1515 	return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK));
1516 }
1517 
mpic_get_irq(void)1518 unsigned int mpic_get_irq(void)
1519 {
1520 	struct mpic *mpic = mpic_primary;
1521 
1522 	BUG_ON(mpic == NULL);
1523 
1524 	return mpic_get_one_irq(mpic);
1525 }
1526 
mpic_get_mcirq(void)1527 unsigned int mpic_get_mcirq(void)
1528 {
1529 	struct mpic *mpic = mpic_primary;
1530 
1531 	BUG_ON(mpic == NULL);
1532 
1533 	return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK));
1534 }
1535 
1536 #ifdef CONFIG_SMP
mpic_request_ipis(void)1537 void mpic_request_ipis(void)
1538 {
1539 	struct mpic *mpic = mpic_primary;
1540 	int i;
1541 	BUG_ON(mpic == NULL);
1542 
1543 	printk(KERN_INFO "mpic: requesting IPIs ... \n");
1544 
1545 	for (i = 0; i < 4; i++) {
1546 		unsigned int vipi = irq_create_mapping(mpic->irqhost,
1547 						       mpic->ipi_vecs[0] + i);
1548 		if (vipi == NO_IRQ) {
1549 			printk(KERN_ERR "Failed to map %s\n", smp_ipi_name[i]);
1550 			continue;
1551 		}
1552 		smp_request_message_ipi(vipi, i);
1553 	}
1554 }
1555 
smp_mpic_message_pass(int target,int msg)1556 void smp_mpic_message_pass(int target, int msg)
1557 {
1558 	/* make sure we're sending something that translates to an IPI */
1559 	if ((unsigned int)msg > 3) {
1560 		printk("SMP %d: smp_message_pass: unknown msg %d\n",
1561 		       smp_processor_id(), msg);
1562 		return;
1563 	}
1564 	switch (target) {
1565 	case MSG_ALL:
1566 		mpic_send_ipi(msg, 0xffffffff);
1567 		break;
1568 	case MSG_ALL_BUT_SELF:
1569 		mpic_send_ipi(msg, 0xffffffff & ~(1 << smp_processor_id()));
1570 		break;
1571 	default:
1572 		mpic_send_ipi(msg, 1 << target);
1573 		break;
1574 	}
1575 }
1576 
smp_mpic_probe(void)1577 int __init smp_mpic_probe(void)
1578 {
1579 	int nr_cpus;
1580 
1581 	DBG("smp_mpic_probe()...\n");
1582 
1583 	nr_cpus = cpus_weight(cpu_possible_map);
1584 
1585 	DBG("nr_cpus: %d\n", nr_cpus);
1586 
1587 	if (nr_cpus > 1)
1588 		mpic_request_ipis();
1589 
1590 	return nr_cpus;
1591 }
1592 
smp_mpic_setup_cpu(int cpu)1593 void __devinit smp_mpic_setup_cpu(int cpu)
1594 {
1595 	mpic_setup_this_cpu();
1596 }
1597 #endif /* CONFIG_SMP */
1598 
1599 #ifdef CONFIG_PM
mpic_suspend(struct sys_device * dev,pm_message_t state)1600 static int mpic_suspend(struct sys_device *dev, pm_message_t state)
1601 {
1602 	struct mpic *mpic = container_of(dev, struct mpic, sysdev);
1603 	int i;
1604 
1605 	for (i = 0; i < mpic->num_sources; i++) {
1606 		mpic->save_data[i].vecprio =
1607 			mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI));
1608 		mpic->save_data[i].dest =
1609 			mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION));
1610 	}
1611 
1612 	return 0;
1613 }
1614 
mpic_resume(struct sys_device * dev)1615 static int mpic_resume(struct sys_device *dev)
1616 {
1617 	struct mpic *mpic = container_of(dev, struct mpic, sysdev);
1618 	int i;
1619 
1620 	for (i = 0; i < mpic->num_sources; i++) {
1621 		mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI),
1622 			       mpic->save_data[i].vecprio);
1623 		mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1624 			       mpic->save_data[i].dest);
1625 
1626 #ifdef CONFIG_MPIC_U3_HT_IRQS
1627 	{
1628 		struct mpic_irq_fixup *fixup = &mpic->fixups[i];
1629 
1630 		if (fixup->base) {
1631 			/* we use the lowest bit in an inverted meaning */
1632 			if ((mpic->save_data[i].fixup_data & 1) == 0)
1633 				continue;
1634 
1635 			/* Enable and configure */
1636 			writeb(0x10 + 2 * fixup->index, fixup->base + 2);
1637 
1638 			writel(mpic->save_data[i].fixup_data & ~1,
1639 			       fixup->base + 4);
1640 		}
1641 	}
1642 #endif
1643 	} /* end for loop */
1644 
1645 	return 0;
1646 }
1647 #endif
1648 
1649 static struct sysdev_class mpic_sysclass = {
1650 #ifdef CONFIG_PM
1651 	.resume = mpic_resume,
1652 	.suspend = mpic_suspend,
1653 #endif
1654 	.name = "mpic",
1655 };
1656 
mpic_init_sys(void)1657 static int mpic_init_sys(void)
1658 {
1659 	struct mpic *mpic = mpics;
1660 	int error, id = 0;
1661 
1662 	error = sysdev_class_register(&mpic_sysclass);
1663 
1664 	while (mpic && !error) {
1665 		mpic->sysdev.cls = &mpic_sysclass;
1666 		mpic->sysdev.id = id++;
1667 		error = sysdev_register(&mpic->sysdev);
1668 		mpic = mpic->next;
1669 	}
1670 	return error;
1671 }
1672 
1673 device_initcall(mpic_init_sys);
1674