1 /*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved.
5 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
7 *
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
13 *
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
16 * conditions are met:
17 *
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer.
21 *
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
26 *
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 * SOFTWARE.
35 */
36
37 #ifndef MLX4_H
38 #define MLX4_H
39
40 #include <linux/mutex.h>
41 #include <linux/radix-tree.h>
42 #include <linux/timer.h>
43
44 #include <linux/mlx4/device.h>
45 #include <linux/mlx4/driver.h>
46 #include <linux/mlx4/doorbell.h>
47
48 #define DRV_NAME "mlx4_core"
49 #define PFX DRV_NAME ": "
50 #define DRV_VERSION "0.01"
51 #define DRV_RELDATE "May 1, 2007"
52
53 enum {
54 MLX4_HCR_BASE = 0x80680,
55 MLX4_HCR_SIZE = 0x0001c,
56 MLX4_CLR_INT_SIZE = 0x00008
57 };
58
59 enum {
60 MLX4_MGM_ENTRY_SIZE = 0x100,
61 MLX4_QP_PER_MGM = 4 * (MLX4_MGM_ENTRY_SIZE / 16 - 2),
62 MLX4_MTT_ENTRY_PER_SEG = 8
63 };
64
65 enum {
66 MLX4_NUM_PDS = 1 << 15
67 };
68
69 enum {
70 MLX4_CMPT_TYPE_QP = 0,
71 MLX4_CMPT_TYPE_SRQ = 1,
72 MLX4_CMPT_TYPE_CQ = 2,
73 MLX4_CMPT_TYPE_EQ = 3,
74 MLX4_CMPT_NUM_TYPE
75 };
76
77 enum {
78 MLX4_CMPT_SHIFT = 24,
79 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
80 };
81
82 #ifdef CONFIG_MLX4_DEBUG
83 extern int mlx4_debug_level;
84 #else /* CONFIG_MLX4_DEBUG */
85 #define mlx4_debug_level (0)
86 #endif /* CONFIG_MLX4_DEBUG */
87
88 #define mlx4_dbg(mdev, format, arg...) \
89 do { \
90 if (mlx4_debug_level) \
91 dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ## arg); \
92 } while (0)
93
94 #define mlx4_err(mdev, format, arg...) \
95 dev_err(&mdev->pdev->dev, format, ## arg)
96 #define mlx4_info(mdev, format, arg...) \
97 dev_info(&mdev->pdev->dev, format, ## arg)
98 #define mlx4_warn(mdev, format, arg...) \
99 dev_warn(&mdev->pdev->dev, format, ## arg)
100
101 struct mlx4_bitmap {
102 u32 last;
103 u32 top;
104 u32 max;
105 u32 reserved_top;
106 u32 mask;
107 spinlock_t lock;
108 unsigned long *table;
109 };
110
111 struct mlx4_buddy {
112 unsigned long **bits;
113 unsigned int *num_free;
114 int max_order;
115 spinlock_t lock;
116 };
117
118 struct mlx4_icm;
119
120 struct mlx4_icm_table {
121 u64 virt;
122 int num_icm;
123 int num_obj;
124 int obj_size;
125 int lowmem;
126 int coherent;
127 struct mutex mutex;
128 struct mlx4_icm **icm;
129 };
130
131 struct mlx4_eq {
132 struct mlx4_dev *dev;
133 void __iomem *doorbell;
134 int eqn;
135 u32 cons_index;
136 u16 irq;
137 u16 have_irq;
138 int nent;
139 struct mlx4_buf_list *page_list;
140 struct mlx4_mtt mtt;
141 };
142
143 struct mlx4_profile {
144 int num_qp;
145 int rdmarc_per_qp;
146 int num_srq;
147 int num_cq;
148 int num_mcg;
149 int num_mpt;
150 int num_mtt;
151 };
152
153 struct mlx4_fw {
154 u64 clr_int_base;
155 u64 catas_offset;
156 struct mlx4_icm *fw_icm;
157 struct mlx4_icm *aux_icm;
158 u32 catas_size;
159 u16 fw_pages;
160 u8 clr_int_bar;
161 u8 catas_bar;
162 };
163
164 struct mlx4_cmd {
165 struct pci_pool *pool;
166 void __iomem *hcr;
167 struct mutex hcr_mutex;
168 struct semaphore poll_sem;
169 struct semaphore event_sem;
170 int max_cmds;
171 spinlock_t context_lock;
172 int free_head;
173 struct mlx4_cmd_context *context;
174 u16 token_mask;
175 u8 use_events;
176 u8 toggle;
177 };
178
179 struct mlx4_uar_table {
180 struct mlx4_bitmap bitmap;
181 };
182
183 struct mlx4_mr_table {
184 struct mlx4_bitmap mpt_bitmap;
185 struct mlx4_buddy mtt_buddy;
186 u64 mtt_base;
187 u64 mpt_base;
188 struct mlx4_icm_table mtt_table;
189 struct mlx4_icm_table dmpt_table;
190 };
191
192 struct mlx4_cq_table {
193 struct mlx4_bitmap bitmap;
194 spinlock_t lock;
195 struct radix_tree_root tree;
196 struct mlx4_icm_table table;
197 struct mlx4_icm_table cmpt_table;
198 };
199
200 struct mlx4_eq_table {
201 struct mlx4_bitmap bitmap;
202 char *irq_names;
203 void __iomem *clr_int;
204 void __iomem **uar_map;
205 u32 clr_mask;
206 struct mlx4_eq *eq;
207 u64 icm_virt;
208 struct page *icm_page;
209 dma_addr_t icm_dma;
210 struct mlx4_icm_table cmpt_table;
211 int have_irq;
212 u8 inta_pin;
213 };
214
215 struct mlx4_srq_table {
216 struct mlx4_bitmap bitmap;
217 spinlock_t lock;
218 struct radix_tree_root tree;
219 struct mlx4_icm_table table;
220 struct mlx4_icm_table cmpt_table;
221 };
222
223 struct mlx4_qp_table {
224 struct mlx4_bitmap bitmap;
225 u32 rdmarc_base;
226 int rdmarc_shift;
227 spinlock_t lock;
228 struct mlx4_icm_table qp_table;
229 struct mlx4_icm_table auxc_table;
230 struct mlx4_icm_table altc_table;
231 struct mlx4_icm_table rdmarc_table;
232 struct mlx4_icm_table cmpt_table;
233 };
234
235 struct mlx4_mcg_table {
236 struct mutex mutex;
237 struct mlx4_bitmap bitmap;
238 struct mlx4_icm_table table;
239 };
240
241 struct mlx4_catas_err {
242 u32 __iomem *map;
243 struct timer_list timer;
244 struct list_head list;
245 };
246
247 #define MLX4_MAX_MAC_NUM 128
248 #define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3)
249
250 struct mlx4_mac_table {
251 __be64 entries[MLX4_MAX_MAC_NUM];
252 int refs[MLX4_MAX_MAC_NUM];
253 struct mutex mutex;
254 int total;
255 int max;
256 };
257
258 #define MLX4_MAX_VLAN_NUM 128
259 #define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2)
260
261 struct mlx4_vlan_table {
262 __be32 entries[MLX4_MAX_VLAN_NUM];
263 int refs[MLX4_MAX_VLAN_NUM];
264 struct mutex mutex;
265 int total;
266 int max;
267 };
268
269 struct mlx4_port_info {
270 struct mlx4_dev *dev;
271 int port;
272 char dev_name[16];
273 struct device_attribute port_attr;
274 enum mlx4_port_type tmp_type;
275 struct mlx4_mac_table mac_table;
276 struct mlx4_vlan_table vlan_table;
277 };
278
279 struct mlx4_priv {
280 struct mlx4_dev dev;
281
282 struct list_head dev_list;
283 struct list_head ctx_list;
284 spinlock_t ctx_lock;
285
286 struct list_head pgdir_list;
287 struct mutex pgdir_mutex;
288
289 struct mlx4_fw fw;
290 struct mlx4_cmd cmd;
291
292 struct mlx4_bitmap pd_bitmap;
293 struct mlx4_uar_table uar_table;
294 struct mlx4_mr_table mr_table;
295 struct mlx4_cq_table cq_table;
296 struct mlx4_eq_table eq_table;
297 struct mlx4_srq_table srq_table;
298 struct mlx4_qp_table qp_table;
299 struct mlx4_mcg_table mcg_table;
300
301 struct mlx4_catas_err catas_err;
302
303 void __iomem *clr_base;
304
305 struct mlx4_uar driver_uar;
306 void __iomem *kar;
307 struct mlx4_port_info port[MLX4_MAX_PORTS + 1];
308 struct mutex port_mutex;
309 };
310
mlx4_priv(struct mlx4_dev * dev)311 static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
312 {
313 return container_of(dev, struct mlx4_priv, dev);
314 }
315
316 u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
317 void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj);
318 u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, int align);
319 void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt);
320 int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask,
321 u32 reserved_bot, u32 resetrved_top);
322 void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);
323
324 int mlx4_reset(struct mlx4_dev *dev);
325
326 int mlx4_alloc_eq_table(struct mlx4_dev *dev);
327 void mlx4_free_eq_table(struct mlx4_dev *dev);
328
329 int mlx4_init_pd_table(struct mlx4_dev *dev);
330 int mlx4_init_uar_table(struct mlx4_dev *dev);
331 int mlx4_init_mr_table(struct mlx4_dev *dev);
332 int mlx4_init_eq_table(struct mlx4_dev *dev);
333 int mlx4_init_cq_table(struct mlx4_dev *dev);
334 int mlx4_init_qp_table(struct mlx4_dev *dev);
335 int mlx4_init_srq_table(struct mlx4_dev *dev);
336 int mlx4_init_mcg_table(struct mlx4_dev *dev);
337
338 void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
339 void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
340 void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
341 void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
342 void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
343 void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
344 void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
345 void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
346
347 void mlx4_start_catas_poll(struct mlx4_dev *dev);
348 void mlx4_stop_catas_poll(struct mlx4_dev *dev);
349 int mlx4_catas_init(void);
350 void mlx4_catas_cleanup(void);
351 int mlx4_restart_one(struct pci_dev *pdev);
352 int mlx4_register_device(struct mlx4_dev *dev);
353 void mlx4_unregister_device(struct mlx4_dev *dev);
354 void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type, int port);
355
356 struct mlx4_dev_cap;
357 struct mlx4_init_hca_param;
358
359 u64 mlx4_make_profile(struct mlx4_dev *dev,
360 struct mlx4_profile *request,
361 struct mlx4_dev_cap *dev_cap,
362 struct mlx4_init_hca_param *init_hca);
363
364 int mlx4_map_eq_icm(struct mlx4_dev *dev, u64 icm_virt);
365 void mlx4_unmap_eq_icm(struct mlx4_dev *dev);
366
367 int mlx4_cmd_init(struct mlx4_dev *dev);
368 void mlx4_cmd_cleanup(struct mlx4_dev *dev);
369 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
370 int mlx4_cmd_use_events(struct mlx4_dev *dev);
371 void mlx4_cmd_use_polling(struct mlx4_dev *dev);
372
373 void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
374 void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);
375
376 void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);
377
378 void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);
379
380 void mlx4_handle_catas_err(struct mlx4_dev *dev);
381
382 void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table);
383 void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table);
384
385 int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port);
386 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps);
387
388 #endif /* MLX4_H */
389