1 /*
2 * MUSB OTG driver core code
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35 /*
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
37 *
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
42 *
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
47 *
48 *
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
53 *
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
56 *
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
61 *
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
66 * each direction.
67 *
68 * RESULT: one device may be perceived as blocking another one.
69 *
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
74 *
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
80 */
81
82 /*
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific informarion
87 * (plus recentrly, SOC or family details)
88 *
89 * Most of the conditional compilation will (someday) vanish.
90 */
91
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/init.h>
97 #include <linux/list.h>
98 #include <linux/kobject.h>
99 #include <linux/platform_device.h>
100 #include <linux/io.h>
101
102 #ifdef CONFIG_ARM
103 #include <mach/hardware.h>
104 #include <mach/memory.h>
105 #include <asm/mach-types.h>
106 #endif
107
108 #include "musb_core.h"
109
110
111 #ifdef CONFIG_ARCH_DAVINCI
112 #include "davinci.h"
113 #endif
114
115
116
117 unsigned musb_debug;
118 module_param_named(debug, musb_debug, uint, S_IRUGO | S_IWUSR);
119 MODULE_PARM_DESC(debug, "Debug message level. Default = 0");
120
121 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
122 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
123
124 #define MUSB_VERSION "6.0"
125
126 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
127
128 #define MUSB_DRIVER_NAME "musb_hdrc"
129 const char musb_driver_name[] = MUSB_DRIVER_NAME;
130
131 MODULE_DESCRIPTION(DRIVER_INFO);
132 MODULE_AUTHOR(DRIVER_AUTHOR);
133 MODULE_LICENSE("GPL");
134 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
135
136
137 /*-------------------------------------------------------------------------*/
138
dev_to_musb(struct device * dev)139 static inline struct musb *dev_to_musb(struct device *dev)
140 {
141 #ifdef CONFIG_USB_MUSB_HDRC_HCD
142 /* usbcore insists dev->driver_data is a "struct hcd *" */
143 return hcd_to_musb(dev_get_drvdata(dev));
144 #else
145 return dev_get_drvdata(dev);
146 #endif
147 }
148
149 /*-------------------------------------------------------------------------*/
150
151 #if !defined(CONFIG_USB_TUSB6010) && !defined(CONFIG_BLACKFIN)
152
153 /*
154 * Load an endpoint's FIFO
155 */
musb_write_fifo(struct musb_hw_ep * hw_ep,u16 len,const u8 * src)156 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
157 {
158 void __iomem *fifo = hw_ep->fifo;
159
160 prefetch((u8 *)src);
161
162 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
163 'T', hw_ep->epnum, fifo, len, src);
164
165 /* we can't assume unaligned reads work */
166 if (likely((0x01 & (unsigned long) src) == 0)) {
167 u16 index = 0;
168
169 /* best case is 32bit-aligned source address */
170 if ((0x02 & (unsigned long) src) == 0) {
171 if (len >= 4) {
172 writesl(fifo, src + index, len >> 2);
173 index += len & ~0x03;
174 }
175 if (len & 0x02) {
176 musb_writew(fifo, 0, *(u16 *)&src[index]);
177 index += 2;
178 }
179 } else {
180 if (len >= 2) {
181 writesw(fifo, src + index, len >> 1);
182 index += len & ~0x01;
183 }
184 }
185 if (len & 0x01)
186 musb_writeb(fifo, 0, src[index]);
187 } else {
188 /* byte aligned */
189 writesb(fifo, src, len);
190 }
191 }
192
193 /*
194 * Unload an endpoint's FIFO
195 */
musb_read_fifo(struct musb_hw_ep * hw_ep,u16 len,u8 * dst)196 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
197 {
198 void __iomem *fifo = hw_ep->fifo;
199
200 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
201 'R', hw_ep->epnum, fifo, len, dst);
202
203 /* we can't assume unaligned writes work */
204 if (likely((0x01 & (unsigned long) dst) == 0)) {
205 u16 index = 0;
206
207 /* best case is 32bit-aligned destination address */
208 if ((0x02 & (unsigned long) dst) == 0) {
209 if (len >= 4) {
210 readsl(fifo, dst, len >> 2);
211 index = len & ~0x03;
212 }
213 if (len & 0x02) {
214 *(u16 *)&dst[index] = musb_readw(fifo, 0);
215 index += 2;
216 }
217 } else {
218 if (len >= 2) {
219 readsw(fifo, dst, len >> 1);
220 index = len & ~0x01;
221 }
222 }
223 if (len & 0x01)
224 dst[index] = musb_readb(fifo, 0);
225 } else {
226 /* byte aligned */
227 readsb(fifo, dst, len);
228 }
229 }
230
231 #endif /* normal PIO */
232
233
234 /*-------------------------------------------------------------------------*/
235
236 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
237 static const u8 musb_test_packet[53] = {
238 /* implicit SYNC then DATA0 to start */
239
240 /* JKJKJKJK x9 */
241 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
242 /* JJKKJJKK x8 */
243 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
244 /* JJJJKKKK x8 */
245 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
246 /* JJJJJJJKKKKKKK x8 */
247 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
248 /* JJJJJJJK x8 */
249 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
250 /* JKKKKKKK x10, JK */
251 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
252
253 /* implicit CRC16 then EOP to end */
254 };
255
musb_load_testpacket(struct musb * musb)256 void musb_load_testpacket(struct musb *musb)
257 {
258 void __iomem *regs = musb->endpoints[0].regs;
259
260 musb_ep_select(musb->mregs, 0);
261 musb_write_fifo(musb->control_ep,
262 sizeof(musb_test_packet), musb_test_packet);
263 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
264 }
265
266 /*-------------------------------------------------------------------------*/
267
otg_state_string(struct musb * musb)268 const char *otg_state_string(struct musb *musb)
269 {
270 switch (musb->xceiv.state) {
271 case OTG_STATE_A_IDLE: return "a_idle";
272 case OTG_STATE_A_WAIT_VRISE: return "a_wait_vrise";
273 case OTG_STATE_A_WAIT_BCON: return "a_wait_bcon";
274 case OTG_STATE_A_HOST: return "a_host";
275 case OTG_STATE_A_SUSPEND: return "a_suspend";
276 case OTG_STATE_A_PERIPHERAL: return "a_peripheral";
277 case OTG_STATE_A_WAIT_VFALL: return "a_wait_vfall";
278 case OTG_STATE_A_VBUS_ERR: return "a_vbus_err";
279 case OTG_STATE_B_IDLE: return "b_idle";
280 case OTG_STATE_B_SRP_INIT: return "b_srp_init";
281 case OTG_STATE_B_PERIPHERAL: return "b_peripheral";
282 case OTG_STATE_B_WAIT_ACON: return "b_wait_acon";
283 case OTG_STATE_B_HOST: return "b_host";
284 default: return "UNDEFINED";
285 }
286 }
287
288 #ifdef CONFIG_USB_MUSB_OTG
289
290 /*
291 * See also USB_OTG_1-3.pdf 6.6.5 Timers
292 * REVISIT: Are the other timers done in the hardware?
293 */
294 #define TB_ASE0_BRST 100 /* Min 3.125 ms */
295
296 /*
297 * Handles OTG hnp timeouts, such as b_ase0_brst
298 */
musb_otg_timer_func(unsigned long data)299 void musb_otg_timer_func(unsigned long data)
300 {
301 struct musb *musb = (struct musb *)data;
302 unsigned long flags;
303
304 spin_lock_irqsave(&musb->lock, flags);
305 switch (musb->xceiv.state) {
306 case OTG_STATE_B_WAIT_ACON:
307 DBG(1, "HNP: b_wait_acon timeout; back to b_peripheral\n");
308 musb_g_disconnect(musb);
309 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
310 musb->is_active = 0;
311 break;
312 case OTG_STATE_A_WAIT_BCON:
313 DBG(1, "HNP: a_wait_bcon timeout; back to a_host\n");
314 musb_hnp_stop(musb);
315 break;
316 default:
317 DBG(1, "HNP: Unhandled mode %s\n", otg_state_string(musb));
318 }
319 musb->ignore_disconnect = 0;
320 spin_unlock_irqrestore(&musb->lock, flags);
321 }
322
323 static DEFINE_TIMER(musb_otg_timer, musb_otg_timer_func, 0, 0);
324
325 /*
326 * Stops the B-device HNP state. Caller must take care of locking.
327 */
musb_hnp_stop(struct musb * musb)328 void musb_hnp_stop(struct musb *musb)
329 {
330 struct usb_hcd *hcd = musb_to_hcd(musb);
331 void __iomem *mbase = musb->mregs;
332 u8 reg;
333
334 switch (musb->xceiv.state) {
335 case OTG_STATE_A_PERIPHERAL:
336 case OTG_STATE_A_WAIT_VFALL:
337 case OTG_STATE_A_WAIT_BCON:
338 DBG(1, "HNP: Switching back to A-host\n");
339 musb_g_disconnect(musb);
340 musb->xceiv.state = OTG_STATE_A_IDLE;
341 MUSB_HST_MODE(musb);
342 musb->is_active = 0;
343 break;
344 case OTG_STATE_B_HOST:
345 DBG(1, "HNP: Disabling HR\n");
346 hcd->self.is_b_host = 0;
347 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
348 MUSB_DEV_MODE(musb);
349 reg = musb_readb(mbase, MUSB_POWER);
350 reg |= MUSB_POWER_SUSPENDM;
351 musb_writeb(mbase, MUSB_POWER, reg);
352 /* REVISIT: Start SESSION_REQUEST here? */
353 break;
354 default:
355 DBG(1, "HNP: Stopping in unknown state %s\n",
356 otg_state_string(musb));
357 }
358
359 /*
360 * When returning to A state after HNP, avoid hub_port_rebounce(),
361 * which cause occasional OPT A "Did not receive reset after connect"
362 * errors.
363 */
364 musb->port1_status &=
365 ~(1 << USB_PORT_FEAT_C_CONNECTION);
366 }
367
368 #endif
369
370 /*
371 * Interrupt Service Routine to record USB "global" interrupts.
372 * Since these do not happen often and signify things of
373 * paramount importance, it seems OK to check them individually;
374 * the order of the tests is specified in the manual
375 *
376 * @param musb instance pointer
377 * @param int_usb register contents
378 * @param devctl
379 * @param power
380 */
381
382 #define STAGE0_MASK (MUSB_INTR_RESUME | MUSB_INTR_SESSREQ \
383 | MUSB_INTR_VBUSERROR | MUSB_INTR_CONNECT \
384 | MUSB_INTR_RESET)
385
musb_stage0_irq(struct musb * musb,u8 int_usb,u8 devctl,u8 power)386 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
387 u8 devctl, u8 power)
388 {
389 irqreturn_t handled = IRQ_NONE;
390 void __iomem *mbase = musb->mregs;
391
392 DBG(3, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl,
393 int_usb);
394
395 /* in host mode, the peripheral may issue remote wakeup.
396 * in peripheral mode, the host may resume the link.
397 * spurious RESUME irqs happen too, paired with SUSPEND.
398 */
399 if (int_usb & MUSB_INTR_RESUME) {
400 handled = IRQ_HANDLED;
401 DBG(3, "RESUME (%s)\n", otg_state_string(musb));
402
403 if (devctl & MUSB_DEVCTL_HM) {
404 #ifdef CONFIG_USB_MUSB_HDRC_HCD
405 switch (musb->xceiv.state) {
406 case OTG_STATE_A_SUSPEND:
407 /* remote wakeup? later, GetPortStatus
408 * will stop RESUME signaling
409 */
410
411 if (power & MUSB_POWER_SUSPENDM) {
412 /* spurious */
413 musb->int_usb &= ~MUSB_INTR_SUSPEND;
414 DBG(2, "Spurious SUSPENDM\n");
415 break;
416 }
417
418 power &= ~MUSB_POWER_SUSPENDM;
419 musb_writeb(mbase, MUSB_POWER,
420 power | MUSB_POWER_RESUME);
421
422 musb->port1_status |=
423 (USB_PORT_STAT_C_SUSPEND << 16)
424 | MUSB_PORT_STAT_RESUME;
425 musb->rh_timer = jiffies
426 + msecs_to_jiffies(20);
427
428 musb->xceiv.state = OTG_STATE_A_HOST;
429 musb->is_active = 1;
430 usb_hcd_resume_root_hub(musb_to_hcd(musb));
431 break;
432 case OTG_STATE_B_WAIT_ACON:
433 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
434 musb->is_active = 1;
435 MUSB_DEV_MODE(musb);
436 break;
437 default:
438 WARNING("bogus %s RESUME (%s)\n",
439 "host",
440 otg_state_string(musb));
441 }
442 #endif
443 } else {
444 switch (musb->xceiv.state) {
445 #ifdef CONFIG_USB_MUSB_HDRC_HCD
446 case OTG_STATE_A_SUSPEND:
447 /* possibly DISCONNECT is upcoming */
448 musb->xceiv.state = OTG_STATE_A_HOST;
449 usb_hcd_resume_root_hub(musb_to_hcd(musb));
450 break;
451 #endif
452 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
453 case OTG_STATE_B_WAIT_ACON:
454 case OTG_STATE_B_PERIPHERAL:
455 /* disconnect while suspended? we may
456 * not get a disconnect irq...
457 */
458 if ((devctl & MUSB_DEVCTL_VBUS)
459 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
460 ) {
461 musb->int_usb |= MUSB_INTR_DISCONNECT;
462 musb->int_usb &= ~MUSB_INTR_SUSPEND;
463 break;
464 }
465 musb_g_resume(musb);
466 break;
467 case OTG_STATE_B_IDLE:
468 musb->int_usb &= ~MUSB_INTR_SUSPEND;
469 break;
470 #endif
471 default:
472 WARNING("bogus %s RESUME (%s)\n",
473 "peripheral",
474 otg_state_string(musb));
475 }
476 }
477 }
478
479 #ifdef CONFIG_USB_MUSB_HDRC_HCD
480 /* see manual for the order of the tests */
481 if (int_usb & MUSB_INTR_SESSREQ) {
482 DBG(1, "SESSION_REQUEST (%s)\n", otg_state_string(musb));
483
484 /* IRQ arrives from ID pin sense or (later, if VBUS power
485 * is removed) SRP. responses are time critical:
486 * - turn on VBUS (with silicon-specific mechanism)
487 * - go through A_WAIT_VRISE
488 * - ... to A_WAIT_BCON.
489 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
490 */
491 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
492 musb->ep0_stage = MUSB_EP0_START;
493 musb->xceiv.state = OTG_STATE_A_IDLE;
494 MUSB_HST_MODE(musb);
495 musb_set_vbus(musb, 1);
496
497 handled = IRQ_HANDLED;
498 }
499
500 if (int_usb & MUSB_INTR_VBUSERROR) {
501 int ignore = 0;
502
503 /* During connection as an A-Device, we may see a short
504 * current spikes causing voltage drop, because of cable
505 * and peripheral capacitance combined with vbus draw.
506 * (So: less common with truly self-powered devices, where
507 * vbus doesn't act like a power supply.)
508 *
509 * Such spikes are short; usually less than ~500 usec, max
510 * of ~2 msec. That is, they're not sustained overcurrent
511 * errors, though they're reported using VBUSERROR irqs.
512 *
513 * Workarounds: (a) hardware: use self powered devices.
514 * (b) software: ignore non-repeated VBUS errors.
515 *
516 * REVISIT: do delays from lots of DEBUG_KERNEL checks
517 * make trouble here, keeping VBUS < 4.4V ?
518 */
519 switch (musb->xceiv.state) {
520 case OTG_STATE_A_HOST:
521 /* recovery is dicey once we've gotten past the
522 * initial stages of enumeration, but if VBUS
523 * stayed ok at the other end of the link, and
524 * another reset is due (at least for high speed,
525 * to redo the chirp etc), it might work OK...
526 */
527 case OTG_STATE_A_WAIT_BCON:
528 case OTG_STATE_A_WAIT_VRISE:
529 if (musb->vbuserr_retry) {
530 musb->vbuserr_retry--;
531 ignore = 1;
532 devctl |= MUSB_DEVCTL_SESSION;
533 musb_writeb(mbase, MUSB_DEVCTL, devctl);
534 } else {
535 musb->port1_status |=
536 (1 << USB_PORT_FEAT_OVER_CURRENT)
537 | (1 << USB_PORT_FEAT_C_OVER_CURRENT);
538 }
539 break;
540 default:
541 break;
542 }
543
544 DBG(1, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
545 otg_state_string(musb),
546 devctl,
547 ({ char *s;
548 switch (devctl & MUSB_DEVCTL_VBUS) {
549 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
550 s = "<SessEnd"; break;
551 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
552 s = "<AValid"; break;
553 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
554 s = "<VBusValid"; break;
555 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
556 default:
557 s = "VALID"; break;
558 }; s; }),
559 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
560 musb->port1_status);
561
562 /* go through A_WAIT_VFALL then start a new session */
563 if (!ignore)
564 musb_set_vbus(musb, 0);
565 handled = IRQ_HANDLED;
566 }
567
568 if (int_usb & MUSB_INTR_CONNECT) {
569 struct usb_hcd *hcd = musb_to_hcd(musb);
570
571 handled = IRQ_HANDLED;
572 musb->is_active = 1;
573 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
574
575 musb->ep0_stage = MUSB_EP0_START;
576
577 #ifdef CONFIG_USB_MUSB_OTG
578 /* flush endpoints when transitioning from Device Mode */
579 if (is_peripheral_active(musb)) {
580 /* REVISIT HNP; just force disconnect */
581 }
582 musb_writew(mbase, MUSB_INTRTXE, musb->epmask);
583 musb_writew(mbase, MUSB_INTRRXE, musb->epmask & 0xfffe);
584 musb_writeb(mbase, MUSB_INTRUSBE, 0xf7);
585 #endif
586 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
587 |USB_PORT_STAT_HIGH_SPEED
588 |USB_PORT_STAT_ENABLE
589 );
590 musb->port1_status |= USB_PORT_STAT_CONNECTION
591 |(USB_PORT_STAT_C_CONNECTION << 16);
592
593 /* high vs full speed is just a guess until after reset */
594 if (devctl & MUSB_DEVCTL_LSDEV)
595 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
596
597 if (hcd->status_urb)
598 usb_hcd_poll_rh_status(hcd);
599 else
600 usb_hcd_resume_root_hub(hcd);
601
602 MUSB_HST_MODE(musb);
603
604 /* indicate new connection to OTG machine */
605 switch (musb->xceiv.state) {
606 case OTG_STATE_B_PERIPHERAL:
607 if (int_usb & MUSB_INTR_SUSPEND) {
608 DBG(1, "HNP: SUSPEND+CONNECT, now b_host\n");
609 musb->xceiv.state = OTG_STATE_B_HOST;
610 hcd->self.is_b_host = 1;
611 int_usb &= ~MUSB_INTR_SUSPEND;
612 } else
613 DBG(1, "CONNECT as b_peripheral???\n");
614 break;
615 case OTG_STATE_B_WAIT_ACON:
616 DBG(1, "HNP: Waiting to switch to b_host state\n");
617 musb->xceiv.state = OTG_STATE_B_HOST;
618 hcd->self.is_b_host = 1;
619 break;
620 default:
621 if ((devctl & MUSB_DEVCTL_VBUS)
622 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
623 musb->xceiv.state = OTG_STATE_A_HOST;
624 hcd->self.is_b_host = 0;
625 }
626 break;
627 }
628 DBG(1, "CONNECT (%s) devctl %02x\n",
629 otg_state_string(musb), devctl);
630 }
631 #endif /* CONFIG_USB_MUSB_HDRC_HCD */
632
633 /* mentor saves a bit: bus reset and babble share the same irq.
634 * only host sees babble; only peripheral sees bus reset.
635 */
636 if (int_usb & MUSB_INTR_RESET) {
637 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) {
638 /*
639 * Looks like non-HS BABBLE can be ignored, but
640 * HS BABBLE is an error condition. For HS the solution
641 * is to avoid babble in the first place and fix what
642 * caused BABBLE. When HS BABBLE happens we can only
643 * stop the session.
644 */
645 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
646 DBG(1, "BABBLE devctl: %02x\n", devctl);
647 else {
648 ERR("Stopping host session -- babble\n");
649 musb_writeb(mbase, MUSB_DEVCTL, 0);
650 }
651 } else if (is_peripheral_capable()) {
652 DBG(1, "BUS RESET as %s\n", otg_state_string(musb));
653 switch (musb->xceiv.state) {
654 #ifdef CONFIG_USB_OTG
655 case OTG_STATE_A_SUSPEND:
656 /* We need to ignore disconnect on suspend
657 * otherwise tusb 2.0 won't reconnect after a
658 * power cycle, which breaks otg compliance.
659 */
660 musb->ignore_disconnect = 1;
661 musb_g_reset(musb);
662 /* FALLTHROUGH */
663 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
664 DBG(1, "HNP: Setting timer as %s\n",
665 otg_state_string(musb));
666 musb_otg_timer.data = (unsigned long)musb;
667 mod_timer(&musb_otg_timer, jiffies
668 + msecs_to_jiffies(100));
669 break;
670 case OTG_STATE_A_PERIPHERAL:
671 musb_hnp_stop(musb);
672 break;
673 case OTG_STATE_B_WAIT_ACON:
674 DBG(1, "HNP: RESET (%s), to b_peripheral\n",
675 otg_state_string(musb));
676 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
677 musb_g_reset(musb);
678 break;
679 #endif
680 case OTG_STATE_B_IDLE:
681 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
682 /* FALLTHROUGH */
683 case OTG_STATE_B_PERIPHERAL:
684 musb_g_reset(musb);
685 break;
686 default:
687 DBG(1, "Unhandled BUS RESET as %s\n",
688 otg_state_string(musb));
689 }
690 }
691
692 handled = IRQ_HANDLED;
693 }
694 schedule_work(&musb->irq_work);
695
696 return handled;
697 }
698
699 /*
700 * Interrupt Service Routine to record USB "global" interrupts.
701 * Since these do not happen often and signify things of
702 * paramount importance, it seems OK to check them individually;
703 * the order of the tests is specified in the manual
704 *
705 * @param musb instance pointer
706 * @param int_usb register contents
707 * @param devctl
708 * @param power
709 */
musb_stage2_irq(struct musb * musb,u8 int_usb,u8 devctl,u8 power)710 static irqreturn_t musb_stage2_irq(struct musb *musb, u8 int_usb,
711 u8 devctl, u8 power)
712 {
713 irqreturn_t handled = IRQ_NONE;
714
715 #if 0
716 /* REVISIT ... this would be for multiplexing periodic endpoints, or
717 * supporting transfer phasing to prevent exceeding ISO bandwidth
718 * limits of a given frame or microframe.
719 *
720 * It's not needed for peripheral side, which dedicates endpoints;
721 * though it _might_ use SOF irqs for other purposes.
722 *
723 * And it's not currently needed for host side, which also dedicates
724 * endpoints, relies on TX/RX interval registers, and isn't claimed
725 * to support ISO transfers yet.
726 */
727 if (int_usb & MUSB_INTR_SOF) {
728 void __iomem *mbase = musb->mregs;
729 struct musb_hw_ep *ep;
730 u8 epnum;
731 u16 frame;
732
733 DBG(6, "START_OF_FRAME\n");
734 handled = IRQ_HANDLED;
735
736 /* start any periodic Tx transfers waiting for current frame */
737 frame = musb_readw(mbase, MUSB_FRAME);
738 ep = musb->endpoints;
739 for (epnum = 1; (epnum < musb->nr_endpoints)
740 && (musb->epmask >= (1 << epnum));
741 epnum++, ep++) {
742 /*
743 * FIXME handle framecounter wraps (12 bits)
744 * eliminate duplicated StartUrb logic
745 */
746 if (ep->dwWaitFrame >= frame) {
747 ep->dwWaitFrame = 0;
748 pr_debug("SOF --> periodic TX%s on %d\n",
749 ep->tx_channel ? " DMA" : "",
750 epnum);
751 if (!ep->tx_channel)
752 musb_h_tx_start(musb, epnum);
753 else
754 cppi_hostdma_start(musb, epnum);
755 }
756 } /* end of for loop */
757 }
758 #endif
759
760 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
761 DBG(1, "DISCONNECT (%s) as %s, devctl %02x\n",
762 otg_state_string(musb),
763 MUSB_MODE(musb), devctl);
764 handled = IRQ_HANDLED;
765
766 switch (musb->xceiv.state) {
767 #ifdef CONFIG_USB_MUSB_HDRC_HCD
768 case OTG_STATE_A_HOST:
769 case OTG_STATE_A_SUSPEND:
770 usb_hcd_resume_root_hub(musb_to_hcd(musb));
771 musb_root_disconnect(musb);
772 if (musb->a_wait_bcon != 0)
773 musb_platform_try_idle(musb, jiffies
774 + msecs_to_jiffies(musb->a_wait_bcon));
775 break;
776 #endif /* HOST */
777 #ifdef CONFIG_USB_MUSB_OTG
778 case OTG_STATE_B_HOST:
779 musb_hnp_stop(musb);
780 break;
781 case OTG_STATE_A_PERIPHERAL:
782 musb_hnp_stop(musb);
783 musb_root_disconnect(musb);
784 /* FALLTHROUGH */
785 case OTG_STATE_B_WAIT_ACON:
786 /* FALLTHROUGH */
787 #endif /* OTG */
788 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
789 case OTG_STATE_B_PERIPHERAL:
790 case OTG_STATE_B_IDLE:
791 musb_g_disconnect(musb);
792 break;
793 #endif /* GADGET */
794 default:
795 WARNING("unhandled DISCONNECT transition (%s)\n",
796 otg_state_string(musb));
797 break;
798 }
799
800 schedule_work(&musb->irq_work);
801 }
802
803 if (int_usb & MUSB_INTR_SUSPEND) {
804 DBG(1, "SUSPEND (%s) devctl %02x power %02x\n",
805 otg_state_string(musb), devctl, power);
806 handled = IRQ_HANDLED;
807
808 switch (musb->xceiv.state) {
809 #ifdef CONFIG_USB_MUSB_OTG
810 case OTG_STATE_A_PERIPHERAL:
811 /*
812 * We cannot stop HNP here, devctl BDEVICE might be
813 * still set.
814 */
815 break;
816 #endif
817 case OTG_STATE_B_PERIPHERAL:
818 musb_g_suspend(musb);
819 musb->is_active = is_otg_enabled(musb)
820 && musb->xceiv.gadget->b_hnp_enable;
821 if (musb->is_active) {
822 #ifdef CONFIG_USB_MUSB_OTG
823 musb->xceiv.state = OTG_STATE_B_WAIT_ACON;
824 DBG(1, "HNP: Setting timer for b_ase0_brst\n");
825 musb_otg_timer.data = (unsigned long)musb;
826 mod_timer(&musb_otg_timer, jiffies
827 + msecs_to_jiffies(TB_ASE0_BRST));
828 #endif
829 }
830 break;
831 case OTG_STATE_A_WAIT_BCON:
832 if (musb->a_wait_bcon != 0)
833 musb_platform_try_idle(musb, jiffies
834 + msecs_to_jiffies(musb->a_wait_bcon));
835 break;
836 case OTG_STATE_A_HOST:
837 musb->xceiv.state = OTG_STATE_A_SUSPEND;
838 musb->is_active = is_otg_enabled(musb)
839 && musb->xceiv.host->b_hnp_enable;
840 break;
841 case OTG_STATE_B_HOST:
842 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
843 DBG(1, "REVISIT: SUSPEND as B_HOST\n");
844 break;
845 default:
846 /* "should not happen" */
847 musb->is_active = 0;
848 break;
849 }
850 schedule_work(&musb->irq_work);
851 }
852
853
854 return handled;
855 }
856
857 /*-------------------------------------------------------------------------*/
858
859 /*
860 * Program the HDRC to start (enable interrupts, dma, etc.).
861 */
musb_start(struct musb * musb)862 void musb_start(struct musb *musb)
863 {
864 void __iomem *regs = musb->mregs;
865 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
866
867 DBG(2, "<== devctl %02x\n", devctl);
868
869 /* Set INT enable registers, enable interrupts */
870 musb_writew(regs, MUSB_INTRTXE, musb->epmask);
871 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe);
872 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
873
874 musb_writeb(regs, MUSB_TESTMODE, 0);
875
876 /* put into basic highspeed mode and start session */
877 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
878 | MUSB_POWER_SOFTCONN
879 | MUSB_POWER_HSENAB
880 /* ENSUSPEND wedges tusb */
881 /* | MUSB_POWER_ENSUSPEND */
882 );
883
884 musb->is_active = 0;
885 devctl = musb_readb(regs, MUSB_DEVCTL);
886 devctl &= ~MUSB_DEVCTL_SESSION;
887
888 if (is_otg_enabled(musb)) {
889 /* session started after:
890 * (a) ID-grounded irq, host mode;
891 * (b) vbus present/connect IRQ, peripheral mode;
892 * (c) peripheral initiates, using SRP
893 */
894 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
895 musb->is_active = 1;
896 else
897 devctl |= MUSB_DEVCTL_SESSION;
898
899 } else if (is_host_enabled(musb)) {
900 /* assume ID pin is hard-wired to ground */
901 devctl |= MUSB_DEVCTL_SESSION;
902
903 } else /* peripheral is enabled */ {
904 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
905 musb->is_active = 1;
906 }
907 musb_platform_enable(musb);
908 musb_writeb(regs, MUSB_DEVCTL, devctl);
909 }
910
911
musb_generic_disable(struct musb * musb)912 static void musb_generic_disable(struct musb *musb)
913 {
914 void __iomem *mbase = musb->mregs;
915 u16 temp;
916
917 /* disable interrupts */
918 musb_writeb(mbase, MUSB_INTRUSBE, 0);
919 musb_writew(mbase, MUSB_INTRTXE, 0);
920 musb_writew(mbase, MUSB_INTRRXE, 0);
921
922 /* off */
923 musb_writeb(mbase, MUSB_DEVCTL, 0);
924
925 /* flush pending interrupts */
926 temp = musb_readb(mbase, MUSB_INTRUSB);
927 temp = musb_readw(mbase, MUSB_INTRTX);
928 temp = musb_readw(mbase, MUSB_INTRRX);
929
930 }
931
932 /*
933 * Make the HDRC stop (disable interrupts, etc.);
934 * reversible by musb_start
935 * called on gadget driver unregister
936 * with controller locked, irqs blocked
937 * acts as a NOP unless some role activated the hardware
938 */
musb_stop(struct musb * musb)939 void musb_stop(struct musb *musb)
940 {
941 /* stop IRQs, timers, ... */
942 musb_platform_disable(musb);
943 musb_generic_disable(musb);
944 DBG(3, "HDRC disabled\n");
945
946 /* FIXME
947 * - mark host and/or peripheral drivers unusable/inactive
948 * - disable DMA (and enable it in HdrcStart)
949 * - make sure we can musb_start() after musb_stop(); with
950 * OTG mode, gadget driver module rmmod/modprobe cycles that
951 * - ...
952 */
953 musb_platform_try_idle(musb, 0);
954 }
955
musb_shutdown(struct platform_device * pdev)956 static void musb_shutdown(struct platform_device *pdev)
957 {
958 struct musb *musb = dev_to_musb(&pdev->dev);
959 unsigned long flags;
960
961 spin_lock_irqsave(&musb->lock, flags);
962 musb_platform_disable(musb);
963 musb_generic_disable(musb);
964 if (musb->clock) {
965 clk_put(musb->clock);
966 musb->clock = NULL;
967 }
968 spin_unlock_irqrestore(&musb->lock, flags);
969
970 /* FIXME power down */
971 }
972
973
974 /*-------------------------------------------------------------------------*/
975
976 /*
977 * The silicon either has hard-wired endpoint configurations, or else
978 * "dynamic fifo" sizing. The driver has support for both, though at this
979 * writing only the dynamic sizing is very well tested. Since we switched
980 * away from compile-time hardware parameters, we can no longer rely on
981 * dead code elimination to leave only the relevant one in the object file.
982 *
983 * We don't currently use dynamic fifo setup capability to do anything
984 * more than selecting one of a bunch of predefined configurations.
985 */
986 #if defined(CONFIG_USB_TUSB6010) || \
987 defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX)
988 static ushort __initdata fifo_mode = 4;
989 #else
990 static ushort __initdata fifo_mode = 2;
991 #endif
992
993 /* "modprobe ... fifo_mode=1" etc */
994 module_param(fifo_mode, ushort, 0);
995 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
996
997
998 enum fifo_style { FIFO_RXTX, FIFO_TX, FIFO_RX } __attribute__ ((packed));
999 enum buf_mode { BUF_SINGLE, BUF_DOUBLE } __attribute__ ((packed));
1000
1001 struct fifo_cfg {
1002 u8 hw_ep_num;
1003 enum fifo_style style;
1004 enum buf_mode mode;
1005 u16 maxpacket;
1006 };
1007
1008 /*
1009 * tables defining fifo_mode values. define more if you like.
1010 * for host side, make sure both halves of ep1 are set up.
1011 */
1012
1013 /* mode 0 - fits in 2KB */
1014 static struct fifo_cfg __initdata mode_0_cfg[] = {
1015 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1016 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1017 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1018 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1019 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1020 };
1021
1022 /* mode 1 - fits in 4KB */
1023 static struct fifo_cfg __initdata mode_1_cfg[] = {
1024 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1025 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1026 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1027 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1028 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1029 };
1030
1031 /* mode 2 - fits in 4KB */
1032 static struct fifo_cfg __initdata mode_2_cfg[] = {
1033 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1034 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1035 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1036 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1037 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1038 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1039 };
1040
1041 /* mode 3 - fits in 4KB */
1042 static struct fifo_cfg __initdata mode_3_cfg[] = {
1043 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1044 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1045 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1046 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1047 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1048 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1049 };
1050
1051 /* mode 4 - fits in 16KB */
1052 static struct fifo_cfg __initdata mode_4_cfg[] = {
1053 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1054 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1055 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1056 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1057 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1058 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1059 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1060 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1061 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1062 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1063 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1064 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1065 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1066 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1067 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1068 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1069 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1070 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1071 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 512, },
1072 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 512, },
1073 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 512, },
1074 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 512, },
1075 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 512, },
1076 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 512, },
1077 { .hw_ep_num = 13, .style = FIFO_TX, .maxpacket = 512, },
1078 { .hw_ep_num = 13, .style = FIFO_RX, .maxpacket = 512, },
1079 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1080 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1081 };
1082
1083
1084 /*
1085 * configure a fifo; for non-shared endpoints, this may be called
1086 * once for a tx fifo and once for an rx fifo.
1087 *
1088 * returns negative errno or offset for next fifo.
1089 */
1090 static int __init
fifo_setup(struct musb * musb,struct musb_hw_ep * hw_ep,const struct fifo_cfg * cfg,u16 offset)1091 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1092 const struct fifo_cfg *cfg, u16 offset)
1093 {
1094 void __iomem *mbase = musb->mregs;
1095 int size = 0;
1096 u16 maxpacket = cfg->maxpacket;
1097 u16 c_off = offset >> 3;
1098 u8 c_size;
1099
1100 /* expect hw_ep has already been zero-initialized */
1101
1102 size = ffs(max(maxpacket, (u16) 8)) - 1;
1103 maxpacket = 1 << size;
1104
1105 c_size = size - 3;
1106 if (cfg->mode == BUF_DOUBLE) {
1107 if ((offset + (maxpacket << 1)) >
1108 (1 << (musb->config->ram_bits + 2)))
1109 return -EMSGSIZE;
1110 c_size |= MUSB_FIFOSZ_DPB;
1111 } else {
1112 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1113 return -EMSGSIZE;
1114 }
1115
1116 /* configure the FIFO */
1117 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1118
1119 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1120 /* EP0 reserved endpoint for control, bidirectional;
1121 * EP1 reserved for bulk, two unidirection halves.
1122 */
1123 if (hw_ep->epnum == 1)
1124 musb->bulk_ep = hw_ep;
1125 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1126 #endif
1127 switch (cfg->style) {
1128 case FIFO_TX:
1129 musb_write_txfifosz(mbase, c_size);
1130 musb_write_txfifoadd(mbase, c_off);
1131 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1132 hw_ep->max_packet_sz_tx = maxpacket;
1133 break;
1134 case FIFO_RX:
1135 musb_write_rxfifosz(mbase, c_size);
1136 musb_write_rxfifoadd(mbase, c_off);
1137 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1138 hw_ep->max_packet_sz_rx = maxpacket;
1139 break;
1140 case FIFO_RXTX:
1141 musb_write_txfifosz(mbase, c_size);
1142 musb_write_txfifoadd(mbase, c_off);
1143 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1144 hw_ep->max_packet_sz_rx = maxpacket;
1145
1146 musb_write_rxfifosz(mbase, c_size);
1147 musb_write_rxfifoadd(mbase, c_off);
1148 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1149 hw_ep->max_packet_sz_tx = maxpacket;
1150
1151 hw_ep->is_shared_fifo = true;
1152 break;
1153 }
1154
1155 /* NOTE rx and tx endpoint irqs aren't managed separately,
1156 * which happens to be ok
1157 */
1158 musb->epmask |= (1 << hw_ep->epnum);
1159
1160 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1161 }
1162
1163 static struct fifo_cfg __initdata ep0_cfg = {
1164 .style = FIFO_RXTX, .maxpacket = 64,
1165 };
1166
ep_config_from_table(struct musb * musb)1167 static int __init ep_config_from_table(struct musb *musb)
1168 {
1169 const struct fifo_cfg *cfg;
1170 unsigned i, n;
1171 int offset;
1172 struct musb_hw_ep *hw_ep = musb->endpoints;
1173
1174 switch (fifo_mode) {
1175 default:
1176 fifo_mode = 0;
1177 /* FALLTHROUGH */
1178 case 0:
1179 cfg = mode_0_cfg;
1180 n = ARRAY_SIZE(mode_0_cfg);
1181 break;
1182 case 1:
1183 cfg = mode_1_cfg;
1184 n = ARRAY_SIZE(mode_1_cfg);
1185 break;
1186 case 2:
1187 cfg = mode_2_cfg;
1188 n = ARRAY_SIZE(mode_2_cfg);
1189 break;
1190 case 3:
1191 cfg = mode_3_cfg;
1192 n = ARRAY_SIZE(mode_3_cfg);
1193 break;
1194 case 4:
1195 cfg = mode_4_cfg;
1196 n = ARRAY_SIZE(mode_4_cfg);
1197 break;
1198 }
1199
1200 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1201 musb_driver_name, fifo_mode);
1202
1203
1204 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1205 /* assert(offset > 0) */
1206
1207 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1208 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1209 */
1210
1211 for (i = 0; i < n; i++) {
1212 u8 epn = cfg->hw_ep_num;
1213
1214 if (epn >= musb->config->num_eps) {
1215 pr_debug("%s: invalid ep %d\n",
1216 musb_driver_name, epn);
1217 return -EINVAL;
1218 }
1219 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1220 if (offset < 0) {
1221 pr_debug("%s: mem overrun, ep %d\n",
1222 musb_driver_name, epn);
1223 return -EINVAL;
1224 }
1225 epn++;
1226 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1227 }
1228
1229 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1230 musb_driver_name,
1231 n + 1, musb->config->num_eps * 2 - 1,
1232 offset, (1 << (musb->config->ram_bits + 2)));
1233
1234 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1235 if (!musb->bulk_ep) {
1236 pr_debug("%s: missing bulk\n", musb_driver_name);
1237 return -EINVAL;
1238 }
1239 #endif
1240
1241 return 0;
1242 }
1243
1244
1245 /*
1246 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1247 * @param musb the controller
1248 */
ep_config_from_hw(struct musb * musb)1249 static int __init ep_config_from_hw(struct musb *musb)
1250 {
1251 u8 epnum = 0;
1252 struct musb_hw_ep *hw_ep;
1253 void *mbase = musb->mregs;
1254 int ret = 0;
1255
1256 DBG(2, "<== static silicon ep config\n");
1257
1258 /* FIXME pick up ep0 maxpacket size */
1259
1260 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1261 musb_ep_select(mbase, epnum);
1262 hw_ep = musb->endpoints + epnum;
1263
1264 ret = musb_read_fifosize(musb, hw_ep, epnum);
1265 if (ret < 0)
1266 break;
1267
1268 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1269
1270 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1271 /* pick an RX/TX endpoint for bulk */
1272 if (hw_ep->max_packet_sz_tx < 512
1273 || hw_ep->max_packet_sz_rx < 512)
1274 continue;
1275
1276 /* REVISIT: this algorithm is lazy, we should at least
1277 * try to pick a double buffered endpoint.
1278 */
1279 if (musb->bulk_ep)
1280 continue;
1281 musb->bulk_ep = hw_ep;
1282 #endif
1283 }
1284
1285 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1286 if (!musb->bulk_ep) {
1287 pr_debug("%s: missing bulk\n", musb_driver_name);
1288 return -EINVAL;
1289 }
1290 #endif
1291
1292 return 0;
1293 }
1294
1295 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1296
1297 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1298 * configure endpoints, or take their config from silicon
1299 */
musb_core_init(u16 musb_type,struct musb * musb)1300 static int __init musb_core_init(u16 musb_type, struct musb *musb)
1301 {
1302 #ifdef MUSB_AHB_ID
1303 u32 data;
1304 #endif
1305 u8 reg;
1306 char *type;
1307 u16 hwvers, rev_major, rev_minor;
1308 char aInfo[78], aRevision[32], aDate[12];
1309 void __iomem *mbase = musb->mregs;
1310 int status = 0;
1311 int i;
1312
1313 /* log core options (read using indexed model) */
1314 musb_ep_select(mbase, 0);
1315 reg = musb_read_configdata(mbase);
1316
1317 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1318 if (reg & MUSB_CONFIGDATA_DYNFIFO)
1319 strcat(aInfo, ", dyn FIFOs");
1320 if (reg & MUSB_CONFIGDATA_MPRXE) {
1321 strcat(aInfo, ", bulk combine");
1322 #ifdef C_MP_RX
1323 musb->bulk_combine = true;
1324 #else
1325 strcat(aInfo, " (X)"); /* no driver support */
1326 #endif
1327 }
1328 if (reg & MUSB_CONFIGDATA_MPTXE) {
1329 strcat(aInfo, ", bulk split");
1330 #ifdef C_MP_TX
1331 musb->bulk_split = true;
1332 #else
1333 strcat(aInfo, " (X)"); /* no driver support */
1334 #endif
1335 }
1336 if (reg & MUSB_CONFIGDATA_HBRXE) {
1337 strcat(aInfo, ", HB-ISO Rx");
1338 strcat(aInfo, " (X)"); /* no driver support */
1339 }
1340 if (reg & MUSB_CONFIGDATA_HBTXE) {
1341 strcat(aInfo, ", HB-ISO Tx");
1342 strcat(aInfo, " (X)"); /* no driver support */
1343 }
1344 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1345 strcat(aInfo, ", SoftConn");
1346
1347 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1348 musb_driver_name, reg, aInfo);
1349
1350 #ifdef MUSB_AHB_ID
1351 data = musb_readl(mbase, 0x404);
1352 sprintf(aDate, "%04d-%02x-%02x", (data & 0xffff),
1353 (data >> 16) & 0xff, (data >> 24) & 0xff);
1354 /* FIXME ID2 and ID3 are unused */
1355 data = musb_readl(mbase, 0x408);
1356 printk(KERN_DEBUG "ID2=%lx\n", (long unsigned)data);
1357 data = musb_readl(mbase, 0x40c);
1358 printk(KERN_DEBUG "ID3=%lx\n", (long unsigned)data);
1359 reg = musb_readb(mbase, 0x400);
1360 musb_type = ('M' == reg) ? MUSB_CONTROLLER_MHDRC : MUSB_CONTROLLER_HDRC;
1361 #else
1362 aDate[0] = 0;
1363 #endif
1364 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1365 musb->is_multipoint = 1;
1366 type = "M";
1367 } else {
1368 musb->is_multipoint = 0;
1369 type = "";
1370 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1371 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1372 printk(KERN_ERR
1373 "%s: kernel must blacklist external hubs\n",
1374 musb_driver_name);
1375 #endif
1376 #endif
1377 }
1378
1379 /* log release info */
1380 hwvers = musb_read_hwvers(mbase);
1381 rev_major = (hwvers >> 10) & 0x1f;
1382 rev_minor = hwvers & 0x3ff;
1383 snprintf(aRevision, 32, "%d.%d%s", rev_major,
1384 rev_minor, (hwvers & 0x8000) ? "RC" : "");
1385 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1386 musb_driver_name, type, aRevision, aDate);
1387
1388 /* configure ep0 */
1389 musb_configure_ep0(musb);
1390
1391 /* discover endpoint configuration */
1392 musb->nr_endpoints = 1;
1393 musb->epmask = 1;
1394
1395 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1396 if (musb->config->dyn_fifo)
1397 status = ep_config_from_table(musb);
1398 else {
1399 ERR("reconfigure software for Dynamic FIFOs\n");
1400 status = -ENODEV;
1401 }
1402 } else {
1403 if (!musb->config->dyn_fifo)
1404 status = ep_config_from_hw(musb);
1405 else {
1406 ERR("reconfigure software for static FIFOs\n");
1407 return -ENODEV;
1408 }
1409 }
1410
1411 if (status < 0)
1412 return status;
1413
1414 /* finish init, and print endpoint config */
1415 for (i = 0; i < musb->nr_endpoints; i++) {
1416 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1417
1418 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
1419 #ifdef CONFIG_USB_TUSB6010
1420 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
1421 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1422 hw_ep->fifo_sync_va =
1423 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1424
1425 if (i == 0)
1426 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1427 else
1428 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
1429 #endif
1430
1431 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
1432 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1433 hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
1434 hw_ep->rx_reinit = 1;
1435 hw_ep->tx_reinit = 1;
1436 #endif
1437
1438 if (hw_ep->max_packet_sz_tx) {
1439 printk(KERN_DEBUG
1440 "%s: hw_ep %d%s, %smax %d\n",
1441 musb_driver_name, i,
1442 hw_ep->is_shared_fifo ? "shared" : "tx",
1443 hw_ep->tx_double_buffered
1444 ? "doublebuffer, " : "",
1445 hw_ep->max_packet_sz_tx);
1446 }
1447 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1448 printk(KERN_DEBUG
1449 "%s: hw_ep %d%s, %smax %d\n",
1450 musb_driver_name, i,
1451 "rx",
1452 hw_ep->rx_double_buffered
1453 ? "doublebuffer, " : "",
1454 hw_ep->max_packet_sz_rx);
1455 }
1456 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1457 DBG(1, "hw_ep %d not configured\n", i);
1458 }
1459
1460 return 0;
1461 }
1462
1463 /*-------------------------------------------------------------------------*/
1464
1465 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
1466
generic_interrupt(int irq,void * __hci)1467 static irqreturn_t generic_interrupt(int irq, void *__hci)
1468 {
1469 unsigned long flags;
1470 irqreturn_t retval = IRQ_NONE;
1471 struct musb *musb = __hci;
1472
1473 spin_lock_irqsave(&musb->lock, flags);
1474
1475 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
1476 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
1477 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
1478
1479 if (musb->int_usb || musb->int_tx || musb->int_rx)
1480 retval = musb_interrupt(musb);
1481
1482 spin_unlock_irqrestore(&musb->lock, flags);
1483
1484 /* REVISIT we sometimes get spurious IRQs on g_ep0
1485 * not clear why...
1486 */
1487 if (retval != IRQ_HANDLED)
1488 DBG(5, "spurious?\n");
1489
1490 return IRQ_HANDLED;
1491 }
1492
1493 #else
1494 #define generic_interrupt NULL
1495 #endif
1496
1497 /*
1498 * handle all the irqs defined by the HDRC core. for now we expect: other
1499 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1500 * will be assigned, and the irq will already have been acked.
1501 *
1502 * called in irq context with spinlock held, irqs blocked
1503 */
musb_interrupt(struct musb * musb)1504 irqreturn_t musb_interrupt(struct musb *musb)
1505 {
1506 irqreturn_t retval = IRQ_NONE;
1507 u8 devctl, power;
1508 int ep_num;
1509 u32 reg;
1510
1511 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1512 power = musb_readb(musb->mregs, MUSB_POWER);
1513
1514 DBG(4, "** IRQ %s usb%04x tx%04x rx%04x\n",
1515 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
1516 musb->int_usb, musb->int_tx, musb->int_rx);
1517
1518 /* the core can interrupt us for multiple reasons; docs have
1519 * a generic interrupt flowchart to follow
1520 */
1521 if (musb->int_usb & STAGE0_MASK)
1522 retval |= musb_stage0_irq(musb, musb->int_usb,
1523 devctl, power);
1524
1525 /* "stage 1" is handling endpoint irqs */
1526
1527 /* handle endpoint 0 first */
1528 if (musb->int_tx & 1) {
1529 if (devctl & MUSB_DEVCTL_HM)
1530 retval |= musb_h_ep0_irq(musb);
1531 else
1532 retval |= musb_g_ep0_irq(musb);
1533 }
1534
1535 /* RX on endpoints 1-15 */
1536 reg = musb->int_rx >> 1;
1537 ep_num = 1;
1538 while (reg) {
1539 if (reg & 1) {
1540 /* musb_ep_select(musb->mregs, ep_num); */
1541 /* REVISIT just retval = ep->rx_irq(...) */
1542 retval = IRQ_HANDLED;
1543 if (devctl & MUSB_DEVCTL_HM) {
1544 if (is_host_capable())
1545 musb_host_rx(musb, ep_num);
1546 } else {
1547 if (is_peripheral_capable())
1548 musb_g_rx(musb, ep_num);
1549 }
1550 }
1551
1552 reg >>= 1;
1553 ep_num++;
1554 }
1555
1556 /* TX on endpoints 1-15 */
1557 reg = musb->int_tx >> 1;
1558 ep_num = 1;
1559 while (reg) {
1560 if (reg & 1) {
1561 /* musb_ep_select(musb->mregs, ep_num); */
1562 /* REVISIT just retval |= ep->tx_irq(...) */
1563 retval = IRQ_HANDLED;
1564 if (devctl & MUSB_DEVCTL_HM) {
1565 if (is_host_capable())
1566 musb_host_tx(musb, ep_num);
1567 } else {
1568 if (is_peripheral_capable())
1569 musb_g_tx(musb, ep_num);
1570 }
1571 }
1572 reg >>= 1;
1573 ep_num++;
1574 }
1575
1576 /* finish handling "global" interrupts after handling fifos */
1577 if (musb->int_usb)
1578 retval |= musb_stage2_irq(musb,
1579 musb->int_usb, devctl, power);
1580
1581 return retval;
1582 }
1583
1584
1585 #ifndef CONFIG_MUSB_PIO_ONLY
1586 static int __initdata use_dma = 1;
1587
1588 /* "modprobe ... use_dma=0" etc */
1589 module_param(use_dma, bool, 0);
1590 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1591
musb_dma_completion(struct musb * musb,u8 epnum,u8 transmit)1592 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1593 {
1594 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1595
1596 /* called with controller lock already held */
1597
1598 if (!epnum) {
1599 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1600 if (!is_cppi_enabled()) {
1601 /* endpoint 0 */
1602 if (devctl & MUSB_DEVCTL_HM)
1603 musb_h_ep0_irq(musb);
1604 else
1605 musb_g_ep0_irq(musb);
1606 }
1607 #endif
1608 } else {
1609 /* endpoints 1..15 */
1610 if (transmit) {
1611 if (devctl & MUSB_DEVCTL_HM) {
1612 if (is_host_capable())
1613 musb_host_tx(musb, epnum);
1614 } else {
1615 if (is_peripheral_capable())
1616 musb_g_tx(musb, epnum);
1617 }
1618 } else {
1619 /* receive */
1620 if (devctl & MUSB_DEVCTL_HM) {
1621 if (is_host_capable())
1622 musb_host_rx(musb, epnum);
1623 } else {
1624 if (is_peripheral_capable())
1625 musb_g_rx(musb, epnum);
1626 }
1627 }
1628 }
1629 }
1630
1631 #else
1632 #define use_dma 0
1633 #endif
1634
1635 /*-------------------------------------------------------------------------*/
1636
1637 #ifdef CONFIG_SYSFS
1638
1639 static ssize_t
musb_mode_show(struct device * dev,struct device_attribute * attr,char * buf)1640 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1641 {
1642 struct musb *musb = dev_to_musb(dev);
1643 unsigned long flags;
1644 int ret = -EINVAL;
1645
1646 spin_lock_irqsave(&musb->lock, flags);
1647 ret = sprintf(buf, "%s\n", otg_state_string(musb));
1648 spin_unlock_irqrestore(&musb->lock, flags);
1649
1650 return ret;
1651 }
1652
1653 static ssize_t
musb_mode_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t n)1654 musb_mode_store(struct device *dev, struct device_attribute *attr,
1655 const char *buf, size_t n)
1656 {
1657 struct musb *musb = dev_to_musb(dev);
1658 unsigned long flags;
1659 int status;
1660
1661 spin_lock_irqsave(&musb->lock, flags);
1662 if (sysfs_streq(buf, "host"))
1663 status = musb_platform_set_mode(musb, MUSB_HOST);
1664 else if (sysfs_streq(buf, "peripheral"))
1665 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1666 else if (sysfs_streq(buf, "otg"))
1667 status = musb_platform_set_mode(musb, MUSB_OTG);
1668 else
1669 status = -EINVAL;
1670 spin_unlock_irqrestore(&musb->lock, flags);
1671
1672 return (status == 0) ? n : status;
1673 }
1674 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1675
1676 static ssize_t
musb_vbus_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t n)1677 musb_vbus_store(struct device *dev, struct device_attribute *attr,
1678 const char *buf, size_t n)
1679 {
1680 struct musb *musb = dev_to_musb(dev);
1681 unsigned long flags;
1682 unsigned long val;
1683
1684 if (sscanf(buf, "%lu", &val) < 1) {
1685 printk(KERN_ERR "Invalid VBUS timeout ms value\n");
1686 return -EINVAL;
1687 }
1688
1689 spin_lock_irqsave(&musb->lock, flags);
1690 musb->a_wait_bcon = val;
1691 if (musb->xceiv.state == OTG_STATE_A_WAIT_BCON)
1692 musb->is_active = 0;
1693 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1694 spin_unlock_irqrestore(&musb->lock, flags);
1695
1696 return n;
1697 }
1698
1699 static ssize_t
musb_vbus_show(struct device * dev,struct device_attribute * attr,char * buf)1700 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1701 {
1702 struct musb *musb = dev_to_musb(dev);
1703 unsigned long flags;
1704 unsigned long val;
1705 int vbus;
1706
1707 spin_lock_irqsave(&musb->lock, flags);
1708 val = musb->a_wait_bcon;
1709 vbus = musb_platform_get_vbus_status(musb);
1710 spin_unlock_irqrestore(&musb->lock, flags);
1711
1712 return sprintf(buf, "Vbus %s, timeout %lu\n",
1713 vbus ? "on" : "off", val);
1714 }
1715 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1716
1717 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1718
1719 /* Gadget drivers can't know that a host is connected so they might want
1720 * to start SRP, but users can. This allows userspace to trigger SRP.
1721 */
1722 static ssize_t
musb_srp_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t n)1723 musb_srp_store(struct device *dev, struct device_attribute *attr,
1724 const char *buf, size_t n)
1725 {
1726 struct musb *musb = dev_to_musb(dev);
1727 unsigned short srp;
1728
1729 if (sscanf(buf, "%hu", &srp) != 1
1730 || (srp != 1)) {
1731 printk(KERN_ERR "SRP: Value must be 1\n");
1732 return -EINVAL;
1733 }
1734
1735 if (srp == 1)
1736 musb_g_wakeup(musb);
1737
1738 return n;
1739 }
1740 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1741
1742 #endif /* CONFIG_USB_GADGET_MUSB_HDRC */
1743
1744 #endif /* sysfs */
1745
1746 /* Only used to provide driver mode change events */
musb_irq_work(struct work_struct * data)1747 static void musb_irq_work(struct work_struct *data)
1748 {
1749 struct musb *musb = container_of(data, struct musb, irq_work);
1750 static int old_state;
1751
1752 if (musb->xceiv.state != old_state) {
1753 old_state = musb->xceiv.state;
1754 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1755 }
1756 }
1757
1758 /* --------------------------------------------------------------------------
1759 * Init support
1760 */
1761
1762 static struct musb *__init
allocate_instance(struct device * dev,struct musb_hdrc_config * config,void __iomem * mbase)1763 allocate_instance(struct device *dev,
1764 struct musb_hdrc_config *config, void __iomem *mbase)
1765 {
1766 struct musb *musb;
1767 struct musb_hw_ep *ep;
1768 int epnum;
1769 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1770 struct usb_hcd *hcd;
1771
1772 hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
1773 if (!hcd)
1774 return NULL;
1775 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
1776
1777 musb = hcd_to_musb(hcd);
1778 INIT_LIST_HEAD(&musb->control);
1779 INIT_LIST_HEAD(&musb->in_bulk);
1780 INIT_LIST_HEAD(&musb->out_bulk);
1781
1782 hcd->uses_new_polling = 1;
1783
1784 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1785 #else
1786 musb = kzalloc(sizeof *musb, GFP_KERNEL);
1787 if (!musb)
1788 return NULL;
1789 dev_set_drvdata(dev, musb);
1790
1791 #endif
1792
1793 musb->mregs = mbase;
1794 musb->ctrl_base = mbase;
1795 musb->nIrq = -ENODEV;
1796 musb->config = config;
1797 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
1798 for (epnum = 0, ep = musb->endpoints;
1799 epnum < musb->config->num_eps;
1800 epnum++, ep++) {
1801 ep->musb = musb;
1802 ep->epnum = epnum;
1803 }
1804
1805 musb->controller = dev;
1806 return musb;
1807 }
1808
musb_free(struct musb * musb)1809 static void musb_free(struct musb *musb)
1810 {
1811 /* this has multiple entry modes. it handles fault cleanup after
1812 * probe(), where things may be partially set up, as well as rmmod
1813 * cleanup after everything's been de-activated.
1814 */
1815
1816 #ifdef CONFIG_SYSFS
1817 device_remove_file(musb->controller, &dev_attr_mode);
1818 device_remove_file(musb->controller, &dev_attr_vbus);
1819 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1820 device_remove_file(musb->controller, &dev_attr_srp);
1821 #endif
1822 #endif
1823
1824 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1825 musb_gadget_cleanup(musb);
1826 #endif
1827
1828 if (musb->nIrq >= 0) {
1829 if (musb->irq_wake)
1830 disable_irq_wake(musb->nIrq);
1831 free_irq(musb->nIrq, musb);
1832 }
1833 if (is_dma_capable() && musb->dma_controller) {
1834 struct dma_controller *c = musb->dma_controller;
1835
1836 (void) c->stop(c);
1837 dma_controller_destroy(c);
1838 }
1839
1840 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1841 musb_platform_exit(musb);
1842 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1843
1844 if (musb->clock) {
1845 clk_disable(musb->clock);
1846 clk_put(musb->clock);
1847 }
1848
1849 #ifdef CONFIG_USB_MUSB_OTG
1850 put_device(musb->xceiv.dev);
1851 #endif
1852
1853 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1854 usb_put_hcd(musb_to_hcd(musb));
1855 #else
1856 kfree(musb);
1857 #endif
1858 }
1859
1860 /*
1861 * Perform generic per-controller initialization.
1862 *
1863 * @pDevice: the controller (already clocked, etc)
1864 * @nIrq: irq
1865 * @mregs: virtual address of controller registers,
1866 * not yet corrected for platform-specific offsets
1867 */
1868 static int __init
musb_init_controller(struct device * dev,int nIrq,void __iomem * ctrl)1869 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1870 {
1871 int status;
1872 struct musb *musb;
1873 struct musb_hdrc_platform_data *plat = dev->platform_data;
1874
1875 /* The driver might handle more features than the board; OK.
1876 * Fail when the board needs a feature that's not enabled.
1877 */
1878 if (!plat) {
1879 dev_dbg(dev, "no platform_data?\n");
1880 return -ENODEV;
1881 }
1882 switch (plat->mode) {
1883 case MUSB_HOST:
1884 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1885 break;
1886 #else
1887 goto bad_config;
1888 #endif
1889 case MUSB_PERIPHERAL:
1890 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1891 break;
1892 #else
1893 goto bad_config;
1894 #endif
1895 case MUSB_OTG:
1896 #ifdef CONFIG_USB_MUSB_OTG
1897 break;
1898 #else
1899 bad_config:
1900 #endif
1901 default:
1902 dev_err(dev, "incompatible Kconfig role setting\n");
1903 return -EINVAL;
1904 }
1905
1906 /* allocate */
1907 musb = allocate_instance(dev, plat->config, ctrl);
1908 if (!musb)
1909 return -ENOMEM;
1910
1911 spin_lock_init(&musb->lock);
1912 musb->board_mode = plat->mode;
1913 musb->board_set_power = plat->set_power;
1914 musb->set_clock = plat->set_clock;
1915 musb->min_power = plat->min_power;
1916
1917 /* Clock usage is chip-specific ... functional clock (DaVinci,
1918 * OMAP2430), or PHY ref (some TUSB6010 boards). All this core
1919 * code does is make sure a clock handle is available; platform
1920 * code manages it during start/stop and suspend/resume.
1921 */
1922 if (plat->clock) {
1923 musb->clock = clk_get(dev, plat->clock);
1924 if (IS_ERR(musb->clock)) {
1925 status = PTR_ERR(musb->clock);
1926 musb->clock = NULL;
1927 goto fail;
1928 }
1929 }
1930
1931 /* assume vbus is off */
1932
1933 /* platform adjusts musb->mregs and musb->isr if needed,
1934 * and activates clocks
1935 */
1936 musb->isr = generic_interrupt;
1937 status = musb_platform_init(musb);
1938
1939 if (status < 0)
1940 goto fail;
1941 if (!musb->isr) {
1942 status = -ENODEV;
1943 goto fail2;
1944 }
1945
1946 #ifndef CONFIG_MUSB_PIO_ONLY
1947 if (use_dma && dev->dma_mask) {
1948 struct dma_controller *c;
1949
1950 c = dma_controller_create(musb, musb->mregs);
1951 musb->dma_controller = c;
1952 if (c)
1953 (void) c->start(c);
1954 }
1955 #endif
1956 /* ideally this would be abstracted in platform setup */
1957 if (!is_dma_capable() || !musb->dma_controller)
1958 dev->dma_mask = NULL;
1959
1960 /* be sure interrupts are disabled before connecting ISR */
1961 musb_platform_disable(musb);
1962 musb_generic_disable(musb);
1963
1964 /* setup musb parts of the core (especially endpoints) */
1965 status = musb_core_init(plat->config->multipoint
1966 ? MUSB_CONTROLLER_MHDRC
1967 : MUSB_CONTROLLER_HDRC, musb);
1968 if (status < 0)
1969 goto fail2;
1970
1971 /* Init IRQ workqueue before request_irq */
1972 INIT_WORK(&musb->irq_work, musb_irq_work);
1973
1974 /* attach to the IRQ */
1975 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
1976 dev_err(dev, "request_irq %d failed!\n", nIrq);
1977 status = -ENODEV;
1978 goto fail2;
1979 }
1980 musb->nIrq = nIrq;
1981 /* FIXME this handles wakeup irqs wrong */
1982 if (enable_irq_wake(nIrq) == 0) {
1983 musb->irq_wake = 1;
1984 device_init_wakeup(dev, 1);
1985 } else {
1986 musb->irq_wake = 0;
1987 }
1988
1989 pr_info("%s: USB %s mode controller at %p using %s, IRQ %d\n",
1990 musb_driver_name,
1991 ({char *s;
1992 switch (musb->board_mode) {
1993 case MUSB_HOST: s = "Host"; break;
1994 case MUSB_PERIPHERAL: s = "Peripheral"; break;
1995 default: s = "OTG"; break;
1996 }; s; }),
1997 ctrl,
1998 (is_dma_capable() && musb->dma_controller)
1999 ? "DMA" : "PIO",
2000 musb->nIrq);
2001
2002 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2003 /* host side needs more setup, except for no-host modes */
2004 if (musb->board_mode != MUSB_PERIPHERAL) {
2005 struct usb_hcd *hcd = musb_to_hcd(musb);
2006
2007 if (musb->board_mode == MUSB_OTG)
2008 hcd->self.otg_port = 1;
2009 musb->xceiv.host = &hcd->self;
2010 hcd->power_budget = 2 * (plat->power ? : 250);
2011 }
2012 #endif /* CONFIG_USB_MUSB_HDRC_HCD */
2013
2014 /* For the host-only role, we can activate right away.
2015 * (We expect the ID pin to be forcibly grounded!!)
2016 * Otherwise, wait till the gadget driver hooks up.
2017 */
2018 if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
2019 MUSB_HST_MODE(musb);
2020 musb->xceiv.default_a = 1;
2021 musb->xceiv.state = OTG_STATE_A_IDLE;
2022
2023 status = usb_add_hcd(musb_to_hcd(musb), -1, 0);
2024 if (status)
2025 goto fail;
2026
2027 DBG(1, "%s mode, status %d, devctl %02x %c\n",
2028 "HOST", status,
2029 musb_readb(musb->mregs, MUSB_DEVCTL),
2030 (musb_readb(musb->mregs, MUSB_DEVCTL)
2031 & MUSB_DEVCTL_BDEVICE
2032 ? 'B' : 'A'));
2033
2034 } else /* peripheral is enabled */ {
2035 MUSB_DEV_MODE(musb);
2036 musb->xceiv.default_a = 0;
2037 musb->xceiv.state = OTG_STATE_B_IDLE;
2038
2039 status = musb_gadget_setup(musb);
2040 if (status)
2041 goto fail;
2042
2043 DBG(1, "%s mode, status %d, dev%02x\n",
2044 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
2045 status,
2046 musb_readb(musb->mregs, MUSB_DEVCTL));
2047
2048 }
2049
2050 #ifdef CONFIG_SYSFS
2051 status = device_create_file(dev, &dev_attr_mode);
2052 status = device_create_file(dev, &dev_attr_vbus);
2053 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
2054 status = device_create_file(dev, &dev_attr_srp);
2055 #endif /* CONFIG_USB_GADGET_MUSB_HDRC */
2056 status = 0;
2057 #endif
2058 if (status)
2059 goto fail2;
2060
2061 return 0;
2062
2063 fail2:
2064 #ifdef CONFIG_SYSFS
2065 device_remove_file(musb->controller, &dev_attr_mode);
2066 device_remove_file(musb->controller, &dev_attr_vbus);
2067 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
2068 device_remove_file(musb->controller, &dev_attr_srp);
2069 #endif
2070 #endif
2071 musb_platform_exit(musb);
2072 fail:
2073 dev_err(musb->controller,
2074 "musb_init_controller failed with status %d\n", status);
2075
2076 if (musb->clock)
2077 clk_put(musb->clock);
2078 device_init_wakeup(dev, 0);
2079 musb_free(musb);
2080
2081 return status;
2082
2083 }
2084
2085 /*-------------------------------------------------------------------------*/
2086
2087 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2088 * bridge to a platform device; this driver then suffices.
2089 */
2090
2091 #ifndef CONFIG_MUSB_PIO_ONLY
2092 static u64 *orig_dma_mask;
2093 #endif
2094
musb_probe(struct platform_device * pdev)2095 static int __init musb_probe(struct platform_device *pdev)
2096 {
2097 struct device *dev = &pdev->dev;
2098 int irq = platform_get_irq(pdev, 0);
2099 struct resource *iomem;
2100 void __iomem *base;
2101
2102 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2103 if (!iomem || irq == 0)
2104 return -ENODEV;
2105
2106 base = ioremap(iomem->start, iomem->end - iomem->start + 1);
2107 if (!base) {
2108 dev_err(dev, "ioremap failed\n");
2109 return -ENOMEM;
2110 }
2111
2112 #ifndef CONFIG_MUSB_PIO_ONLY
2113 /* clobbered by use_dma=n */
2114 orig_dma_mask = dev->dma_mask;
2115 #endif
2116 return musb_init_controller(dev, irq, base);
2117 }
2118
musb_remove(struct platform_device * pdev)2119 static int __devexit musb_remove(struct platform_device *pdev)
2120 {
2121 struct musb *musb = dev_to_musb(&pdev->dev);
2122 void __iomem *ctrl_base = musb->ctrl_base;
2123
2124 /* this gets called on rmmod.
2125 * - Host mode: host may still be active
2126 * - Peripheral mode: peripheral is deactivated (or never-activated)
2127 * - OTG mode: both roles are deactivated (or never-activated)
2128 */
2129 musb_shutdown(pdev);
2130 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2131 if (musb->board_mode == MUSB_HOST)
2132 usb_remove_hcd(musb_to_hcd(musb));
2133 #endif
2134 musb_free(musb);
2135 iounmap(ctrl_base);
2136 device_init_wakeup(&pdev->dev, 0);
2137 #ifndef CONFIG_MUSB_PIO_ONLY
2138 pdev->dev.dma_mask = orig_dma_mask;
2139 #endif
2140 return 0;
2141 }
2142
2143 #ifdef CONFIG_PM
2144
musb_suspend(struct platform_device * pdev,pm_message_t message)2145 static int musb_suspend(struct platform_device *pdev, pm_message_t message)
2146 {
2147 unsigned long flags;
2148 struct musb *musb = dev_to_musb(&pdev->dev);
2149
2150 if (!musb->clock)
2151 return 0;
2152
2153 spin_lock_irqsave(&musb->lock, flags);
2154
2155 if (is_peripheral_active(musb)) {
2156 /* FIXME force disconnect unless we know USB will wake
2157 * the system up quickly enough to respond ...
2158 */
2159 } else if (is_host_active(musb)) {
2160 /* we know all the children are suspended; sometimes
2161 * they will even be wakeup-enabled.
2162 */
2163 }
2164
2165 if (musb->set_clock)
2166 musb->set_clock(musb->clock, 0);
2167 else
2168 clk_disable(musb->clock);
2169 spin_unlock_irqrestore(&musb->lock, flags);
2170 return 0;
2171 }
2172
musb_resume(struct platform_device * pdev)2173 static int musb_resume(struct platform_device *pdev)
2174 {
2175 unsigned long flags;
2176 struct musb *musb = dev_to_musb(&pdev->dev);
2177
2178 if (!musb->clock)
2179 return 0;
2180
2181 spin_lock_irqsave(&musb->lock, flags);
2182
2183 if (musb->set_clock)
2184 musb->set_clock(musb->clock, 1);
2185 else
2186 clk_enable(musb->clock);
2187
2188 /* for static cmos like DaVinci, register values were preserved
2189 * unless for some reason the whole soc powered down and we're
2190 * not treating that as a whole-system restart (e.g. swsusp)
2191 */
2192 spin_unlock_irqrestore(&musb->lock, flags);
2193 return 0;
2194 }
2195
2196 #else
2197 #define musb_suspend NULL
2198 #define musb_resume NULL
2199 #endif
2200
2201 static struct platform_driver musb_driver = {
2202 .driver = {
2203 .name = (char *)musb_driver_name,
2204 .bus = &platform_bus_type,
2205 .owner = THIS_MODULE,
2206 },
2207 .remove = __devexit_p(musb_remove),
2208 .shutdown = musb_shutdown,
2209 .suspend = musb_suspend,
2210 .resume = musb_resume,
2211 };
2212
2213 /*-------------------------------------------------------------------------*/
2214
musb_init(void)2215 static int __init musb_init(void)
2216 {
2217 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2218 if (usb_disabled())
2219 return 0;
2220 #endif
2221
2222 pr_info("%s: version " MUSB_VERSION ", "
2223 #ifdef CONFIG_MUSB_PIO_ONLY
2224 "pio"
2225 #elif defined(CONFIG_USB_TI_CPPI_DMA)
2226 "cppi-dma"
2227 #elif defined(CONFIG_USB_INVENTRA_DMA)
2228 "musb-dma"
2229 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
2230 "tusb-omap-dma"
2231 #else
2232 "?dma?"
2233 #endif
2234 ", "
2235 #ifdef CONFIG_USB_MUSB_OTG
2236 "otg (peripheral+host)"
2237 #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
2238 "peripheral"
2239 #elif defined(CONFIG_USB_MUSB_HDRC_HCD)
2240 "host"
2241 #endif
2242 ", debug=%d\n",
2243 musb_driver_name, musb_debug);
2244 return platform_driver_probe(&musb_driver, musb_probe);
2245 }
2246
2247 /* make us init after usbcore and i2c (transceivers, regulators, etc)
2248 * and before usb gadget and host-side drivers start to register
2249 */
2250 fs_initcall(musb_init);
2251
musb_cleanup(void)2252 static void __exit musb_cleanup(void)
2253 {
2254 platform_driver_unregister(&musb_driver);
2255 }
2256 module_exit(musb_cleanup);
2257