1 /*
2 * Support for PCI bridges found on Power Macintoshes.
3 *
4 * Copyright (C) 2003-2005 Benjamin Herrenschmuidt (benh@kernel.crashing.org)
5 * Copyright (C) 1997 Paul Mackerras (paulus@samba.org)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
13 #include <linux/kernel.h>
14 #include <linux/pci.h>
15 #include <linux/delay.h>
16 #include <linux/string.h>
17 #include <linux/init.h>
18 #include <linux/bootmem.h>
19 #include <linux/irq.h>
20
21 #include <asm/sections.h>
22 #include <asm/io.h>
23 #include <asm/prom.h>
24 #include <asm/pci-bridge.h>
25 #include <asm/machdep.h>
26 #include <asm/pmac_feature.h>
27 #include <asm/grackle.h>
28 #include <asm/ppc-pci.h>
29
30 #undef DEBUG
31
32 #ifdef DEBUG
33 #define DBG(x...) printk(x)
34 #else
35 #define DBG(x...)
36 #endif
37
38 /* XXX Could be per-controller, but I don't think we risk anything by
39 * assuming we won't have both UniNorth and Bandit */
40 static int has_uninorth;
41 #ifdef CONFIG_PPC64
42 static struct pci_controller *u3_agp;
43 #else
44 static int has_second_ohare;
45 #endif /* CONFIG_PPC64 */
46
47 extern int pcibios_assign_bus_offset;
48
49 struct device_node *k2_skiplist[2];
50
51 /*
52 * Magic constants for enabling cache coherency in the bandit/PSX bridge.
53 */
54 #define BANDIT_DEVID_2 8
55 #define BANDIT_REVID 3
56
57 #define BANDIT_DEVNUM 11
58 #define BANDIT_MAGIC 0x50
59 #define BANDIT_COHERENT 0x40
60
fixup_one_level_bus_range(struct device_node * node,int higher)61 static int __init fixup_one_level_bus_range(struct device_node *node, int higher)
62 {
63 for (; node != 0;node = node->sibling) {
64 const int * bus_range;
65 const unsigned int *class_code;
66 int len;
67
68 /* For PCI<->PCI bridges or CardBus bridges, we go down */
69 class_code = of_get_property(node, "class-code", NULL);
70 if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
71 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS))
72 continue;
73 bus_range = of_get_property(node, "bus-range", &len);
74 if (bus_range != NULL && len > 2 * sizeof(int)) {
75 if (bus_range[1] > higher)
76 higher = bus_range[1];
77 }
78 higher = fixup_one_level_bus_range(node->child, higher);
79 }
80 return higher;
81 }
82
83 /* This routine fixes the "bus-range" property of all bridges in the
84 * system since they tend to have their "last" member wrong on macs
85 *
86 * Note that the bus numbers manipulated here are OF bus numbers, they
87 * are not Linux bus numbers.
88 */
fixup_bus_range(struct device_node * bridge)89 static void __init fixup_bus_range(struct device_node *bridge)
90 {
91 int *bus_range, len;
92 struct property *prop;
93
94 /* Lookup the "bus-range" property for the hose */
95 prop = of_find_property(bridge, "bus-range", &len);
96 if (prop == NULL || prop->length < 2 * sizeof(int))
97 return;
98
99 bus_range = prop->value;
100 bus_range[1] = fixup_one_level_bus_range(bridge->child, bus_range[1]);
101 }
102
103 /*
104 * Apple MacRISC (U3, UniNorth, Bandit, Chaos) PCI controllers.
105 *
106 * The "Bandit" version is present in all early PCI PowerMacs,
107 * and up to the first ones using Grackle. Some machines may
108 * have 2 bandit controllers (2 PCI busses).
109 *
110 * "Chaos" is used in some "Bandit"-type machines as a bridge
111 * for the separate display bus. It is accessed the same
112 * way as bandit, but cannot be probed for devices. It therefore
113 * has its own config access functions.
114 *
115 * The "UniNorth" version is present in all Core99 machines
116 * (iBook, G4, new IMacs, and all the recent Apple machines).
117 * It contains 3 controllers in one ASIC.
118 *
119 * The U3 is the bridge used on G5 machines. It contains an
120 * AGP bus which is dealt with the old UniNorth access routines
121 * and a HyperTransport bus which uses its own set of access
122 * functions.
123 */
124
125 #define MACRISC_CFA0(devfn, off) \
126 ((1 << (unsigned int)PCI_SLOT(dev_fn)) \
127 | (((unsigned int)PCI_FUNC(dev_fn)) << 8) \
128 | (((unsigned int)(off)) & 0xFCUL))
129
130 #define MACRISC_CFA1(bus, devfn, off) \
131 ((((unsigned int)(bus)) << 16) \
132 |(((unsigned int)(devfn)) << 8) \
133 |(((unsigned int)(off)) & 0xFCUL) \
134 |1UL)
135
macrisc_cfg_access(struct pci_controller * hose,u8 bus,u8 dev_fn,u8 offset)136 static volatile void __iomem *macrisc_cfg_access(struct pci_controller* hose,
137 u8 bus, u8 dev_fn, u8 offset)
138 {
139 unsigned int caddr;
140
141 if (bus == hose->first_busno) {
142 if (dev_fn < (11 << 3))
143 return NULL;
144 caddr = MACRISC_CFA0(dev_fn, offset);
145 } else
146 caddr = MACRISC_CFA1(bus, dev_fn, offset);
147
148 /* Uninorth will return garbage if we don't read back the value ! */
149 do {
150 out_le32(hose->cfg_addr, caddr);
151 } while (in_le32(hose->cfg_addr) != caddr);
152
153 offset &= has_uninorth ? 0x07 : 0x03;
154 return hose->cfg_data + offset;
155 }
156
macrisc_read_config(struct pci_bus * bus,unsigned int devfn,int offset,int len,u32 * val)157 static int macrisc_read_config(struct pci_bus *bus, unsigned int devfn,
158 int offset, int len, u32 *val)
159 {
160 struct pci_controller *hose;
161 volatile void __iomem *addr;
162
163 hose = pci_bus_to_host(bus);
164 if (hose == NULL)
165 return PCIBIOS_DEVICE_NOT_FOUND;
166 if (offset >= 0x100)
167 return PCIBIOS_BAD_REGISTER_NUMBER;
168 addr = macrisc_cfg_access(hose, bus->number, devfn, offset);
169 if (!addr)
170 return PCIBIOS_DEVICE_NOT_FOUND;
171 /*
172 * Note: the caller has already checked that offset is
173 * suitably aligned and that len is 1, 2 or 4.
174 */
175 switch (len) {
176 case 1:
177 *val = in_8(addr);
178 break;
179 case 2:
180 *val = in_le16(addr);
181 break;
182 default:
183 *val = in_le32(addr);
184 break;
185 }
186 return PCIBIOS_SUCCESSFUL;
187 }
188
macrisc_write_config(struct pci_bus * bus,unsigned int devfn,int offset,int len,u32 val)189 static int macrisc_write_config(struct pci_bus *bus, unsigned int devfn,
190 int offset, int len, u32 val)
191 {
192 struct pci_controller *hose;
193 volatile void __iomem *addr;
194
195 hose = pci_bus_to_host(bus);
196 if (hose == NULL)
197 return PCIBIOS_DEVICE_NOT_FOUND;
198 if (offset >= 0x100)
199 return PCIBIOS_BAD_REGISTER_NUMBER;
200 addr = macrisc_cfg_access(hose, bus->number, devfn, offset);
201 if (!addr)
202 return PCIBIOS_DEVICE_NOT_FOUND;
203 /*
204 * Note: the caller has already checked that offset is
205 * suitably aligned and that len is 1, 2 or 4.
206 */
207 switch (len) {
208 case 1:
209 out_8(addr, val);
210 break;
211 case 2:
212 out_le16(addr, val);
213 break;
214 default:
215 out_le32(addr, val);
216 break;
217 }
218 return PCIBIOS_SUCCESSFUL;
219 }
220
221 static struct pci_ops macrisc_pci_ops =
222 {
223 .read = macrisc_read_config,
224 .write = macrisc_write_config,
225 };
226
227 #ifdef CONFIG_PPC32
228 /*
229 * Verify that a specific (bus, dev_fn) exists on chaos
230 */
chaos_validate_dev(struct pci_bus * bus,int devfn,int offset)231 static int chaos_validate_dev(struct pci_bus *bus, int devfn, int offset)
232 {
233 struct device_node *np;
234 const u32 *vendor, *device;
235
236 if (offset >= 0x100)
237 return PCIBIOS_BAD_REGISTER_NUMBER;
238 np = pci_busdev_to_OF_node(bus, devfn);
239 if (np == NULL)
240 return PCIBIOS_DEVICE_NOT_FOUND;
241
242 vendor = of_get_property(np, "vendor-id", NULL);
243 device = of_get_property(np, "device-id", NULL);
244 if (vendor == NULL || device == NULL)
245 return PCIBIOS_DEVICE_NOT_FOUND;
246
247 if ((*vendor == 0x106b) && (*device == 3) && (offset >= 0x10)
248 && (offset != 0x14) && (offset != 0x18) && (offset <= 0x24))
249 return PCIBIOS_BAD_REGISTER_NUMBER;
250
251 return PCIBIOS_SUCCESSFUL;
252 }
253
254 static int
chaos_read_config(struct pci_bus * bus,unsigned int devfn,int offset,int len,u32 * val)255 chaos_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
256 int len, u32 *val)
257 {
258 int result = chaos_validate_dev(bus, devfn, offset);
259 if (result == PCIBIOS_BAD_REGISTER_NUMBER)
260 *val = ~0U;
261 if (result != PCIBIOS_SUCCESSFUL)
262 return result;
263 return macrisc_read_config(bus, devfn, offset, len, val);
264 }
265
266 static int
chaos_write_config(struct pci_bus * bus,unsigned int devfn,int offset,int len,u32 val)267 chaos_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
268 int len, u32 val)
269 {
270 int result = chaos_validate_dev(bus, devfn, offset);
271 if (result != PCIBIOS_SUCCESSFUL)
272 return result;
273 return macrisc_write_config(bus, devfn, offset, len, val);
274 }
275
276 static struct pci_ops chaos_pci_ops =
277 {
278 .read = chaos_read_config,
279 .write = chaos_write_config,
280 };
281
setup_chaos(struct pci_controller * hose,struct resource * addr)282 static void __init setup_chaos(struct pci_controller *hose,
283 struct resource *addr)
284 {
285 /* assume a `chaos' bridge */
286 hose->ops = &chaos_pci_ops;
287 hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000);
288 hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000);
289 }
290 #endif /* CONFIG_PPC32 */
291
292 #ifdef CONFIG_PPC64
293 /*
294 * These versions of U3 HyperTransport config space access ops do not
295 * implement self-view of the HT host yet
296 */
297
298 /*
299 * This function deals with some "special cases" devices.
300 *
301 * 0 -> No special case
302 * 1 -> Skip the device but act as if the access was successfull
303 * (return 0xff's on reads, eventually, cache config space
304 * accesses in a later version)
305 * -1 -> Hide the device (unsuccessful acess)
306 */
u3_ht_skip_device(struct pci_controller * hose,struct pci_bus * bus,unsigned int devfn)307 static int u3_ht_skip_device(struct pci_controller *hose,
308 struct pci_bus *bus, unsigned int devfn)
309 {
310 struct device_node *busdn, *dn;
311 int i;
312
313 /* We only allow config cycles to devices that are in OF device-tree
314 * as we are apparently having some weird things going on with some
315 * revs of K2 on recent G5s, except for the host bridge itself, which
316 * is missing from the tree but we know we can probe.
317 */
318 if (bus->self)
319 busdn = pci_device_to_OF_node(bus->self);
320 else if (devfn == 0)
321 return 0;
322 else
323 busdn = hose->dn;
324 for (dn = busdn->child; dn; dn = dn->sibling)
325 if (PCI_DN(dn) && PCI_DN(dn)->devfn == devfn)
326 break;
327 if (dn == NULL)
328 return -1;
329
330 /*
331 * When a device in K2 is powered down, we die on config
332 * cycle accesses. Fix that here.
333 */
334 for (i=0; i<2; i++)
335 if (k2_skiplist[i] == dn)
336 return 1;
337
338 return 0;
339 }
340
341 #define U3_HT_CFA0(devfn, off) \
342 ((((unsigned int)devfn) << 8) | offset)
343 #define U3_HT_CFA1(bus, devfn, off) \
344 (U3_HT_CFA0(devfn, off) \
345 + (((unsigned int)bus) << 16) \
346 + 0x01000000UL)
347
u3_ht_cfg_access(struct pci_controller * hose,u8 bus,u8 devfn,u8 offset,int * swap)348 static void __iomem *u3_ht_cfg_access(struct pci_controller *hose, u8 bus,
349 u8 devfn, u8 offset, int *swap)
350 {
351 *swap = 1;
352 if (bus == hose->first_busno) {
353 if (devfn != 0)
354 return hose->cfg_data + U3_HT_CFA0(devfn, offset);
355 *swap = 0;
356 return ((void __iomem *)hose->cfg_addr) + (offset << 2);
357 } else
358 return hose->cfg_data + U3_HT_CFA1(bus, devfn, offset);
359 }
360
u3_ht_read_config(struct pci_bus * bus,unsigned int devfn,int offset,int len,u32 * val)361 static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn,
362 int offset, int len, u32 *val)
363 {
364 struct pci_controller *hose;
365 void __iomem *addr;
366 int swap;
367
368 hose = pci_bus_to_host(bus);
369 if (hose == NULL)
370 return PCIBIOS_DEVICE_NOT_FOUND;
371 if (offset >= 0x100)
372 return PCIBIOS_BAD_REGISTER_NUMBER;
373 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset, &swap);
374 if (!addr)
375 return PCIBIOS_DEVICE_NOT_FOUND;
376
377 switch (u3_ht_skip_device(hose, bus, devfn)) {
378 case 0:
379 break;
380 case 1:
381 switch (len) {
382 case 1:
383 *val = 0xff; break;
384 case 2:
385 *val = 0xffff; break;
386 default:
387 *val = 0xfffffffful; break;
388 }
389 return PCIBIOS_SUCCESSFUL;
390 default:
391 return PCIBIOS_DEVICE_NOT_FOUND;
392 }
393
394 /*
395 * Note: the caller has already checked that offset is
396 * suitably aligned and that len is 1, 2 or 4.
397 */
398 switch (len) {
399 case 1:
400 *val = in_8(addr);
401 break;
402 case 2:
403 *val = swap ? in_le16(addr) : in_be16(addr);
404 break;
405 default:
406 *val = swap ? in_le32(addr) : in_be32(addr);
407 break;
408 }
409 return PCIBIOS_SUCCESSFUL;
410 }
411
u3_ht_write_config(struct pci_bus * bus,unsigned int devfn,int offset,int len,u32 val)412 static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn,
413 int offset, int len, u32 val)
414 {
415 struct pci_controller *hose;
416 void __iomem *addr;
417 int swap;
418
419 hose = pci_bus_to_host(bus);
420 if (hose == NULL)
421 return PCIBIOS_DEVICE_NOT_FOUND;
422 if (offset >= 0x100)
423 return PCIBIOS_BAD_REGISTER_NUMBER;
424 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset, &swap);
425 if (!addr)
426 return PCIBIOS_DEVICE_NOT_FOUND;
427
428 switch (u3_ht_skip_device(hose, bus, devfn)) {
429 case 0:
430 break;
431 case 1:
432 return PCIBIOS_SUCCESSFUL;
433 default:
434 return PCIBIOS_DEVICE_NOT_FOUND;
435 }
436
437 /*
438 * Note: the caller has already checked that offset is
439 * suitably aligned and that len is 1, 2 or 4.
440 */
441 switch (len) {
442 case 1:
443 out_8(addr, val);
444 break;
445 case 2:
446 swap ? out_le16(addr, val) : out_be16(addr, val);
447 break;
448 default:
449 swap ? out_le32(addr, val) : out_be32(addr, val);
450 break;
451 }
452 return PCIBIOS_SUCCESSFUL;
453 }
454
455 static struct pci_ops u3_ht_pci_ops =
456 {
457 .read = u3_ht_read_config,
458 .write = u3_ht_write_config,
459 };
460
461 #define U4_PCIE_CFA0(devfn, off) \
462 ((1 << ((unsigned int)PCI_SLOT(dev_fn))) \
463 | (((unsigned int)PCI_FUNC(dev_fn)) << 8) \
464 | ((((unsigned int)(off)) >> 8) << 28) \
465 | (((unsigned int)(off)) & 0xfcU))
466
467 #define U4_PCIE_CFA1(bus, devfn, off) \
468 ((((unsigned int)(bus)) << 16) \
469 |(((unsigned int)(devfn)) << 8) \
470 | ((((unsigned int)(off)) >> 8) << 28) \
471 |(((unsigned int)(off)) & 0xfcU) \
472 |1UL)
473
u4_pcie_cfg_access(struct pci_controller * hose,u8 bus,u8 dev_fn,int offset)474 static volatile void __iomem *u4_pcie_cfg_access(struct pci_controller* hose,
475 u8 bus, u8 dev_fn, int offset)
476 {
477 unsigned int caddr;
478
479 if (bus == hose->first_busno) {
480 caddr = U4_PCIE_CFA0(dev_fn, offset);
481 } else
482 caddr = U4_PCIE_CFA1(bus, dev_fn, offset);
483
484 /* Uninorth will return garbage if we don't read back the value ! */
485 do {
486 out_le32(hose->cfg_addr, caddr);
487 } while (in_le32(hose->cfg_addr) != caddr);
488
489 offset &= 0x03;
490 return hose->cfg_data + offset;
491 }
492
u4_pcie_read_config(struct pci_bus * bus,unsigned int devfn,int offset,int len,u32 * val)493 static int u4_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
494 int offset, int len, u32 *val)
495 {
496 struct pci_controller *hose;
497 volatile void __iomem *addr;
498
499 hose = pci_bus_to_host(bus);
500 if (hose == NULL)
501 return PCIBIOS_DEVICE_NOT_FOUND;
502 if (offset >= 0x1000)
503 return PCIBIOS_BAD_REGISTER_NUMBER;
504 addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset);
505 if (!addr)
506 return PCIBIOS_DEVICE_NOT_FOUND;
507 /*
508 * Note: the caller has already checked that offset is
509 * suitably aligned and that len is 1, 2 or 4.
510 */
511 switch (len) {
512 case 1:
513 *val = in_8(addr);
514 break;
515 case 2:
516 *val = in_le16(addr);
517 break;
518 default:
519 *val = in_le32(addr);
520 break;
521 }
522 return PCIBIOS_SUCCESSFUL;
523 }
524
u4_pcie_write_config(struct pci_bus * bus,unsigned int devfn,int offset,int len,u32 val)525 static int u4_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
526 int offset, int len, u32 val)
527 {
528 struct pci_controller *hose;
529 volatile void __iomem *addr;
530
531 hose = pci_bus_to_host(bus);
532 if (hose == NULL)
533 return PCIBIOS_DEVICE_NOT_FOUND;
534 if (offset >= 0x1000)
535 return PCIBIOS_BAD_REGISTER_NUMBER;
536 addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset);
537 if (!addr)
538 return PCIBIOS_DEVICE_NOT_FOUND;
539 /*
540 * Note: the caller has already checked that offset is
541 * suitably aligned and that len is 1, 2 or 4.
542 */
543 switch (len) {
544 case 1:
545 out_8(addr, val);
546 break;
547 case 2:
548 out_le16(addr, val);
549 break;
550 default:
551 out_le32(addr, val);
552 break;
553 }
554 return PCIBIOS_SUCCESSFUL;
555 }
556
557 static struct pci_ops u4_pcie_pci_ops =
558 {
559 .read = u4_pcie_read_config,
560 .write = u4_pcie_write_config,
561 };
562
563 #endif /* CONFIG_PPC64 */
564
565 #ifdef CONFIG_PPC32
566 /*
567 * For a bandit bridge, turn on cache coherency if necessary.
568 * N.B. we could clean this up using the hose ops directly.
569 */
init_bandit(struct pci_controller * bp)570 static void __init init_bandit(struct pci_controller *bp)
571 {
572 unsigned int vendev, magic;
573 int rev;
574
575 /* read the word at offset 0 in config space for device 11 */
576 out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + PCI_VENDOR_ID);
577 udelay(2);
578 vendev = in_le32(bp->cfg_data);
579 if (vendev == (PCI_DEVICE_ID_APPLE_BANDIT << 16) +
580 PCI_VENDOR_ID_APPLE) {
581 /* read the revision id */
582 out_le32(bp->cfg_addr,
583 (1UL << BANDIT_DEVNUM) + PCI_REVISION_ID);
584 udelay(2);
585 rev = in_8(bp->cfg_data);
586 if (rev != BANDIT_REVID)
587 printk(KERN_WARNING
588 "Unknown revision %d for bandit\n", rev);
589 } else if (vendev != (BANDIT_DEVID_2 << 16) + PCI_VENDOR_ID_APPLE) {
590 printk(KERN_WARNING "bandit isn't? (%x)\n", vendev);
591 return;
592 }
593
594 /* read the word at offset 0x50 */
595 out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + BANDIT_MAGIC);
596 udelay(2);
597 magic = in_le32(bp->cfg_data);
598 if ((magic & BANDIT_COHERENT) != 0)
599 return;
600 magic |= BANDIT_COHERENT;
601 udelay(2);
602 out_le32(bp->cfg_data, magic);
603 printk(KERN_INFO "Cache coherency enabled for bandit/PSX\n");
604 }
605
606 /*
607 * Tweak the PCI-PCI bridge chip on the blue & white G3s.
608 */
init_p2pbridge(void)609 static void __init init_p2pbridge(void)
610 {
611 struct device_node *p2pbridge;
612 struct pci_controller* hose;
613 u8 bus, devfn;
614 u16 val;
615
616 /* XXX it would be better here to identify the specific
617 PCI-PCI bridge chip we have. */
618 p2pbridge = of_find_node_by_name(NULL, "pci-bridge");
619 if (p2pbridge == NULL
620 || p2pbridge->parent == NULL
621 || strcmp(p2pbridge->parent->name, "pci") != 0)
622 goto done;
623 if (pci_device_from_OF_node(p2pbridge, &bus, &devfn) < 0) {
624 DBG("Can't find PCI infos for PCI<->PCI bridge\n");
625 goto done;
626 }
627 /* Warning: At this point, we have not yet renumbered all busses.
628 * So we must use OF walking to find out hose
629 */
630 hose = pci_find_hose_for_OF_device(p2pbridge);
631 if (!hose) {
632 DBG("Can't find hose for PCI<->PCI bridge\n");
633 goto done;
634 }
635 if (early_read_config_word(hose, bus, devfn,
636 PCI_BRIDGE_CONTROL, &val) < 0) {
637 printk(KERN_ERR "init_p2pbridge: couldn't read bridge"
638 " control\n");
639 goto done;
640 }
641 val &= ~PCI_BRIDGE_CTL_MASTER_ABORT;
642 early_write_config_word(hose, bus, devfn, PCI_BRIDGE_CONTROL, val);
643 done:
644 of_node_put(p2pbridge);
645 }
646
init_second_ohare(void)647 static void __init init_second_ohare(void)
648 {
649 struct device_node *np = of_find_node_by_name(NULL, "pci106b,7");
650 unsigned char bus, devfn;
651 unsigned short cmd;
652
653 if (np == NULL)
654 return;
655
656 /* This must run before we initialize the PICs since the second
657 * ohare hosts a PIC that will be accessed there.
658 */
659 if (pci_device_from_OF_node(np, &bus, &devfn) == 0) {
660 struct pci_controller* hose =
661 pci_find_hose_for_OF_device(np);
662 if (!hose) {
663 printk(KERN_ERR "Can't find PCI hose for OHare2 !\n");
664 of_node_put(np);
665 return;
666 }
667 early_read_config_word(hose, bus, devfn, PCI_COMMAND, &cmd);
668 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
669 cmd &= ~PCI_COMMAND_IO;
670 early_write_config_word(hose, bus, devfn, PCI_COMMAND, cmd);
671 }
672 has_second_ohare = 1;
673 of_node_put(np);
674 }
675
676 /*
677 * Some Apple desktop machines have a NEC PD720100A USB2 controller
678 * on the motherboard. Open Firmware, on these, will disable the
679 * EHCI part of it so it behaves like a pair of OHCI's. This fixup
680 * code re-enables it ;)
681 */
fixup_nec_usb2(void)682 static void __init fixup_nec_usb2(void)
683 {
684 struct device_node *nec;
685
686 for (nec = NULL; (nec = of_find_node_by_name(nec, "usb")) != NULL;) {
687 struct pci_controller *hose;
688 u32 data;
689 const u32 *prop;
690 u8 bus, devfn;
691
692 prop = of_get_property(nec, "vendor-id", NULL);
693 if (prop == NULL)
694 continue;
695 if (0x1033 != *prop)
696 continue;
697 prop = of_get_property(nec, "device-id", NULL);
698 if (prop == NULL)
699 continue;
700 if (0x0035 != *prop)
701 continue;
702 prop = of_get_property(nec, "reg", NULL);
703 if (prop == NULL)
704 continue;
705 devfn = (prop[0] >> 8) & 0xff;
706 bus = (prop[0] >> 16) & 0xff;
707 if (PCI_FUNC(devfn) != 0)
708 continue;
709 hose = pci_find_hose_for_OF_device(nec);
710 if (!hose)
711 continue;
712 early_read_config_dword(hose, bus, devfn, 0xe4, &data);
713 if (data & 1UL) {
714 printk("Found NEC PD720100A USB2 chip with disabled"
715 " EHCI, fixing up...\n");
716 data &= ~1UL;
717 early_write_config_dword(hose, bus, devfn, 0xe4, data);
718 }
719 }
720 }
721
setup_bandit(struct pci_controller * hose,struct resource * addr)722 static void __init setup_bandit(struct pci_controller *hose,
723 struct resource *addr)
724 {
725 hose->ops = ¯isc_pci_ops;
726 hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000);
727 hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000);
728 init_bandit(hose);
729 }
730
setup_uninorth(struct pci_controller * hose,struct resource * addr)731 static int __init setup_uninorth(struct pci_controller *hose,
732 struct resource *addr)
733 {
734 ppc_pci_add_flags(PPC_PCI_REASSIGN_ALL_BUS);
735 has_uninorth = 1;
736 hose->ops = ¯isc_pci_ops;
737 hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000);
738 hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000);
739 /* We "know" that the bridge at f2000000 has the PCI slots. */
740 return addr->start == 0xf2000000;
741 }
742 #endif /* CONFIG_PPC32 */
743
744 #ifdef CONFIG_PPC64
setup_u3_agp(struct pci_controller * hose)745 static void __init setup_u3_agp(struct pci_controller* hose)
746 {
747 /* On G5, we move AGP up to high bus number so we don't need
748 * to reassign bus numbers for HT. If we ever have P2P bridges
749 * on AGP, we'll have to move pci_assign_all_busses to the
750 * pci_controller structure so we enable it for AGP and not for
751 * HT childs.
752 * We hard code the address because of the different size of
753 * the reg address cell, we shall fix that by killing struct
754 * reg_property and using some accessor functions instead
755 */
756 hose->first_busno = 0xf0;
757 hose->last_busno = 0xff;
758 has_uninorth = 1;
759 hose->ops = ¯isc_pci_ops;
760 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);
761 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);
762 u3_agp = hose;
763 }
764
setup_u4_pcie(struct pci_controller * hose)765 static void __init setup_u4_pcie(struct pci_controller* hose)
766 {
767 /* We currently only implement the "non-atomic" config space, to
768 * be optimised later.
769 */
770 hose->ops = &u4_pcie_pci_ops;
771 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);
772 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);
773
774 /* The bus contains a bridge from root -> device, we need to
775 * make it visible on bus 0 so that we pick the right type
776 * of config cycles. If we didn't, we would have to force all
777 * config cycles to be type 1. So we override the "bus-range"
778 * property here
779 */
780 hose->first_busno = 0x00;
781 hose->last_busno = 0xff;
782 }
783
parse_region_decode(struct pci_controller * hose,u32 decode)784 static void __init parse_region_decode(struct pci_controller *hose,
785 u32 decode)
786 {
787 unsigned long base, end, next = -1;
788 int i, cur = -1;
789
790 /* Iterate through all bits. We ignore the last bit as this region is
791 * reserved for the ROM among other niceties
792 */
793 for (i = 0; i < 31; i++) {
794 if ((decode & (0x80000000 >> i)) == 0)
795 continue;
796 if (i < 16) {
797 base = 0xf0000000 | (((u32)i) << 24);
798 end = base + 0x00ffffff;
799 } else {
800 base = ((u32)i-16) << 28;
801 end = base + 0x0fffffff;
802 }
803 if (base != next) {
804 if (++cur >= 3) {
805 printk(KERN_WARNING "PCI: Too many ranges !\n");
806 break;
807 }
808 hose->mem_resources[cur].flags = IORESOURCE_MEM;
809 hose->mem_resources[cur].name = hose->dn->full_name;
810 hose->mem_resources[cur].start = base;
811 hose->mem_resources[cur].end = end;
812 DBG(" %d: 0x%08lx-0x%08lx\n", cur, base, end);
813 } else {
814 DBG(" : -0x%08lx\n", end);
815 hose->mem_resources[cur].end = end;
816 }
817 next = end + 1;
818 }
819 }
820
setup_u3_ht(struct pci_controller * hose)821 static void __init setup_u3_ht(struct pci_controller* hose)
822 {
823 struct device_node *np = hose->dn;
824 struct resource cfg_res, self_res;
825 u32 decode;
826
827 hose->ops = &u3_ht_pci_ops;
828
829 /* Get base addresses from OF tree
830 */
831 if (of_address_to_resource(np, 0, &cfg_res) ||
832 of_address_to_resource(np, 1, &self_res)) {
833 printk(KERN_ERR "PCI: Failed to get U3/U4 HT resources !\n");
834 return;
835 }
836
837 /* Map external cfg space access into cfg_data and self registers
838 * into cfg_addr
839 */
840 hose->cfg_data = ioremap(cfg_res.start, 0x02000000);
841 hose->cfg_addr = ioremap(self_res.start,
842 self_res.end - self_res.start + 1);
843
844 /*
845 * /ht node doesn't expose a "ranges" property, we read the register
846 * that controls the decoding logic and use that for memory regions.
847 * The IO region is hard coded since it is fixed in HW as well.
848 */
849 hose->io_base_phys = 0xf4000000;
850 hose->pci_io_size = 0x00400000;
851 hose->io_resource.name = np->full_name;
852 hose->io_resource.start = 0;
853 hose->io_resource.end = 0x003fffff;
854 hose->io_resource.flags = IORESOURCE_IO;
855 hose->pci_mem_offset = 0;
856 hose->first_busno = 0;
857 hose->last_busno = 0xef;
858
859 /* Note: fix offset when cfg_addr becomes a void * */
860 decode = in_be32(hose->cfg_addr + 0x80);
861
862 DBG("PCI: Apple HT bridge decode register: 0x%08x\n", decode);
863
864 /* NOTE: The decode register setup is a bit weird... region
865 * 0xf8000000 for example is marked as enabled in there while it's
866 & actually the memory controller registers.
867 * That means that we are incorrectly attributing it to HT.
868 *
869 * In a similar vein, region 0xf4000000 is actually the HT IO space but
870 * also marked as enabled in here and 0xf9000000 is used by some other
871 * internal bits of the northbridge.
872 *
873 * Unfortunately, we can't just mask out those bit as we would end
874 * up with more regions than we can cope (linux can only cope with
875 * 3 memory regions for a PHB at this stage).
876 *
877 * So for now, we just do a little hack. We happen to -know- that
878 * Apple firmware doesn't assign things below 0xfa000000 for that
879 * bridge anyway so we mask out all bits we don't want.
880 */
881 decode &= 0x003fffff;
882
883 /* Now parse the resulting bits and build resources */
884 parse_region_decode(hose, decode);
885 }
886 #endif /* CONFIG_PPC64 */
887
888 /*
889 * We assume that if we have a G3 powermac, we have one bridge called
890 * "pci" (a MPC106) and no bandit or chaos bridges, and contrariwise,
891 * if we have one or more bandit or chaos bridges, we don't have a MPC106.
892 */
pmac_add_bridge(struct device_node * dev)893 static int __init pmac_add_bridge(struct device_node *dev)
894 {
895 int len;
896 struct pci_controller *hose;
897 struct resource rsrc;
898 char *disp_name;
899 const int *bus_range;
900 int primary = 1, has_address = 0;
901
902 DBG("Adding PCI host bridge %s\n", dev->full_name);
903
904 /* Fetch host bridge registers address */
905 has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);
906
907 /* Get bus range if any */
908 bus_range = of_get_property(dev, "bus-range", &len);
909 if (bus_range == NULL || len < 2 * sizeof(int)) {
910 printk(KERN_WARNING "Can't get bus-range for %s, assume"
911 " bus 0\n", dev->full_name);
912 }
913
914 hose = pcibios_alloc_controller(dev);
915 if (!hose)
916 return -ENOMEM;
917 hose->first_busno = bus_range ? bus_range[0] : 0;
918 hose->last_busno = bus_range ? bus_range[1] : 0xff;
919
920 disp_name = NULL;
921
922 /* 64 bits only bridges */
923 #ifdef CONFIG_PPC64
924 if (of_device_is_compatible(dev, "u3-agp")) {
925 setup_u3_agp(hose);
926 disp_name = "U3-AGP";
927 primary = 0;
928 } else if (of_device_is_compatible(dev, "u3-ht")) {
929 setup_u3_ht(hose);
930 disp_name = "U3-HT";
931 primary = 1;
932 } else if (of_device_is_compatible(dev, "u4-pcie")) {
933 setup_u4_pcie(hose);
934 disp_name = "U4-PCIE";
935 primary = 0;
936 }
937 printk(KERN_INFO "Found %s PCI host bridge. Firmware bus number:"
938 " %d->%d\n", disp_name, hose->first_busno, hose->last_busno);
939 #endif /* CONFIG_PPC64 */
940
941 /* 32 bits only bridges */
942 #ifdef CONFIG_PPC32
943 if (of_device_is_compatible(dev, "uni-north")) {
944 primary = setup_uninorth(hose, &rsrc);
945 disp_name = "UniNorth";
946 } else if (strcmp(dev->name, "pci") == 0) {
947 /* XXX assume this is a mpc106 (grackle) */
948 setup_grackle(hose);
949 disp_name = "Grackle (MPC106)";
950 } else if (strcmp(dev->name, "bandit") == 0) {
951 setup_bandit(hose, &rsrc);
952 disp_name = "Bandit";
953 } else if (strcmp(dev->name, "chaos") == 0) {
954 setup_chaos(hose, &rsrc);
955 disp_name = "Chaos";
956 primary = 0;
957 }
958 printk(KERN_INFO "Found %s PCI host bridge at 0x%016llx. "
959 "Firmware bus number: %d->%d\n",
960 disp_name, (unsigned long long)rsrc.start, hose->first_busno,
961 hose->last_busno);
962 #endif /* CONFIG_PPC32 */
963
964 DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
965 hose, hose->cfg_addr, hose->cfg_data);
966
967 /* Interpret the "ranges" property */
968 /* This also maps the I/O region and sets isa_io/mem_base */
969 pci_process_bridge_OF_ranges(hose, dev, primary);
970
971 /* Fixup "bus-range" OF property */
972 fixup_bus_range(dev);
973
974 return 0;
975 }
976
pmac_pci_irq_fixup(struct pci_dev * dev)977 void __devinit pmac_pci_irq_fixup(struct pci_dev *dev)
978 {
979 #ifdef CONFIG_PPC32
980 /* Fixup interrupt for the modem/ethernet combo controller.
981 * on machines with a second ohare chip.
982 * The number in the device tree (27) is bogus (correct for
983 * the ethernet-only board but not the combo ethernet/modem
984 * board). The real interrupt is 28 on the second controller
985 * -> 28+32 = 60.
986 */
987 if (has_second_ohare &&
988 dev->vendor == PCI_VENDOR_ID_DEC &&
989 dev->device == PCI_DEVICE_ID_DEC_TULIP_PLUS) {
990 dev->irq = irq_create_mapping(NULL, 60);
991 set_irq_type(dev->irq, IRQ_TYPE_LEVEL_LOW);
992 }
993 #endif /* CONFIG_PPC32 */
994 }
995
pmac_pci_init(void)996 void __init pmac_pci_init(void)
997 {
998 struct device_node *np, *root;
999 struct device_node *ht = NULL;
1000
1001 ppc_pci_set_flags(PPC_PCI_CAN_SKIP_ISA_ALIGN);
1002
1003 root = of_find_node_by_path("/");
1004 if (root == NULL) {
1005 printk(KERN_CRIT "pmac_pci_init: can't find root "
1006 "of device tree\n");
1007 return;
1008 }
1009 for (np = NULL; (np = of_get_next_child(root, np)) != NULL;) {
1010 if (np->name == NULL)
1011 continue;
1012 if (strcmp(np->name, "bandit") == 0
1013 || strcmp(np->name, "chaos") == 0
1014 || strcmp(np->name, "pci") == 0) {
1015 if (pmac_add_bridge(np) == 0)
1016 of_node_get(np);
1017 }
1018 if (strcmp(np->name, "ht") == 0) {
1019 of_node_get(np);
1020 ht = np;
1021 }
1022 }
1023 of_node_put(root);
1024
1025 #ifdef CONFIG_PPC64
1026 /* Probe HT last as it relies on the agp resources to be already
1027 * setup
1028 */
1029 if (ht && pmac_add_bridge(ht) != 0)
1030 of_node_put(ht);
1031
1032 /* Setup the linkage between OF nodes and PHBs */
1033 pci_devs_phb_init();
1034
1035 /* Fixup the PCI<->OF mapping for U3 AGP due to bus renumbering. We
1036 * assume there is no P2P bridge on the AGP bus, which should be a
1037 * safe assumptions for now. We should do something better in the
1038 * future though
1039 */
1040 if (u3_agp) {
1041 struct device_node *np = u3_agp->dn;
1042 PCI_DN(np)->busno = 0xf0;
1043 for (np = np->child; np; np = np->sibling)
1044 PCI_DN(np)->busno = 0xf0;
1045 }
1046 /* pmac_check_ht_link(); */
1047
1048 /* We can allocate missing resources if any */
1049 pci_probe_only = 0;
1050
1051 #else /* CONFIG_PPC64 */
1052 init_p2pbridge();
1053 init_second_ohare();
1054 fixup_nec_usb2();
1055
1056 /* We are still having some issues with the Xserve G4, enabling
1057 * some offset between bus number and domains for now when we
1058 * assign all busses should help for now
1059 */
1060 if (ppc_pci_has_flag(PPC_PCI_REASSIGN_ALL_BUS))
1061 pcibios_assign_bus_offset = 0x10;
1062 #endif
1063 }
1064
1065 #ifdef CONFIG_PPC32
pmac_pci_enable_device_hook(struct pci_dev * dev)1066 int pmac_pci_enable_device_hook(struct pci_dev *dev)
1067 {
1068 struct device_node* node;
1069 int updatecfg = 0;
1070 int uninorth_child;
1071
1072 node = pci_device_to_OF_node(dev);
1073
1074 /* We don't want to enable USB controllers absent from the OF tree
1075 * (iBook second controller)
1076 */
1077 if (dev->vendor == PCI_VENDOR_ID_APPLE
1078 && dev->class == PCI_CLASS_SERIAL_USB_OHCI
1079 && !node) {
1080 printk(KERN_INFO "Apple USB OHCI %s disabled by firmware\n",
1081 pci_name(dev));
1082 return -EINVAL;
1083 }
1084
1085 if (!node)
1086 return 0;
1087
1088 uninorth_child = node->parent &&
1089 of_device_is_compatible(node->parent, "uni-north");
1090
1091 /* Firewire & GMAC were disabled after PCI probe, the driver is
1092 * claiming them, we must re-enable them now.
1093 */
1094 if (uninorth_child && !strcmp(node->name, "firewire") &&
1095 (of_device_is_compatible(node, "pci106b,18") ||
1096 of_device_is_compatible(node, "pci106b,30") ||
1097 of_device_is_compatible(node, "pci11c1,5811"))) {
1098 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, node, 0, 1);
1099 pmac_call_feature(PMAC_FTR_1394_ENABLE, node, 0, 1);
1100 updatecfg = 1;
1101 }
1102 if (uninorth_child && !strcmp(node->name, "ethernet") &&
1103 of_device_is_compatible(node, "gmac")) {
1104 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, node, 0, 1);
1105 updatecfg = 1;
1106 }
1107
1108 /*
1109 * Fixup various header fields on 32 bits. We don't do that on
1110 * 64 bits as some of these have strange values behind the HT
1111 * bridge and we must not, for example, enable MWI or set the
1112 * cache line size on them.
1113 */
1114 if (updatecfg) {
1115 u16 cmd;
1116
1117 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1118 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
1119 | PCI_COMMAND_INVALIDATE;
1120 pci_write_config_word(dev, PCI_COMMAND, cmd);
1121 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 16);
1122
1123 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
1124 L1_CACHE_BYTES >> 2);
1125 }
1126
1127 return 0;
1128 }
1129
pmac_pci_fixup_ohci(struct pci_dev * dev)1130 void __devinit pmac_pci_fixup_ohci(struct pci_dev *dev)
1131 {
1132 struct device_node *node = pci_device_to_OF_node(dev);
1133
1134 /* We don't want to assign resources to USB controllers
1135 * absent from the OF tree (iBook second controller)
1136 */
1137 if (dev->class == PCI_CLASS_SERIAL_USB_OHCI && !node)
1138 dev->resource[0].flags = 0;
1139 }
1140 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_APPLE, PCI_ANY_ID, pmac_pci_fixup_ohci);
1141
1142 /* We power down some devices after they have been probed. They'll
1143 * be powered back on later on
1144 */
pmac_pcibios_after_init(void)1145 void __init pmac_pcibios_after_init(void)
1146 {
1147 struct device_node* nd;
1148
1149 for_each_node_by_name(nd, "firewire") {
1150 if (nd->parent && (of_device_is_compatible(nd, "pci106b,18") ||
1151 of_device_is_compatible(nd, "pci106b,30") ||
1152 of_device_is_compatible(nd, "pci11c1,5811"))
1153 && of_device_is_compatible(nd->parent, "uni-north")) {
1154 pmac_call_feature(PMAC_FTR_1394_ENABLE, nd, 0, 0);
1155 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, nd, 0, 0);
1156 }
1157 }
1158 of_node_put(nd);
1159 for_each_node_by_name(nd, "ethernet") {
1160 if (nd->parent && of_device_is_compatible(nd, "gmac")
1161 && of_device_is_compatible(nd->parent, "uni-north"))
1162 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, nd, 0, 0);
1163 }
1164 of_node_put(nd);
1165 }
1166
pmac_pci_fixup_cardbus(struct pci_dev * dev)1167 void pmac_pci_fixup_cardbus(struct pci_dev* dev)
1168 {
1169 if (!machine_is(powermac))
1170 return;
1171 /*
1172 * Fix the interrupt routing on the various cardbus bridges
1173 * used on powerbooks
1174 */
1175 if (dev->vendor != PCI_VENDOR_ID_TI)
1176 return;
1177 if (dev->device == PCI_DEVICE_ID_TI_1130 ||
1178 dev->device == PCI_DEVICE_ID_TI_1131) {
1179 u8 val;
1180 /* Enable PCI interrupt */
1181 if (pci_read_config_byte(dev, 0x91, &val) == 0)
1182 pci_write_config_byte(dev, 0x91, val | 0x30);
1183 /* Disable ISA interrupt mode */
1184 if (pci_read_config_byte(dev, 0x92, &val) == 0)
1185 pci_write_config_byte(dev, 0x92, val & ~0x06);
1186 }
1187 if (dev->device == PCI_DEVICE_ID_TI_1210 ||
1188 dev->device == PCI_DEVICE_ID_TI_1211 ||
1189 dev->device == PCI_DEVICE_ID_TI_1410 ||
1190 dev->device == PCI_DEVICE_ID_TI_1510) {
1191 u8 val;
1192 /* 0x8c == TI122X_IRQMUX, 2 says to route the INTA
1193 signal out the MFUNC0 pin */
1194 if (pci_read_config_byte(dev, 0x8c, &val) == 0)
1195 pci_write_config_byte(dev, 0x8c, (val & ~0x0f) | 2);
1196 /* Disable ISA interrupt mode */
1197 if (pci_read_config_byte(dev, 0x92, &val) == 0)
1198 pci_write_config_byte(dev, 0x92, val & ~0x06);
1199 }
1200 }
1201
1202 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_ANY_ID, pmac_pci_fixup_cardbus);
1203
pmac_pci_fixup_pciata(struct pci_dev * dev)1204 void pmac_pci_fixup_pciata(struct pci_dev* dev)
1205 {
1206 u8 progif = 0;
1207
1208 /*
1209 * On PowerMacs, we try to switch any PCI ATA controller to
1210 * fully native mode
1211 */
1212 if (!machine_is(powermac))
1213 return;
1214
1215 /* Some controllers don't have the class IDE */
1216 if (dev->vendor == PCI_VENDOR_ID_PROMISE)
1217 switch(dev->device) {
1218 case PCI_DEVICE_ID_PROMISE_20246:
1219 case PCI_DEVICE_ID_PROMISE_20262:
1220 case PCI_DEVICE_ID_PROMISE_20263:
1221 case PCI_DEVICE_ID_PROMISE_20265:
1222 case PCI_DEVICE_ID_PROMISE_20267:
1223 case PCI_DEVICE_ID_PROMISE_20268:
1224 case PCI_DEVICE_ID_PROMISE_20269:
1225 case PCI_DEVICE_ID_PROMISE_20270:
1226 case PCI_DEVICE_ID_PROMISE_20271:
1227 case PCI_DEVICE_ID_PROMISE_20275:
1228 case PCI_DEVICE_ID_PROMISE_20276:
1229 case PCI_DEVICE_ID_PROMISE_20277:
1230 goto good;
1231 }
1232 /* Others, check PCI class */
1233 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
1234 return;
1235 good:
1236 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1237 if ((progif & 5) != 5) {
1238 printk(KERN_INFO "PCI: %s Forcing PCI IDE into native mode\n",
1239 pci_name(dev));
1240 (void) pci_write_config_byte(dev, PCI_CLASS_PROG, progif|5);
1241 if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) ||
1242 (progif & 5) != 5)
1243 printk(KERN_ERR "Rewrite of PROGIF failed !\n");
1244 else {
1245 /* Clear IO BARs, they will be reassigned */
1246 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0);
1247 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0);
1248 pci_write_config_dword(dev, PCI_BASE_ADDRESS_2, 0);
1249 pci_write_config_dword(dev, PCI_BASE_ADDRESS_3, 0);
1250 }
1251 }
1252 }
1253 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, pmac_pci_fixup_pciata);
1254 #endif /* CONFIG_PPC32 */
1255
1256 /*
1257 * Disable second function on K2-SATA, it's broken
1258 * and disable IO BARs on first one
1259 */
fixup_k2_sata(struct pci_dev * dev)1260 static void fixup_k2_sata(struct pci_dev* dev)
1261 {
1262 int i;
1263 u16 cmd;
1264
1265 if (PCI_FUNC(dev->devfn) > 0) {
1266 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1267 cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
1268 pci_write_config_word(dev, PCI_COMMAND, cmd);
1269 for (i = 0; i < 6; i++) {
1270 dev->resource[i].start = dev->resource[i].end = 0;
1271 dev->resource[i].flags = 0;
1272 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i,
1273 0);
1274 }
1275 } else {
1276 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1277 cmd &= ~PCI_COMMAND_IO;
1278 pci_write_config_word(dev, PCI_COMMAND, cmd);
1279 for (i = 0; i < 5; i++) {
1280 dev->resource[i].start = dev->resource[i].end = 0;
1281 dev->resource[i].flags = 0;
1282 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i,
1283 0);
1284 }
1285 }
1286 }
1287 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 0x0240, fixup_k2_sata);
1288
1289