1 /**************************************************************************** 2 * Driver for Solarflare Solarstorm network controllers and boards 3 * Copyright 2005-2006 Fen Systems Ltd. 4 * Copyright 2006-2008 Solarflare Communications Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published 8 * by the Free Software Foundation, incorporated herein by reference. 9 */ 10 11 #ifndef EFX_FALCON_HWDEFS_H 12 #define EFX_FALCON_HWDEFS_H 13 14 /* 15 * Falcon hardware value definitions. 16 * Falcon is the internal codename for the SFC4000 controller that is 17 * present in SFE400X evaluation boards 18 */ 19 20 /************************************************************************** 21 * 22 * Falcon registers 23 * 24 ************************************************************************** 25 */ 26 27 /* Address region register */ 28 #define ADR_REGION_REG_KER 0x00 29 #define ADR_REGION0_LBN 0 30 #define ADR_REGION0_WIDTH 18 31 #define ADR_REGION1_LBN 32 32 #define ADR_REGION1_WIDTH 18 33 #define ADR_REGION2_LBN 64 34 #define ADR_REGION2_WIDTH 18 35 #define ADR_REGION3_LBN 96 36 #define ADR_REGION3_WIDTH 18 37 38 /* Interrupt enable register */ 39 #define INT_EN_REG_KER 0x0010 40 #define KER_INT_KER_LBN 3 41 #define KER_INT_KER_WIDTH 1 42 #define DRV_INT_EN_KER_LBN 0 43 #define DRV_INT_EN_KER_WIDTH 1 44 45 /* Interrupt status address register */ 46 #define INT_ADR_REG_KER 0x0030 47 #define NORM_INT_VEC_DIS_KER_LBN 64 48 #define NORM_INT_VEC_DIS_KER_WIDTH 1 49 #define INT_ADR_KER_LBN 0 50 #define INT_ADR_KER_WIDTH EFX_DMA_TYPE_WIDTH(64) /* not 46 for this one */ 51 52 /* Interrupt status register (B0 only) */ 53 #define INT_ISR0_B0 0x90 54 #define INT_ISR1_B0 0xA0 55 56 /* Interrupt acknowledge register (A0/A1 only) */ 57 #define INT_ACK_REG_KER_A1 0x0050 58 #define INT_ACK_DUMMY_DATA_LBN 0 59 #define INT_ACK_DUMMY_DATA_WIDTH 32 60 61 /* Interrupt acknowledge work-around register (A0/A1 only )*/ 62 #define WORK_AROUND_BROKEN_PCI_READS_REG_KER_A1 0x0070 63 64 /* SPI host command register */ 65 #define EE_SPI_HCMD_REG_KER 0x0100 66 #define EE_SPI_HCMD_CMD_EN_LBN 31 67 #define EE_SPI_HCMD_CMD_EN_WIDTH 1 68 #define EE_WR_TIMER_ACTIVE_LBN 28 69 #define EE_WR_TIMER_ACTIVE_WIDTH 1 70 #define EE_SPI_HCMD_SF_SEL_LBN 24 71 #define EE_SPI_HCMD_SF_SEL_WIDTH 1 72 #define EE_SPI_EEPROM 0 73 #define EE_SPI_FLASH 1 74 #define EE_SPI_HCMD_DABCNT_LBN 16 75 #define EE_SPI_HCMD_DABCNT_WIDTH 5 76 #define EE_SPI_HCMD_READ_LBN 15 77 #define EE_SPI_HCMD_READ_WIDTH 1 78 #define EE_SPI_READ 1 79 #define EE_SPI_WRITE 0 80 #define EE_SPI_HCMD_DUBCNT_LBN 12 81 #define EE_SPI_HCMD_DUBCNT_WIDTH 2 82 #define EE_SPI_HCMD_ADBCNT_LBN 8 83 #define EE_SPI_HCMD_ADBCNT_WIDTH 2 84 #define EE_SPI_HCMD_ENC_LBN 0 85 #define EE_SPI_HCMD_ENC_WIDTH 8 86 87 /* SPI host address register */ 88 #define EE_SPI_HADR_REG_KER 0x0110 89 #define EE_SPI_HADR_ADR_LBN 0 90 #define EE_SPI_HADR_ADR_WIDTH 24 91 92 /* SPI host data register */ 93 #define EE_SPI_HDATA_REG_KER 0x0120 94 95 /* SPI/VPD config register */ 96 #define EE_VPD_CFG_REG_KER 0x0140 97 #define EE_VPD_EN_LBN 0 98 #define EE_VPD_EN_WIDTH 1 99 #define EE_VPD_EN_AD9_MODE_LBN 1 100 #define EE_VPD_EN_AD9_MODE_WIDTH 1 101 #define EE_EE_CLOCK_DIV_LBN 112 102 #define EE_EE_CLOCK_DIV_WIDTH 7 103 #define EE_SF_CLOCK_DIV_LBN 120 104 #define EE_SF_CLOCK_DIV_WIDTH 7 105 106 /* PCIE CORE ACCESS REG */ 107 #define PCIE_CORE_ADDR_PCIE_DEVICE_CTRL_STAT 0x68 108 #define PCIE_CORE_ADDR_PCIE_LINK_CTRL_STAT 0x70 109 #define PCIE_CORE_ADDR_ACK_RPL_TIMER 0x700 110 #define PCIE_CORE_ADDR_ACK_FREQ 0x70C 111 112 /* NIC status register */ 113 #define NIC_STAT_REG 0x0200 114 #define EE_STRAP_EN_LBN 31 115 #define EE_STRAP_EN_WIDTH 1 116 #define EE_STRAP_OVR_LBN 24 117 #define EE_STRAP_OVR_WIDTH 4 118 #define ONCHIP_SRAM_LBN 16 119 #define ONCHIP_SRAM_WIDTH 1 120 #define SF_PRST_LBN 9 121 #define SF_PRST_WIDTH 1 122 #define EE_PRST_LBN 8 123 #define EE_PRST_WIDTH 1 124 #define STRAP_PINS_LBN 0 125 #define STRAP_PINS_WIDTH 3 126 /* These bit definitions are extrapolated from the list of numerical 127 * values for STRAP_PINS. 128 */ 129 #define STRAP_10G_LBN 2 130 #define STRAP_10G_WIDTH 1 131 #define STRAP_PCIE_LBN 0 132 #define STRAP_PCIE_WIDTH 1 133 134 #define BOOTED_USING_NVDEVICE_LBN 3 135 #define BOOTED_USING_NVDEVICE_WIDTH 1 136 137 /* GPIO control register */ 138 #define GPIO_CTL_REG_KER 0x0210 139 #define GPIO_USE_NIC_CLK_LBN (30) 140 #define GPIO_USE_NIC_CLK_WIDTH (1) 141 #define GPIO_OUTPUTS_LBN (16) 142 #define GPIO_OUTPUTS_WIDTH (4) 143 #define GPIO_INPUTS_LBN (8) 144 #define GPIO_DIRECTION_LBN (24) 145 #define GPIO_DIRECTION_WIDTH (4) 146 #define GPIO_DIRECTION_OUT (1) 147 #define GPIO_SRAM_SLEEP (1 << 1) 148 149 #define GPIO3_OEN_LBN (GPIO_DIRECTION_LBN + 3) 150 #define GPIO3_OEN_WIDTH 1 151 #define GPIO2_OEN_LBN (GPIO_DIRECTION_LBN + 2) 152 #define GPIO2_OEN_WIDTH 1 153 #define GPIO1_OEN_LBN (GPIO_DIRECTION_LBN + 1) 154 #define GPIO1_OEN_WIDTH 1 155 #define GPIO0_OEN_LBN (GPIO_DIRECTION_LBN + 0) 156 #define GPIO0_OEN_WIDTH 1 157 158 #define GPIO3_OUT_LBN (GPIO_OUTPUTS_LBN + 3) 159 #define GPIO3_OUT_WIDTH 1 160 #define GPIO2_OUT_LBN (GPIO_OUTPUTS_LBN + 2) 161 #define GPIO2_OUT_WIDTH 1 162 #define GPIO1_OUT_LBN (GPIO_OUTPUTS_LBN + 1) 163 #define GPIO1_OUT_WIDTH 1 164 #define GPIO0_OUT_LBN (GPIO_OUTPUTS_LBN + 0) 165 #define GPIO0_OUT_WIDTH 1 166 167 #define GPIO3_IN_LBN (GPIO_INPUTS_LBN + 3) 168 #define GPIO3_IN_WIDTH 1 169 #define GPIO2_IN_WIDTH 1 170 #define GPIO1_IN_WIDTH 1 171 #define GPIO0_IN_LBN (GPIO_INPUTS_LBN + 0) 172 #define GPIO0_IN_WIDTH 1 173 174 /* Global control register */ 175 #define GLB_CTL_REG_KER 0x0220 176 #define EXT_PHY_RST_CTL_LBN 63 177 #define EXT_PHY_RST_CTL_WIDTH 1 178 #define PCIE_SD_RST_CTL_LBN 61 179 #define PCIE_SD_RST_CTL_WIDTH 1 180 181 #define PCIE_NSTCK_RST_CTL_LBN 58 182 #define PCIE_NSTCK_RST_CTL_WIDTH 1 183 #define PCIE_CORE_RST_CTL_LBN 57 184 #define PCIE_CORE_RST_CTL_WIDTH 1 185 #define EE_RST_CTL_LBN 49 186 #define EE_RST_CTL_WIDTH 1 187 #define RST_XGRX_LBN 24 188 #define RST_XGRX_WIDTH 1 189 #define RST_XGTX_LBN 23 190 #define RST_XGTX_WIDTH 1 191 #define RST_EM_LBN 22 192 #define RST_EM_WIDTH 1 193 #define EXT_PHY_RST_DUR_LBN 1 194 #define EXT_PHY_RST_DUR_WIDTH 3 195 #define SWRST_LBN 0 196 #define SWRST_WIDTH 1 197 #define INCLUDE_IN_RESET 0 198 #define EXCLUDE_FROM_RESET 1 199 200 /* Fatal interrupt register */ 201 #define FATAL_INTR_REG_KER 0x0230 202 #define RBUF_OWN_INT_KER_EN_LBN 39 203 #define RBUF_OWN_INT_KER_EN_WIDTH 1 204 #define TBUF_OWN_INT_KER_EN_LBN 38 205 #define TBUF_OWN_INT_KER_EN_WIDTH 1 206 #define ILL_ADR_INT_KER_EN_LBN 33 207 #define ILL_ADR_INT_KER_EN_WIDTH 1 208 #define MEM_PERR_INT_KER_LBN 8 209 #define MEM_PERR_INT_KER_WIDTH 1 210 #define INT_KER_ERROR_LBN 0 211 #define INT_KER_ERROR_WIDTH 12 212 213 #define DP_CTRL_REG 0x250 214 #define FLS_EVQ_ID_LBN 0 215 #define FLS_EVQ_ID_WIDTH 11 216 217 #define MEM_STAT_REG_KER 0x260 218 219 /* Debug probe register */ 220 #define DEBUG_BLK_SEL_MISC 7 221 #define DEBUG_BLK_SEL_SERDES 6 222 #define DEBUG_BLK_SEL_EM 5 223 #define DEBUG_BLK_SEL_SR 4 224 #define DEBUG_BLK_SEL_EV 3 225 #define DEBUG_BLK_SEL_RX 2 226 #define DEBUG_BLK_SEL_TX 1 227 #define DEBUG_BLK_SEL_BIU 0 228 229 /* FPGA build version */ 230 #define ALTERA_BUILD_REG_KER 0x0300 231 #define VER_ALL_LBN 0 232 #define VER_ALL_WIDTH 32 233 234 /* Spare EEPROM bits register (flash 0x390) */ 235 #define SPARE_REG_KER 0x310 236 #define MEM_PERR_EN_TX_DATA_LBN 72 237 #define MEM_PERR_EN_TX_DATA_WIDTH 2 238 239 /* Timer table for kernel access */ 240 #define TIMER_CMD_REG_KER 0x420 241 #define TIMER_MODE_LBN 12 242 #define TIMER_MODE_WIDTH 2 243 #define TIMER_MODE_DIS 0 244 #define TIMER_MODE_INT_HLDOFF 2 245 #define TIMER_VAL_LBN 0 246 #define TIMER_VAL_WIDTH 12 247 248 /* Driver generated event register */ 249 #define DRV_EV_REG_KER 0x440 250 #define DRV_EV_QID_LBN 64 251 #define DRV_EV_QID_WIDTH 12 252 #define DRV_EV_DATA_LBN 0 253 #define DRV_EV_DATA_WIDTH 64 254 255 /* Buffer table configuration register */ 256 #define BUF_TBL_CFG_REG_KER 0x600 257 #define BUF_TBL_MODE_LBN 3 258 #define BUF_TBL_MODE_WIDTH 1 259 #define BUF_TBL_MODE_HALF 0 260 #define BUF_TBL_MODE_FULL 1 261 262 /* SRAM receive descriptor cache configuration register */ 263 #define SRM_RX_DC_CFG_REG_KER 0x610 264 #define SRM_RX_DC_BASE_ADR_LBN 0 265 #define SRM_RX_DC_BASE_ADR_WIDTH 21 266 267 /* SRAM transmit descriptor cache configuration register */ 268 #define SRM_TX_DC_CFG_REG_KER 0x620 269 #define SRM_TX_DC_BASE_ADR_LBN 0 270 #define SRM_TX_DC_BASE_ADR_WIDTH 21 271 272 /* SRAM configuration register */ 273 #define SRM_CFG_REG_KER 0x630 274 #define SRAM_OOB_BT_INIT_EN_LBN 3 275 #define SRAM_OOB_BT_INIT_EN_WIDTH 1 276 #define SRM_NUM_BANKS_AND_BANK_SIZE_LBN 0 277 #define SRM_NUM_BANKS_AND_BANK_SIZE_WIDTH 3 278 #define SRM_NB_BSZ_1BANKS_2M 0 279 #define SRM_NB_BSZ_1BANKS_4M 1 280 #define SRM_NB_BSZ_1BANKS_8M 2 281 #define SRM_NB_BSZ_DEFAULT 3 /* char driver will set the default */ 282 #define SRM_NB_BSZ_2BANKS_4M 4 283 #define SRM_NB_BSZ_2BANKS_8M 5 284 #define SRM_NB_BSZ_2BANKS_16M 6 285 #define SRM_NB_BSZ_RESERVED 7 286 287 /* Special buffer table update register */ 288 #define BUF_TBL_UPD_REG_KER 0x0650 289 #define BUF_UPD_CMD_LBN 63 290 #define BUF_UPD_CMD_WIDTH 1 291 #define BUF_CLR_CMD_LBN 62 292 #define BUF_CLR_CMD_WIDTH 1 293 #define BUF_CLR_END_ID_LBN 32 294 #define BUF_CLR_END_ID_WIDTH 20 295 #define BUF_CLR_START_ID_LBN 0 296 #define BUF_CLR_START_ID_WIDTH 20 297 298 /* Receive configuration register */ 299 #define RX_CFG_REG_KER 0x800 300 301 /* B0 */ 302 #define RX_INGR_EN_B0_LBN 47 303 #define RX_INGR_EN_B0_WIDTH 1 304 #define RX_DESC_PUSH_EN_B0_LBN 43 305 #define RX_DESC_PUSH_EN_B0_WIDTH 1 306 #define RX_XON_TX_TH_B0_LBN 33 307 #define RX_XON_TX_TH_B0_WIDTH 5 308 #define RX_XOFF_TX_TH_B0_LBN 28 309 #define RX_XOFF_TX_TH_B0_WIDTH 5 310 #define RX_USR_BUF_SIZE_B0_LBN 19 311 #define RX_USR_BUF_SIZE_B0_WIDTH 9 312 #define RX_XON_MAC_TH_B0_LBN 10 313 #define RX_XON_MAC_TH_B0_WIDTH 9 314 #define RX_XOFF_MAC_TH_B0_LBN 1 315 #define RX_XOFF_MAC_TH_B0_WIDTH 9 316 #define RX_XOFF_MAC_EN_B0_LBN 0 317 #define RX_XOFF_MAC_EN_B0_WIDTH 1 318 319 /* A1 */ 320 #define RX_DESC_PUSH_EN_A1_LBN 35 321 #define RX_DESC_PUSH_EN_A1_WIDTH 1 322 #define RX_XON_TX_TH_A1_LBN 25 323 #define RX_XON_TX_TH_A1_WIDTH 5 324 #define RX_XOFF_TX_TH_A1_LBN 20 325 #define RX_XOFF_TX_TH_A1_WIDTH 5 326 #define RX_USR_BUF_SIZE_A1_LBN 11 327 #define RX_USR_BUF_SIZE_A1_WIDTH 9 328 #define RX_XON_MAC_TH_A1_LBN 6 329 #define RX_XON_MAC_TH_A1_WIDTH 5 330 #define RX_XOFF_MAC_TH_A1_LBN 1 331 #define RX_XOFF_MAC_TH_A1_WIDTH 5 332 #define RX_XOFF_MAC_EN_A1_LBN 0 333 #define RX_XOFF_MAC_EN_A1_WIDTH 1 334 335 /* Receive filter control register */ 336 #define RX_FILTER_CTL_REG 0x810 337 #define UDP_FULL_SRCH_LIMIT_LBN 32 338 #define UDP_FULL_SRCH_LIMIT_WIDTH 8 339 #define NUM_KER_LBN 24 340 #define NUM_KER_WIDTH 2 341 #define UDP_WILD_SRCH_LIMIT_LBN 16 342 #define UDP_WILD_SRCH_LIMIT_WIDTH 8 343 #define TCP_WILD_SRCH_LIMIT_LBN 8 344 #define TCP_WILD_SRCH_LIMIT_WIDTH 8 345 #define TCP_FULL_SRCH_LIMIT_LBN 0 346 #define TCP_FULL_SRCH_LIMIT_WIDTH 8 347 348 /* RX queue flush register */ 349 #define RX_FLUSH_DESCQ_REG_KER 0x0820 350 #define RX_FLUSH_DESCQ_CMD_LBN 24 351 #define RX_FLUSH_DESCQ_CMD_WIDTH 1 352 #define RX_FLUSH_DESCQ_LBN 0 353 #define RX_FLUSH_DESCQ_WIDTH 12 354 355 /* Receive descriptor update register */ 356 #define RX_DESC_UPD_REG_KER_DWORD (0x830 + 12) 357 #define RX_DESC_WPTR_DWORD_LBN 0 358 #define RX_DESC_WPTR_DWORD_WIDTH 12 359 360 /* Receive descriptor cache configuration register */ 361 #define RX_DC_CFG_REG_KER 0x840 362 #define RX_DC_SIZE_LBN 0 363 #define RX_DC_SIZE_WIDTH 2 364 365 #define RX_DC_PF_WM_REG_KER 0x850 366 #define RX_DC_PF_LWM_LBN 0 367 #define RX_DC_PF_LWM_WIDTH 6 368 369 /* RX no descriptor drop counter */ 370 #define RX_NODESC_DROP_REG_KER 0x880 371 #define RX_NODESC_DROP_CNT_LBN 0 372 #define RX_NODESC_DROP_CNT_WIDTH 16 373 374 /* RX black magic register */ 375 #define RX_SELF_RST_REG_KER 0x890 376 #define RX_ISCSI_DIS_LBN 17 377 #define RX_ISCSI_DIS_WIDTH 1 378 #define RX_NODESC_WAIT_DIS_LBN 9 379 #define RX_NODESC_WAIT_DIS_WIDTH 1 380 #define RX_RECOVERY_EN_LBN 8 381 #define RX_RECOVERY_EN_WIDTH 1 382 383 /* TX queue flush register */ 384 #define TX_FLUSH_DESCQ_REG_KER 0x0a00 385 #define TX_FLUSH_DESCQ_CMD_LBN 12 386 #define TX_FLUSH_DESCQ_CMD_WIDTH 1 387 #define TX_FLUSH_DESCQ_LBN 0 388 #define TX_FLUSH_DESCQ_WIDTH 12 389 390 /* Transmit descriptor update register */ 391 #define TX_DESC_UPD_REG_KER_DWORD (0xa10 + 12) 392 #define TX_DESC_WPTR_DWORD_LBN 0 393 #define TX_DESC_WPTR_DWORD_WIDTH 12 394 395 /* Transmit descriptor cache configuration register */ 396 #define TX_DC_CFG_REG_KER 0xa20 397 #define TX_DC_SIZE_LBN 0 398 #define TX_DC_SIZE_WIDTH 2 399 400 /* Transmit checksum configuration register (A0/A1 only) */ 401 #define TX_CHKSM_CFG_REG_KER_A1 0xa30 402 403 /* Transmit configuration register */ 404 #define TX_CFG_REG_KER 0xa50 405 #define TX_NO_EOP_DISC_EN_LBN 5 406 #define TX_NO_EOP_DISC_EN_WIDTH 1 407 408 /* Transmit configuration register 2 */ 409 #define TX_CFG2_REG_KER 0xa80 410 #define TX_CSR_PUSH_EN_LBN 89 411 #define TX_CSR_PUSH_EN_WIDTH 1 412 #define TX_RX_SPACER_LBN 64 413 #define TX_RX_SPACER_WIDTH 8 414 #define TX_SW_EV_EN_LBN 59 415 #define TX_SW_EV_EN_WIDTH 1 416 #define TX_RX_SPACER_EN_LBN 57 417 #define TX_RX_SPACER_EN_WIDTH 1 418 #define TX_PREF_THRESHOLD_LBN 19 419 #define TX_PREF_THRESHOLD_WIDTH 2 420 #define TX_ONE_PKT_PER_Q_LBN 18 421 #define TX_ONE_PKT_PER_Q_WIDTH 1 422 #define TX_DIS_NON_IP_EV_LBN 17 423 #define TX_DIS_NON_IP_EV_WIDTH 1 424 #define TX_FLUSH_MIN_LEN_EN_B0_LBN 7 425 #define TX_FLUSH_MIN_LEN_EN_B0_WIDTH 1 426 427 /* PHY management transmit data register */ 428 #define MD_TXD_REG_KER 0xc00 429 #define MD_TXD_LBN 0 430 #define MD_TXD_WIDTH 16 431 432 /* PHY management receive data register */ 433 #define MD_RXD_REG_KER 0xc10 434 #define MD_RXD_LBN 0 435 #define MD_RXD_WIDTH 16 436 437 /* PHY management configuration & status register */ 438 #define MD_CS_REG_KER 0xc20 439 #define MD_GC_LBN 4 440 #define MD_GC_WIDTH 1 441 #define MD_RIC_LBN 2 442 #define MD_RIC_WIDTH 1 443 #define MD_RDC_LBN 1 444 #define MD_RDC_WIDTH 1 445 #define MD_WRC_LBN 0 446 #define MD_WRC_WIDTH 1 447 448 /* PHY management PHY address register */ 449 #define MD_PHY_ADR_REG_KER 0xc30 450 #define MD_PHY_ADR_LBN 0 451 #define MD_PHY_ADR_WIDTH 16 452 453 /* PHY management ID register */ 454 #define MD_ID_REG_KER 0xc40 455 #define MD_PRT_ADR_LBN 11 456 #define MD_PRT_ADR_WIDTH 5 457 #define MD_DEV_ADR_LBN 6 458 #define MD_DEV_ADR_WIDTH 5 459 /* Used for writing both at once */ 460 #define MD_PRT_DEV_ADR_LBN 6 461 #define MD_PRT_DEV_ADR_WIDTH 10 462 463 /* PHY management status & mask register (DWORD read only) */ 464 #define MD_STAT_REG_KER 0xc50 465 #define MD_BSERR_LBN 2 466 #define MD_BSERR_WIDTH 1 467 #define MD_LNFL_LBN 1 468 #define MD_LNFL_WIDTH 1 469 #define MD_BSY_LBN 0 470 #define MD_BSY_WIDTH 1 471 472 /* Port 0 and 1 MAC stats registers */ 473 #define MAC0_STAT_DMA_REG_KER 0xc60 474 #define MAC_STAT_DMA_CMD_LBN 48 475 #define MAC_STAT_DMA_CMD_WIDTH 1 476 #define MAC_STAT_DMA_ADR_LBN 0 477 #define MAC_STAT_DMA_ADR_WIDTH EFX_DMA_TYPE_WIDTH(46) 478 479 /* Port 0 and 1 MAC control registers */ 480 #define MAC0_CTRL_REG_KER 0xc80 481 #define MAC_XOFF_VAL_LBN 16 482 #define MAC_XOFF_VAL_WIDTH 16 483 #define TXFIFO_DRAIN_EN_B0_LBN 7 484 #define TXFIFO_DRAIN_EN_B0_WIDTH 1 485 #define MAC_BCAD_ACPT_LBN 4 486 #define MAC_BCAD_ACPT_WIDTH 1 487 #define MAC_UC_PROM_LBN 3 488 #define MAC_UC_PROM_WIDTH 1 489 #define MAC_LINK_STATUS_LBN 2 490 #define MAC_LINK_STATUS_WIDTH 1 491 #define MAC_SPEED_LBN 0 492 #define MAC_SPEED_WIDTH 2 493 494 /* 10G XAUI XGXS default values */ 495 #define XX_TXDRV_DEQ_DEFAULT 0xe /* deq=.6 */ 496 #define XX_TXDRV_DTX_DEFAULT 0x5 /* 1.25 */ 497 #define XX_SD_CTL_DRV_DEFAULT 0 /* 20mA */ 498 499 /* Multicast address hash table */ 500 #define MAC_MCAST_HASH_REG0_KER 0xca0 501 #define MAC_MCAST_HASH_REG1_KER 0xcb0 502 503 /* GMAC configuration register 1 */ 504 #define GM_CFG1_REG 0xe00 505 #define GM_SW_RST_LBN 31 506 #define GM_SW_RST_WIDTH 1 507 #define GM_LOOP_LBN 8 508 #define GM_LOOP_WIDTH 1 509 #define GM_RX_FC_EN_LBN 5 510 #define GM_RX_FC_EN_WIDTH 1 511 #define GM_TX_FC_EN_LBN 4 512 #define GM_TX_FC_EN_WIDTH 1 513 #define GM_RX_EN_LBN 2 514 #define GM_RX_EN_WIDTH 1 515 #define GM_TX_EN_LBN 0 516 #define GM_TX_EN_WIDTH 1 517 518 /* GMAC configuration register 2 */ 519 #define GM_CFG2_REG 0xe10 520 #define GM_PAMBL_LEN_LBN 12 521 #define GM_PAMBL_LEN_WIDTH 4 522 #define GM_IF_MODE_LBN 8 523 #define GM_IF_MODE_WIDTH 2 524 #define GM_LEN_CHK_LBN 4 525 #define GM_LEN_CHK_WIDTH 1 526 #define GM_PAD_CRC_EN_LBN 2 527 #define GM_PAD_CRC_EN_WIDTH 1 528 #define GM_FD_LBN 0 529 #define GM_FD_WIDTH 1 530 531 /* GMAC maximum frame length register */ 532 #define GM_MAX_FLEN_REG 0xe40 533 #define GM_MAX_FLEN_LBN 0 534 #define GM_MAX_FLEN_WIDTH 16 535 536 /* GMAC station address register 1 */ 537 #define GM_ADR1_REG 0xf00 538 #define GM_HWADDR_5_LBN 24 539 #define GM_HWADDR_5_WIDTH 8 540 #define GM_HWADDR_4_LBN 16 541 #define GM_HWADDR_4_WIDTH 8 542 #define GM_HWADDR_3_LBN 8 543 #define GM_HWADDR_3_WIDTH 8 544 #define GM_HWADDR_2_LBN 0 545 #define GM_HWADDR_2_WIDTH 8 546 547 /* GMAC station address register 2 */ 548 #define GM_ADR2_REG 0xf10 549 #define GM_HWADDR_1_LBN 24 550 #define GM_HWADDR_1_WIDTH 8 551 #define GM_HWADDR_0_LBN 16 552 #define GM_HWADDR_0_WIDTH 8 553 554 /* GMAC FIFO configuration register 0 */ 555 #define GMF_CFG0_REG 0xf20 556 #define GMF_FTFENREQ_LBN 12 557 #define GMF_FTFENREQ_WIDTH 1 558 #define GMF_STFENREQ_LBN 11 559 #define GMF_STFENREQ_WIDTH 1 560 #define GMF_FRFENREQ_LBN 10 561 #define GMF_FRFENREQ_WIDTH 1 562 #define GMF_SRFENREQ_LBN 9 563 #define GMF_SRFENREQ_WIDTH 1 564 #define GMF_WTMENREQ_LBN 8 565 #define GMF_WTMENREQ_WIDTH 1 566 567 /* GMAC FIFO configuration register 1 */ 568 #define GMF_CFG1_REG 0xf30 569 #define GMF_CFGFRTH_LBN 16 570 #define GMF_CFGFRTH_WIDTH 5 571 #define GMF_CFGXOFFRTX_LBN 0 572 #define GMF_CFGXOFFRTX_WIDTH 16 573 574 /* GMAC FIFO configuration register 2 */ 575 #define GMF_CFG2_REG 0xf40 576 #define GMF_CFGHWM_LBN 16 577 #define GMF_CFGHWM_WIDTH 6 578 #define GMF_CFGLWM_LBN 0 579 #define GMF_CFGLWM_WIDTH 6 580 581 /* GMAC FIFO configuration register 3 */ 582 #define GMF_CFG3_REG 0xf50 583 #define GMF_CFGHWMFT_LBN 16 584 #define GMF_CFGHWMFT_WIDTH 6 585 #define GMF_CFGFTTH_LBN 0 586 #define GMF_CFGFTTH_WIDTH 6 587 588 /* GMAC FIFO configuration register 4 */ 589 #define GMF_CFG4_REG 0xf60 590 #define GMF_HSTFLTRFRM_PAUSE_LBN 12 591 #define GMF_HSTFLTRFRM_PAUSE_WIDTH 12 592 593 /* GMAC FIFO configuration register 5 */ 594 #define GMF_CFG5_REG 0xf70 595 #define GMF_CFGHDPLX_LBN 22 596 #define GMF_CFGHDPLX_WIDTH 1 597 #define GMF_CFGBYTMODE_LBN 19 598 #define GMF_CFGBYTMODE_WIDTH 1 599 #define GMF_HSTDRPLT64_LBN 18 600 #define GMF_HSTDRPLT64_WIDTH 1 601 #define GMF_HSTFLTRFRMDC_PAUSE_LBN 12 602 #define GMF_HSTFLTRFRMDC_PAUSE_WIDTH 1 603 604 /* XGMAC address register low */ 605 #define XM_ADR_LO_REG 0x1200 606 #define XM_ADR_3_LBN 24 607 #define XM_ADR_3_WIDTH 8 608 #define XM_ADR_2_LBN 16 609 #define XM_ADR_2_WIDTH 8 610 #define XM_ADR_1_LBN 8 611 #define XM_ADR_1_WIDTH 8 612 #define XM_ADR_0_LBN 0 613 #define XM_ADR_0_WIDTH 8 614 615 /* XGMAC address register high */ 616 #define XM_ADR_HI_REG 0x1210 617 #define XM_ADR_5_LBN 8 618 #define XM_ADR_5_WIDTH 8 619 #define XM_ADR_4_LBN 0 620 #define XM_ADR_4_WIDTH 8 621 622 /* XGMAC global configuration */ 623 #define XM_GLB_CFG_REG 0x1220 624 #define XM_RX_STAT_EN_LBN 11 625 #define XM_RX_STAT_EN_WIDTH 1 626 #define XM_TX_STAT_EN_LBN 10 627 #define XM_TX_STAT_EN_WIDTH 1 628 #define XM_RX_JUMBO_MODE_LBN 6 629 #define XM_RX_JUMBO_MODE_WIDTH 1 630 #define XM_INTCLR_MODE_LBN 3 631 #define XM_INTCLR_MODE_WIDTH 1 632 #define XM_CORE_RST_LBN 0 633 #define XM_CORE_RST_WIDTH 1 634 635 /* XGMAC transmit configuration */ 636 #define XM_TX_CFG_REG 0x1230 637 #define XM_IPG_LBN 16 638 #define XM_IPG_WIDTH 4 639 #define XM_FCNTL_LBN 10 640 #define XM_FCNTL_WIDTH 1 641 #define XM_TXCRC_LBN 8 642 #define XM_TXCRC_WIDTH 1 643 #define XM_AUTO_PAD_LBN 5 644 #define XM_AUTO_PAD_WIDTH 1 645 #define XM_TX_PRMBL_LBN 2 646 #define XM_TX_PRMBL_WIDTH 1 647 #define XM_TXEN_LBN 1 648 #define XM_TXEN_WIDTH 1 649 650 /* XGMAC receive configuration */ 651 #define XM_RX_CFG_REG 0x1240 652 #define XM_PASS_CRC_ERR_LBN 25 653 #define XM_PASS_CRC_ERR_WIDTH 1 654 #define XM_ACPT_ALL_MCAST_LBN 11 655 #define XM_ACPT_ALL_MCAST_WIDTH 1 656 #define XM_ACPT_ALL_UCAST_LBN 9 657 #define XM_ACPT_ALL_UCAST_WIDTH 1 658 #define XM_AUTO_DEPAD_LBN 8 659 #define XM_AUTO_DEPAD_WIDTH 1 660 #define XM_RXEN_LBN 1 661 #define XM_RXEN_WIDTH 1 662 663 /* XGMAC management interrupt mask register */ 664 #define XM_MGT_INT_MSK_REG_B0 0x1250 665 #define XM_MSK_PRMBLE_ERR_LBN 2 666 #define XM_MSK_PRMBLE_ERR_WIDTH 1 667 #define XM_MSK_RMTFLT_LBN 1 668 #define XM_MSK_RMTFLT_WIDTH 1 669 #define XM_MSK_LCLFLT_LBN 0 670 #define XM_MSK_LCLFLT_WIDTH 1 671 672 /* XGMAC flow control register */ 673 #define XM_FC_REG 0x1270 674 #define XM_PAUSE_TIME_LBN 16 675 #define XM_PAUSE_TIME_WIDTH 16 676 #define XM_DIS_FCNTL_LBN 0 677 #define XM_DIS_FCNTL_WIDTH 1 678 679 /* XGMAC pause time count register */ 680 #define XM_PAUSE_TIME_REG 0x1290 681 682 /* XGMAC transmit parameter register */ 683 #define XM_TX_PARAM_REG 0x012d0 684 #define XM_TX_JUMBO_MODE_LBN 31 685 #define XM_TX_JUMBO_MODE_WIDTH 1 686 #define XM_MAX_TX_FRM_SIZE_LBN 16 687 #define XM_MAX_TX_FRM_SIZE_WIDTH 14 688 689 /* XGMAC receive parameter register */ 690 #define XM_RX_PARAM_REG 0x12e0 691 #define XM_MAX_RX_FRM_SIZE_LBN 0 692 #define XM_MAX_RX_FRM_SIZE_WIDTH 14 693 694 /* XGMAC management interrupt status register */ 695 #define XM_MGT_INT_REG_B0 0x12f0 696 #define XM_PRMBLE_ERR 2 697 #define XM_PRMBLE_WIDTH 1 698 #define XM_RMTFLT_LBN 1 699 #define XM_RMTFLT_WIDTH 1 700 #define XM_LCLFLT_LBN 0 701 #define XM_LCLFLT_WIDTH 1 702 703 /* XGXS/XAUI powerdown/reset register */ 704 #define XX_PWR_RST_REG 0x1300 705 706 #define XX_PWRDND_EN_LBN 15 707 #define XX_PWRDND_EN_WIDTH 1 708 #define XX_PWRDNC_EN_LBN 14 709 #define XX_PWRDNC_EN_WIDTH 1 710 #define XX_PWRDNB_EN_LBN 13 711 #define XX_PWRDNB_EN_WIDTH 1 712 #define XX_PWRDNA_EN_LBN 12 713 #define XX_PWRDNA_EN_WIDTH 1 714 #define XX_RSTPLLCD_EN_LBN 9 715 #define XX_RSTPLLCD_EN_WIDTH 1 716 #define XX_RSTPLLAB_EN_LBN 8 717 #define XX_RSTPLLAB_EN_WIDTH 1 718 #define XX_RESETD_EN_LBN 7 719 #define XX_RESETD_EN_WIDTH 1 720 #define XX_RESETC_EN_LBN 6 721 #define XX_RESETC_EN_WIDTH 1 722 #define XX_RESETB_EN_LBN 5 723 #define XX_RESETB_EN_WIDTH 1 724 #define XX_RESETA_EN_LBN 4 725 #define XX_RESETA_EN_WIDTH 1 726 #define XX_RSTXGXSRX_EN_LBN 2 727 #define XX_RSTXGXSRX_EN_WIDTH 1 728 #define XX_RSTXGXSTX_EN_LBN 1 729 #define XX_RSTXGXSTX_EN_WIDTH 1 730 #define XX_RST_XX_EN_LBN 0 731 #define XX_RST_XX_EN_WIDTH 1 732 733 /* XGXS/XAUI powerdown/reset control register */ 734 #define XX_SD_CTL_REG 0x1310 735 #define XX_HIDRVD_LBN 15 736 #define XX_HIDRVD_WIDTH 1 737 #define XX_LODRVD_LBN 14 738 #define XX_LODRVD_WIDTH 1 739 #define XX_HIDRVC_LBN 13 740 #define XX_HIDRVC_WIDTH 1 741 #define XX_LODRVC_LBN 12 742 #define XX_LODRVC_WIDTH 1 743 #define XX_HIDRVB_LBN 11 744 #define XX_HIDRVB_WIDTH 1 745 #define XX_LODRVB_LBN 10 746 #define XX_LODRVB_WIDTH 1 747 #define XX_HIDRVA_LBN 9 748 #define XX_HIDRVA_WIDTH 1 749 #define XX_LODRVA_LBN 8 750 #define XX_LODRVA_WIDTH 1 751 #define XX_LPBKD_LBN 3 752 #define XX_LPBKD_WIDTH 1 753 #define XX_LPBKC_LBN 2 754 #define XX_LPBKC_WIDTH 1 755 #define XX_LPBKB_LBN 1 756 #define XX_LPBKB_WIDTH 1 757 #define XX_LPBKA_LBN 0 758 #define XX_LPBKA_WIDTH 1 759 760 #define XX_TXDRV_CTL_REG 0x1320 761 #define XX_DEQD_LBN 28 762 #define XX_DEQD_WIDTH 4 763 #define XX_DEQC_LBN 24 764 #define XX_DEQC_WIDTH 4 765 #define XX_DEQB_LBN 20 766 #define XX_DEQB_WIDTH 4 767 #define XX_DEQA_LBN 16 768 #define XX_DEQA_WIDTH 4 769 #define XX_DTXD_LBN 12 770 #define XX_DTXD_WIDTH 4 771 #define XX_DTXC_LBN 8 772 #define XX_DTXC_WIDTH 4 773 #define XX_DTXB_LBN 4 774 #define XX_DTXB_WIDTH 4 775 #define XX_DTXA_LBN 0 776 #define XX_DTXA_WIDTH 4 777 778 /* XAUI XGXS core status register */ 779 #define XX_CORE_STAT_REG 0x1360 780 #define XX_FORCE_SIG_LBN 24 781 #define XX_FORCE_SIG_WIDTH 8 782 #define XX_FORCE_SIG_DECODE_FORCED 0xff 783 #define XX_XGXS_LB_EN_LBN 23 784 #define XX_XGXS_LB_EN_WIDTH 1 785 #define XX_XGMII_LB_EN_LBN 22 786 #define XX_XGMII_LB_EN_WIDTH 1 787 #define XX_ALIGN_DONE_LBN 20 788 #define XX_ALIGN_DONE_WIDTH 1 789 #define XX_SYNC_STAT_LBN 16 790 #define XX_SYNC_STAT_WIDTH 4 791 #define XX_SYNC_STAT_DECODE_SYNCED 0xf 792 #define XX_COMMA_DET_LBN 12 793 #define XX_COMMA_DET_WIDTH 4 794 #define XX_COMMA_DET_DECODE_DETECTED 0xf 795 #define XX_COMMA_DET_RESET 0xf 796 #define XX_CHARERR_LBN 4 797 #define XX_CHARERR_WIDTH 4 798 #define XX_CHARERR_RESET 0xf 799 #define XX_DISPERR_LBN 0 800 #define XX_DISPERR_WIDTH 4 801 #define XX_DISPERR_RESET 0xf 802 803 /* Receive filter table */ 804 #define RX_FILTER_TBL0 0xF00000 805 806 /* Receive descriptor pointer table */ 807 #define RX_DESC_PTR_TBL_KER_A1 0x11800 808 #define RX_DESC_PTR_TBL_KER_B0 0xF40000 809 #define RX_DESC_PTR_TBL_KER_P0 0x900 810 #define RX_ISCSI_DDIG_EN_LBN 88 811 #define RX_ISCSI_DDIG_EN_WIDTH 1 812 #define RX_ISCSI_HDIG_EN_LBN 87 813 #define RX_ISCSI_HDIG_EN_WIDTH 1 814 #define RX_DESCQ_BUF_BASE_ID_LBN 36 815 #define RX_DESCQ_BUF_BASE_ID_WIDTH 20 816 #define RX_DESCQ_EVQ_ID_LBN 24 817 #define RX_DESCQ_EVQ_ID_WIDTH 12 818 #define RX_DESCQ_OWNER_ID_LBN 10 819 #define RX_DESCQ_OWNER_ID_WIDTH 14 820 #define RX_DESCQ_LABEL_LBN 5 821 #define RX_DESCQ_LABEL_WIDTH 5 822 #define RX_DESCQ_SIZE_LBN 3 823 #define RX_DESCQ_SIZE_WIDTH 2 824 #define RX_DESCQ_SIZE_4K 3 825 #define RX_DESCQ_SIZE_2K 2 826 #define RX_DESCQ_SIZE_1K 1 827 #define RX_DESCQ_SIZE_512 0 828 #define RX_DESCQ_TYPE_LBN 2 829 #define RX_DESCQ_TYPE_WIDTH 1 830 #define RX_DESCQ_JUMBO_LBN 1 831 #define RX_DESCQ_JUMBO_WIDTH 1 832 #define RX_DESCQ_EN_LBN 0 833 #define RX_DESCQ_EN_WIDTH 1 834 835 /* Transmit descriptor pointer table */ 836 #define TX_DESC_PTR_TBL_KER_A1 0x11900 837 #define TX_DESC_PTR_TBL_KER_B0 0xF50000 838 #define TX_DESC_PTR_TBL_KER_P0 0xa40 839 #define TX_NON_IP_DROP_DIS_B0_LBN 91 840 #define TX_NON_IP_DROP_DIS_B0_WIDTH 1 841 #define TX_IP_CHKSM_DIS_B0_LBN 90 842 #define TX_IP_CHKSM_DIS_B0_WIDTH 1 843 #define TX_TCP_CHKSM_DIS_B0_LBN 89 844 #define TX_TCP_CHKSM_DIS_B0_WIDTH 1 845 #define TX_DESCQ_EN_LBN 88 846 #define TX_DESCQ_EN_WIDTH 1 847 #define TX_ISCSI_DDIG_EN_LBN 87 848 #define TX_ISCSI_DDIG_EN_WIDTH 1 849 #define TX_ISCSI_HDIG_EN_LBN 86 850 #define TX_ISCSI_HDIG_EN_WIDTH 1 851 #define TX_DESCQ_BUF_BASE_ID_LBN 36 852 #define TX_DESCQ_BUF_BASE_ID_WIDTH 20 853 #define TX_DESCQ_EVQ_ID_LBN 24 854 #define TX_DESCQ_EVQ_ID_WIDTH 12 855 #define TX_DESCQ_OWNER_ID_LBN 10 856 #define TX_DESCQ_OWNER_ID_WIDTH 14 857 #define TX_DESCQ_LABEL_LBN 5 858 #define TX_DESCQ_LABEL_WIDTH 5 859 #define TX_DESCQ_SIZE_LBN 3 860 #define TX_DESCQ_SIZE_WIDTH 2 861 #define TX_DESCQ_SIZE_4K 3 862 #define TX_DESCQ_SIZE_2K 2 863 #define TX_DESCQ_SIZE_1K 1 864 #define TX_DESCQ_SIZE_512 0 865 #define TX_DESCQ_TYPE_LBN 1 866 #define TX_DESCQ_TYPE_WIDTH 2 867 868 /* Event queue pointer */ 869 #define EVQ_PTR_TBL_KER_A1 0x11a00 870 #define EVQ_PTR_TBL_KER_B0 0xf60000 871 #define EVQ_PTR_TBL_KER_P0 0x500 872 #define EVQ_EN_LBN 23 873 #define EVQ_EN_WIDTH 1 874 #define EVQ_SIZE_LBN 20 875 #define EVQ_SIZE_WIDTH 3 876 #define EVQ_SIZE_32K 6 877 #define EVQ_SIZE_16K 5 878 #define EVQ_SIZE_8K 4 879 #define EVQ_SIZE_4K 3 880 #define EVQ_SIZE_2K 2 881 #define EVQ_SIZE_1K 1 882 #define EVQ_SIZE_512 0 883 #define EVQ_BUF_BASE_ID_LBN 0 884 #define EVQ_BUF_BASE_ID_WIDTH 20 885 886 /* Event queue read pointer */ 887 #define EVQ_RPTR_REG_KER_A1 0x11b00 888 #define EVQ_RPTR_REG_KER_B0 0xfa0000 889 #define EVQ_RPTR_REG_KER_DWORD (EVQ_RPTR_REG_KER + 0) 890 #define EVQ_RPTR_DWORD_LBN 0 891 #define EVQ_RPTR_DWORD_WIDTH 14 892 893 /* RSS indirection table */ 894 #define RX_RSS_INDIR_TBL_B0 0xFB0000 895 #define RX_RSS_INDIR_ENT_B0_LBN 0 896 #define RX_RSS_INDIR_ENT_B0_WIDTH 6 897 898 /* Special buffer descriptors (full-mode) */ 899 #define BUF_FULL_TBL_KER_A1 0x8000 900 #define BUF_FULL_TBL_KER_B0 0x800000 901 #define IP_DAT_BUF_SIZE_LBN 50 902 #define IP_DAT_BUF_SIZE_WIDTH 1 903 #define IP_DAT_BUF_SIZE_8K 1 904 #define IP_DAT_BUF_SIZE_4K 0 905 #define BUF_ADR_REGION_LBN 48 906 #define BUF_ADR_REGION_WIDTH 2 907 #define BUF_ADR_FBUF_LBN 14 908 #define BUF_ADR_FBUF_WIDTH 34 909 #define BUF_OWNER_ID_FBUF_LBN 0 910 #define BUF_OWNER_ID_FBUF_WIDTH 14 911 912 /* Transmit descriptor */ 913 #define TX_KER_PORT_LBN 63 914 #define TX_KER_PORT_WIDTH 1 915 #define TX_KER_CONT_LBN 62 916 #define TX_KER_CONT_WIDTH 1 917 #define TX_KER_BYTE_CNT_LBN 48 918 #define TX_KER_BYTE_CNT_WIDTH 14 919 #define TX_KER_BUF_REGION_LBN 46 920 #define TX_KER_BUF_REGION_WIDTH 2 921 #define TX_KER_BUF_REGION0_DECODE 0 922 #define TX_KER_BUF_REGION1_DECODE 1 923 #define TX_KER_BUF_REGION2_DECODE 2 924 #define TX_KER_BUF_REGION3_DECODE 3 925 #define TX_KER_BUF_ADR_LBN 0 926 #define TX_KER_BUF_ADR_WIDTH EFX_DMA_TYPE_WIDTH(46) 927 928 /* Receive descriptor */ 929 #define RX_KER_BUF_SIZE_LBN 48 930 #define RX_KER_BUF_SIZE_WIDTH 14 931 #define RX_KER_BUF_REGION_LBN 46 932 #define RX_KER_BUF_REGION_WIDTH 2 933 #define RX_KER_BUF_REGION0_DECODE 0 934 #define RX_KER_BUF_REGION1_DECODE 1 935 #define RX_KER_BUF_REGION2_DECODE 2 936 #define RX_KER_BUF_REGION3_DECODE 3 937 #define RX_KER_BUF_ADR_LBN 0 938 #define RX_KER_BUF_ADR_WIDTH EFX_DMA_TYPE_WIDTH(46) 939 940 /************************************************************************** 941 * 942 * Falcon events 943 * 944 ************************************************************************** 945 */ 946 947 /* Event queue entries */ 948 #define EV_CODE_LBN 60 949 #define EV_CODE_WIDTH 4 950 #define RX_IP_EV_DECODE 0 951 #define TX_IP_EV_DECODE 2 952 #define DRIVER_EV_DECODE 5 953 #define GLOBAL_EV_DECODE 6 954 #define DRV_GEN_EV_DECODE 7 955 #define WHOLE_EVENT_LBN 0 956 #define WHOLE_EVENT_WIDTH 64 957 958 /* Receive events */ 959 #define RX_EV_PKT_OK_LBN 56 960 #define RX_EV_PKT_OK_WIDTH 1 961 #define RX_EV_PAUSE_FRM_ERR_LBN 55 962 #define RX_EV_PAUSE_FRM_ERR_WIDTH 1 963 #define RX_EV_BUF_OWNER_ID_ERR_LBN 54 964 #define RX_EV_BUF_OWNER_ID_ERR_WIDTH 1 965 #define RX_EV_IF_FRAG_ERR_LBN 53 966 #define RX_EV_IF_FRAG_ERR_WIDTH 1 967 #define RX_EV_IP_HDR_CHKSUM_ERR_LBN 52 968 #define RX_EV_IP_HDR_CHKSUM_ERR_WIDTH 1 969 #define RX_EV_TCP_UDP_CHKSUM_ERR_LBN 51 970 #define RX_EV_TCP_UDP_CHKSUM_ERR_WIDTH 1 971 #define RX_EV_ETH_CRC_ERR_LBN 50 972 #define RX_EV_ETH_CRC_ERR_WIDTH 1 973 #define RX_EV_FRM_TRUNC_LBN 49 974 #define RX_EV_FRM_TRUNC_WIDTH 1 975 #define RX_EV_DRIB_NIB_LBN 48 976 #define RX_EV_DRIB_NIB_WIDTH 1 977 #define RX_EV_TOBE_DISC_LBN 47 978 #define RX_EV_TOBE_DISC_WIDTH 1 979 #define RX_EV_PKT_TYPE_LBN 44 980 #define RX_EV_PKT_TYPE_WIDTH 3 981 #define RX_EV_PKT_TYPE_ETH_DECODE 0 982 #define RX_EV_PKT_TYPE_LLC_DECODE 1 983 #define RX_EV_PKT_TYPE_JUMBO_DECODE 2 984 #define RX_EV_PKT_TYPE_VLAN_DECODE 3 985 #define RX_EV_PKT_TYPE_VLAN_LLC_DECODE 4 986 #define RX_EV_PKT_TYPE_VLAN_JUMBO_DECODE 5 987 #define RX_EV_HDR_TYPE_LBN 42 988 #define RX_EV_HDR_TYPE_WIDTH 2 989 #define RX_EV_HDR_TYPE_TCP_IPV4_DECODE 0 990 #define RX_EV_HDR_TYPE_UDP_IPV4_DECODE 1 991 #define RX_EV_HDR_TYPE_OTHER_IP_DECODE 2 992 #define RX_EV_HDR_TYPE_NON_IP_DECODE 3 993 #define RX_EV_HDR_TYPE_HAS_CHECKSUMS(hdr_type) \ 994 ((hdr_type) <= RX_EV_HDR_TYPE_UDP_IPV4_DECODE) 995 #define RX_EV_MCAST_HASH_MATCH_LBN 40 996 #define RX_EV_MCAST_HASH_MATCH_WIDTH 1 997 #define RX_EV_MCAST_PKT_LBN 39 998 #define RX_EV_MCAST_PKT_WIDTH 1 999 #define RX_EV_Q_LABEL_LBN 32 1000 #define RX_EV_Q_LABEL_WIDTH 5 1001 #define RX_EV_JUMBO_CONT_LBN 31 1002 #define RX_EV_JUMBO_CONT_WIDTH 1 1003 #define RX_EV_BYTE_CNT_LBN 16 1004 #define RX_EV_BYTE_CNT_WIDTH 14 1005 #define RX_EV_SOP_LBN 15 1006 #define RX_EV_SOP_WIDTH 1 1007 #define RX_EV_DESC_PTR_LBN 0 1008 #define RX_EV_DESC_PTR_WIDTH 12 1009 1010 /* Transmit events */ 1011 #define TX_EV_PKT_ERR_LBN 38 1012 #define TX_EV_PKT_ERR_WIDTH 1 1013 #define TX_EV_Q_LABEL_LBN 32 1014 #define TX_EV_Q_LABEL_WIDTH 5 1015 #define TX_EV_WQ_FF_FULL_LBN 15 1016 #define TX_EV_WQ_FF_FULL_WIDTH 1 1017 #define TX_EV_COMP_LBN 12 1018 #define TX_EV_COMP_WIDTH 1 1019 #define TX_EV_DESC_PTR_LBN 0 1020 #define TX_EV_DESC_PTR_WIDTH 12 1021 1022 /* Driver events */ 1023 #define DRIVER_EV_SUB_CODE_LBN 56 1024 #define DRIVER_EV_SUB_CODE_WIDTH 4 1025 #define DRIVER_EV_SUB_DATA_LBN 0 1026 #define DRIVER_EV_SUB_DATA_WIDTH 14 1027 #define TX_DESCQ_FLS_DONE_EV_DECODE 0 1028 #define RX_DESCQ_FLS_DONE_EV_DECODE 1 1029 #define EVQ_INIT_DONE_EV_DECODE 2 1030 #define EVQ_NOT_EN_EV_DECODE 3 1031 #define RX_DESCQ_FLSFF_OVFL_EV_DECODE 4 1032 #define SRM_UPD_DONE_EV_DECODE 5 1033 #define WAKE_UP_EV_DECODE 6 1034 #define TX_PKT_NON_TCP_UDP_DECODE 9 1035 #define TIMER_EV_DECODE 10 1036 #define RX_RECOVERY_EV_DECODE 11 1037 #define RX_DSC_ERROR_EV_DECODE 14 1038 #define TX_DSC_ERROR_EV_DECODE 15 1039 #define DRIVER_EV_TX_DESCQ_ID_LBN 0 1040 #define DRIVER_EV_TX_DESCQ_ID_WIDTH 12 1041 #define DRIVER_EV_RX_FLUSH_FAIL_LBN 12 1042 #define DRIVER_EV_RX_FLUSH_FAIL_WIDTH 1 1043 #define DRIVER_EV_RX_DESCQ_ID_LBN 0 1044 #define DRIVER_EV_RX_DESCQ_ID_WIDTH 12 1045 #define SRM_CLR_EV_DECODE 0 1046 #define SRM_UPD_EV_DECODE 1 1047 #define SRM_ILLCLR_EV_DECODE 2 1048 1049 /* Global events */ 1050 #define RX_RECOVERY_B0_LBN 12 1051 #define RX_RECOVERY_B0_WIDTH 1 1052 #define XG_MNT_INTR_B0_LBN 11 1053 #define XG_MNT_INTR_B0_WIDTH 1 1054 #define RX_RECOVERY_A1_LBN 11 1055 #define RX_RECOVERY_A1_WIDTH 1 1056 #define XFP_PHY_INTR_LBN 10 1057 #define XFP_PHY_INTR_WIDTH 1 1058 #define XG_PHY_INTR_LBN 9 1059 #define XG_PHY_INTR_WIDTH 1 1060 #define G_PHY1_INTR_LBN 8 1061 #define G_PHY1_INTR_WIDTH 1 1062 #define G_PHY0_INTR_LBN 7 1063 #define G_PHY0_INTR_WIDTH 1 1064 1065 /* Driver-generated test events */ 1066 #define EVQ_MAGIC_LBN 0 1067 #define EVQ_MAGIC_WIDTH 32 1068 1069 /************************************************************************** 1070 * 1071 * Falcon MAC stats 1072 * 1073 ************************************************************************** 1074 * 1075 */ 1076 1077 #define GRxGoodOct_offset 0x0 1078 #define GRxGoodOct_WIDTH 48 1079 #define GRxBadOct_offset 0x8 1080 #define GRxBadOct_WIDTH 48 1081 #define GRxMissPkt_offset 0x10 1082 #define GRxMissPkt_WIDTH 32 1083 #define GRxFalseCRS_offset 0x14 1084 #define GRxFalseCRS_WIDTH 32 1085 #define GRxPausePkt_offset 0x18 1086 #define GRxPausePkt_WIDTH 32 1087 #define GRxBadPkt_offset 0x1C 1088 #define GRxBadPkt_WIDTH 32 1089 #define GRxUcastPkt_offset 0x20 1090 #define GRxUcastPkt_WIDTH 32 1091 #define GRxMcastPkt_offset 0x24 1092 #define GRxMcastPkt_WIDTH 32 1093 #define GRxBcastPkt_offset 0x28 1094 #define GRxBcastPkt_WIDTH 32 1095 #define GRxGoodLt64Pkt_offset 0x2C 1096 #define GRxGoodLt64Pkt_WIDTH 32 1097 #define GRxBadLt64Pkt_offset 0x30 1098 #define GRxBadLt64Pkt_WIDTH 32 1099 #define GRx64Pkt_offset 0x34 1100 #define GRx64Pkt_WIDTH 32 1101 #define GRx65to127Pkt_offset 0x38 1102 #define GRx65to127Pkt_WIDTH 32 1103 #define GRx128to255Pkt_offset 0x3C 1104 #define GRx128to255Pkt_WIDTH 32 1105 #define GRx256to511Pkt_offset 0x40 1106 #define GRx256to511Pkt_WIDTH 32 1107 #define GRx512to1023Pkt_offset 0x44 1108 #define GRx512to1023Pkt_WIDTH 32 1109 #define GRx1024to15xxPkt_offset 0x48 1110 #define GRx1024to15xxPkt_WIDTH 32 1111 #define GRx15xxtoJumboPkt_offset 0x4C 1112 #define GRx15xxtoJumboPkt_WIDTH 32 1113 #define GRxGtJumboPkt_offset 0x50 1114 #define GRxGtJumboPkt_WIDTH 32 1115 #define GRxFcsErr64to15xxPkt_offset 0x54 1116 #define GRxFcsErr64to15xxPkt_WIDTH 32 1117 #define GRxFcsErr15xxtoJumboPkt_offset 0x58 1118 #define GRxFcsErr15xxtoJumboPkt_WIDTH 32 1119 #define GRxFcsErrGtJumboPkt_offset 0x5C 1120 #define GRxFcsErrGtJumboPkt_WIDTH 32 1121 #define GTxGoodBadOct_offset 0x80 1122 #define GTxGoodBadOct_WIDTH 48 1123 #define GTxGoodOct_offset 0x88 1124 #define GTxGoodOct_WIDTH 48 1125 #define GTxSglColPkt_offset 0x90 1126 #define GTxSglColPkt_WIDTH 32 1127 #define GTxMultColPkt_offset 0x94 1128 #define GTxMultColPkt_WIDTH 32 1129 #define GTxExColPkt_offset 0x98 1130 #define GTxExColPkt_WIDTH 32 1131 #define GTxDefPkt_offset 0x9C 1132 #define GTxDefPkt_WIDTH 32 1133 #define GTxLateCol_offset 0xA0 1134 #define GTxLateCol_WIDTH 32 1135 #define GTxExDefPkt_offset 0xA4 1136 #define GTxExDefPkt_WIDTH 32 1137 #define GTxPausePkt_offset 0xA8 1138 #define GTxPausePkt_WIDTH 32 1139 #define GTxBadPkt_offset 0xAC 1140 #define GTxBadPkt_WIDTH 32 1141 #define GTxUcastPkt_offset 0xB0 1142 #define GTxUcastPkt_WIDTH 32 1143 #define GTxMcastPkt_offset 0xB4 1144 #define GTxMcastPkt_WIDTH 32 1145 #define GTxBcastPkt_offset 0xB8 1146 #define GTxBcastPkt_WIDTH 32 1147 #define GTxLt64Pkt_offset 0xBC 1148 #define GTxLt64Pkt_WIDTH 32 1149 #define GTx64Pkt_offset 0xC0 1150 #define GTx64Pkt_WIDTH 32 1151 #define GTx65to127Pkt_offset 0xC4 1152 #define GTx65to127Pkt_WIDTH 32 1153 #define GTx128to255Pkt_offset 0xC8 1154 #define GTx128to255Pkt_WIDTH 32 1155 #define GTx256to511Pkt_offset 0xCC 1156 #define GTx256to511Pkt_WIDTH 32 1157 #define GTx512to1023Pkt_offset 0xD0 1158 #define GTx512to1023Pkt_WIDTH 32 1159 #define GTx1024to15xxPkt_offset 0xD4 1160 #define GTx1024to15xxPkt_WIDTH 32 1161 #define GTx15xxtoJumboPkt_offset 0xD8 1162 #define GTx15xxtoJumboPkt_WIDTH 32 1163 #define GTxGtJumboPkt_offset 0xDC 1164 #define GTxGtJumboPkt_WIDTH 32 1165 #define GTxNonTcpUdpPkt_offset 0xE0 1166 #define GTxNonTcpUdpPkt_WIDTH 16 1167 #define GTxMacSrcErrPkt_offset 0xE4 1168 #define GTxMacSrcErrPkt_WIDTH 16 1169 #define GTxIpSrcErrPkt_offset 0xE8 1170 #define GTxIpSrcErrPkt_WIDTH 16 1171 #define GDmaDone_offset 0xEC 1172 #define GDmaDone_WIDTH 32 1173 1174 #define XgRxOctets_offset 0x0 1175 #define XgRxOctets_WIDTH 48 1176 #define XgRxOctetsOK_offset 0x8 1177 #define XgRxOctetsOK_WIDTH 48 1178 #define XgRxPkts_offset 0x10 1179 #define XgRxPkts_WIDTH 32 1180 #define XgRxPktsOK_offset 0x14 1181 #define XgRxPktsOK_WIDTH 32 1182 #define XgRxBroadcastPkts_offset 0x18 1183 #define XgRxBroadcastPkts_WIDTH 32 1184 #define XgRxMulticastPkts_offset 0x1C 1185 #define XgRxMulticastPkts_WIDTH 32 1186 #define XgRxUnicastPkts_offset 0x20 1187 #define XgRxUnicastPkts_WIDTH 32 1188 #define XgRxUndersizePkts_offset 0x24 1189 #define XgRxUndersizePkts_WIDTH 32 1190 #define XgRxOversizePkts_offset 0x28 1191 #define XgRxOversizePkts_WIDTH 32 1192 #define XgRxJabberPkts_offset 0x2C 1193 #define XgRxJabberPkts_WIDTH 32 1194 #define XgRxUndersizeFCSerrorPkts_offset 0x30 1195 #define XgRxUndersizeFCSerrorPkts_WIDTH 32 1196 #define XgRxDropEvents_offset 0x34 1197 #define XgRxDropEvents_WIDTH 32 1198 #define XgRxFCSerrorPkts_offset 0x38 1199 #define XgRxFCSerrorPkts_WIDTH 32 1200 #define XgRxAlignError_offset 0x3C 1201 #define XgRxAlignError_WIDTH 32 1202 #define XgRxSymbolError_offset 0x40 1203 #define XgRxSymbolError_WIDTH 32 1204 #define XgRxInternalMACError_offset 0x44 1205 #define XgRxInternalMACError_WIDTH 32 1206 #define XgRxControlPkts_offset 0x48 1207 #define XgRxControlPkts_WIDTH 32 1208 #define XgRxPausePkts_offset 0x4C 1209 #define XgRxPausePkts_WIDTH 32 1210 #define XgRxPkts64Octets_offset 0x50 1211 #define XgRxPkts64Octets_WIDTH 32 1212 #define XgRxPkts65to127Octets_offset 0x54 1213 #define XgRxPkts65to127Octets_WIDTH 32 1214 #define XgRxPkts128to255Octets_offset 0x58 1215 #define XgRxPkts128to255Octets_WIDTH 32 1216 #define XgRxPkts256to511Octets_offset 0x5C 1217 #define XgRxPkts256to511Octets_WIDTH 32 1218 #define XgRxPkts512to1023Octets_offset 0x60 1219 #define XgRxPkts512to1023Octets_WIDTH 32 1220 #define XgRxPkts1024to15xxOctets_offset 0x64 1221 #define XgRxPkts1024to15xxOctets_WIDTH 32 1222 #define XgRxPkts15xxtoMaxOctets_offset 0x68 1223 #define XgRxPkts15xxtoMaxOctets_WIDTH 32 1224 #define XgRxLengthError_offset 0x6C 1225 #define XgRxLengthError_WIDTH 32 1226 #define XgTxPkts_offset 0x80 1227 #define XgTxPkts_WIDTH 32 1228 #define XgTxOctets_offset 0x88 1229 #define XgTxOctets_WIDTH 48 1230 #define XgTxMulticastPkts_offset 0x90 1231 #define XgTxMulticastPkts_WIDTH 32 1232 #define XgTxBroadcastPkts_offset 0x94 1233 #define XgTxBroadcastPkts_WIDTH 32 1234 #define XgTxUnicastPkts_offset 0x98 1235 #define XgTxUnicastPkts_WIDTH 32 1236 #define XgTxControlPkts_offset 0x9C 1237 #define XgTxControlPkts_WIDTH 32 1238 #define XgTxPausePkts_offset 0xA0 1239 #define XgTxPausePkts_WIDTH 32 1240 #define XgTxPkts64Octets_offset 0xA4 1241 #define XgTxPkts64Octets_WIDTH 32 1242 #define XgTxPkts65to127Octets_offset 0xA8 1243 #define XgTxPkts65to127Octets_WIDTH 32 1244 #define XgTxPkts128to255Octets_offset 0xAC 1245 #define XgTxPkts128to255Octets_WIDTH 32 1246 #define XgTxPkts256to511Octets_offset 0xB0 1247 #define XgTxPkts256to511Octets_WIDTH 32 1248 #define XgTxPkts512to1023Octets_offset 0xB4 1249 #define XgTxPkts512to1023Octets_WIDTH 32 1250 #define XgTxPkts1024to15xxOctets_offset 0xB8 1251 #define XgTxPkts1024to15xxOctets_WIDTH 32 1252 #define XgTxPkts1519toMaxOctets_offset 0xBC 1253 #define XgTxPkts1519toMaxOctets_WIDTH 32 1254 #define XgTxUndersizePkts_offset 0xC0 1255 #define XgTxUndersizePkts_WIDTH 32 1256 #define XgTxOversizePkts_offset 0xC4 1257 #define XgTxOversizePkts_WIDTH 32 1258 #define XgTxNonTcpUdpPkt_offset 0xC8 1259 #define XgTxNonTcpUdpPkt_WIDTH 16 1260 #define XgTxMacSrcErrPkt_offset 0xCC 1261 #define XgTxMacSrcErrPkt_WIDTH 16 1262 #define XgTxIpSrcErrPkt_offset 0xD0 1263 #define XgTxIpSrcErrPkt_WIDTH 16 1264 #define XgDmaDone_offset 0xD4 1265 1266 #define FALCON_STATS_NOT_DONE 0x00000000 1267 #define FALCON_STATS_DONE 0xffffffff 1268 1269 /* Interrupt status register bits */ 1270 #define FATAL_INT_LBN 64 1271 #define FATAL_INT_WIDTH 1 1272 #define INT_EVQS_LBN 40 1273 #define INT_EVQS_WIDTH 4 1274 1275 /************************************************************************** 1276 * 1277 * Falcon non-volatile configuration 1278 * 1279 ************************************************************************** 1280 */ 1281 1282 /* Board configuration v2 (v1 is obsolete; later versions are compatible) */ 1283 struct falcon_nvconfig_board_v2 { 1284 __le16 nports; 1285 u8 port0_phy_addr; 1286 u8 port0_phy_type; 1287 u8 port1_phy_addr; 1288 u8 port1_phy_type; 1289 __le16 asic_sub_revision; 1290 __le16 board_revision; 1291 } __packed; 1292 1293 /* Board configuration v3 extra information */ 1294 struct falcon_nvconfig_board_v3 { 1295 __le32 spi_device_type[2]; 1296 } __packed; 1297 1298 /* Bit numbers for spi_device_type */ 1299 #define SPI_DEV_TYPE_SIZE_LBN 0 1300 #define SPI_DEV_TYPE_SIZE_WIDTH 5 1301 #define SPI_DEV_TYPE_ADDR_LEN_LBN 6 1302 #define SPI_DEV_TYPE_ADDR_LEN_WIDTH 2 1303 #define SPI_DEV_TYPE_ERASE_CMD_LBN 8 1304 #define SPI_DEV_TYPE_ERASE_CMD_WIDTH 8 1305 #define SPI_DEV_TYPE_ERASE_SIZE_LBN 16 1306 #define SPI_DEV_TYPE_ERASE_SIZE_WIDTH 5 1307 #define SPI_DEV_TYPE_BLOCK_SIZE_LBN 24 1308 #define SPI_DEV_TYPE_BLOCK_SIZE_WIDTH 5 1309 #define SPI_DEV_TYPE_FIELD(type, field) \ 1310 (((type) >> EFX_LOW_BIT(field)) & EFX_MASK32(EFX_WIDTH(field))) 1311 1312 #define NVCONFIG_OFFSET 0x300 1313 1314 #define NVCONFIG_BOARD_MAGIC_NUM 0xFA1C 1315 struct falcon_nvconfig { 1316 efx_oword_t ee_vpd_cfg_reg; /* 0x300 */ 1317 u8 mac_address[2][8]; /* 0x310 */ 1318 efx_oword_t pcie_sd_ctl0123_reg; /* 0x320 */ 1319 efx_oword_t pcie_sd_ctl45_reg; /* 0x330 */ 1320 efx_oword_t pcie_pcs_ctl_stat_reg; /* 0x340 */ 1321 efx_oword_t hw_init_reg; /* 0x350 */ 1322 efx_oword_t nic_stat_reg; /* 0x360 */ 1323 efx_oword_t glb_ctl_reg; /* 0x370 */ 1324 efx_oword_t srm_cfg_reg; /* 0x380 */ 1325 efx_oword_t spare_reg; /* 0x390 */ 1326 __le16 board_magic_num; /* 0x3A0 */ 1327 __le16 board_struct_ver; 1328 __le16 board_checksum; 1329 struct falcon_nvconfig_board_v2 board_v2; 1330 efx_oword_t ee_base_page_reg; /* 0x3B0 */ 1331 struct falcon_nvconfig_board_v3 board_v3; 1332 } __packed; 1333 1334 #endif /* EFX_FALCON_HWDEFS_H */ 1335