1 #include <linux/module.h>
2 #include <linux/kernel.h>
3 #include <linux/init.h>
4 #include <linux/platform_device.h>
5 #include <linux/dma-mapping.h>
6
7 #include <mach/pxa-regs.h>
8 #include <mach/udc.h>
9 #include <mach/pxafb.h>
10 #include <mach/mmc.h>
11 #include <mach/irda.h>
12 #include <mach/i2c.h>
13 #include <mach/ohci.h>
14 #include <mach/pxa27x_keypad.h>
15 #include <mach/pxa2xx_spi.h>
16 #include <mach/camera.h>
17 #include <mach/audio.h>
18 #include <mach/pxa3xx_nand.h>
19
20 #include "devices.h"
21 #include "generic.h"
22
pxa_register_device(struct platform_device * dev,void * data)23 void __init pxa_register_device(struct platform_device *dev, void *data)
24 {
25 int ret;
26
27 dev->dev.platform_data = data;
28
29 ret = platform_device_register(dev);
30 if (ret)
31 dev_err(&dev->dev, "unable to register device: %d\n", ret);
32 }
33
34 static struct resource pxamci_resources[] = {
35 [0] = {
36 .start = 0x41100000,
37 .end = 0x41100fff,
38 .flags = IORESOURCE_MEM,
39 },
40 [1] = {
41 .start = IRQ_MMC,
42 .end = IRQ_MMC,
43 .flags = IORESOURCE_IRQ,
44 },
45 [2] = {
46 .start = 21,
47 .end = 21,
48 .flags = IORESOURCE_DMA,
49 },
50 [3] = {
51 .start = 22,
52 .end = 22,
53 .flags = IORESOURCE_DMA,
54 },
55 };
56
57 static u64 pxamci_dmamask = 0xffffffffUL;
58
59 struct platform_device pxa_device_mci = {
60 .name = "pxa2xx-mci",
61 .id = 0,
62 .dev = {
63 .dma_mask = &pxamci_dmamask,
64 .coherent_dma_mask = 0xffffffff,
65 },
66 .num_resources = ARRAY_SIZE(pxamci_resources),
67 .resource = pxamci_resources,
68 };
69
pxa_set_mci_info(struct pxamci_platform_data * info)70 void __init pxa_set_mci_info(struct pxamci_platform_data *info)
71 {
72 pxa_register_device(&pxa_device_mci, info);
73 }
74
75
76 static struct pxa2xx_udc_mach_info pxa_udc_info;
77
pxa_set_udc_info(struct pxa2xx_udc_mach_info * info)78 void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info)
79 {
80 memcpy(&pxa_udc_info, info, sizeof *info);
81 }
82
83 static struct resource pxa2xx_udc_resources[] = {
84 [0] = {
85 .start = 0x40600000,
86 .end = 0x4060ffff,
87 .flags = IORESOURCE_MEM,
88 },
89 [1] = {
90 .start = IRQ_USB,
91 .end = IRQ_USB,
92 .flags = IORESOURCE_IRQ,
93 },
94 };
95
96 static u64 udc_dma_mask = ~(u32)0;
97
98 struct platform_device pxa25x_device_udc = {
99 .name = "pxa25x-udc",
100 .id = -1,
101 .resource = pxa2xx_udc_resources,
102 .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
103 .dev = {
104 .platform_data = &pxa_udc_info,
105 .dma_mask = &udc_dma_mask,
106 }
107 };
108
109 struct platform_device pxa27x_device_udc = {
110 .name = "pxa27x-udc",
111 .id = -1,
112 .resource = pxa2xx_udc_resources,
113 .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
114 .dev = {
115 .platform_data = &pxa_udc_info,
116 .dma_mask = &udc_dma_mask,
117 }
118 };
119
120 static struct resource pxafb_resources[] = {
121 [0] = {
122 .start = 0x44000000,
123 .end = 0x4400ffff,
124 .flags = IORESOURCE_MEM,
125 },
126 [1] = {
127 .start = IRQ_LCD,
128 .end = IRQ_LCD,
129 .flags = IORESOURCE_IRQ,
130 },
131 };
132
133 static u64 fb_dma_mask = ~(u64)0;
134
135 struct platform_device pxa_device_fb = {
136 .name = "pxa2xx-fb",
137 .id = -1,
138 .dev = {
139 .dma_mask = &fb_dma_mask,
140 .coherent_dma_mask = 0xffffffff,
141 },
142 .num_resources = ARRAY_SIZE(pxafb_resources),
143 .resource = pxafb_resources,
144 };
145
set_pxa_fb_info(struct pxafb_mach_info * info)146 void __init set_pxa_fb_info(struct pxafb_mach_info *info)
147 {
148 pxa_register_device(&pxa_device_fb, info);
149 }
150
set_pxa_fb_parent(struct device * parent_dev)151 void __init set_pxa_fb_parent(struct device *parent_dev)
152 {
153 pxa_device_fb.dev.parent = parent_dev;
154 }
155
156 static struct resource pxa_resource_ffuart[] = {
157 {
158 .start = 0x40100000,
159 .end = 0x40100023,
160 .flags = IORESOURCE_MEM,
161 }, {
162 .start = IRQ_FFUART,
163 .end = IRQ_FFUART,
164 .flags = IORESOURCE_IRQ,
165 }
166 };
167
168 struct platform_device pxa_device_ffuart= {
169 .name = "pxa2xx-uart",
170 .id = 0,
171 .resource = pxa_resource_ffuart,
172 .num_resources = ARRAY_SIZE(pxa_resource_ffuart),
173 };
174
175 static struct resource pxa_resource_btuart[] = {
176 {
177 .start = 0x40200000,
178 .end = 0x40200023,
179 .flags = IORESOURCE_MEM,
180 }, {
181 .start = IRQ_BTUART,
182 .end = IRQ_BTUART,
183 .flags = IORESOURCE_IRQ,
184 }
185 };
186
187 struct platform_device pxa_device_btuart = {
188 .name = "pxa2xx-uart",
189 .id = 1,
190 .resource = pxa_resource_btuart,
191 .num_resources = ARRAY_SIZE(pxa_resource_btuart),
192 };
193
194 static struct resource pxa_resource_stuart[] = {
195 {
196 .start = 0x40700000,
197 .end = 0x40700023,
198 .flags = IORESOURCE_MEM,
199 }, {
200 .start = IRQ_STUART,
201 .end = IRQ_STUART,
202 .flags = IORESOURCE_IRQ,
203 }
204 };
205
206 struct platform_device pxa_device_stuart = {
207 .name = "pxa2xx-uart",
208 .id = 2,
209 .resource = pxa_resource_stuart,
210 .num_resources = ARRAY_SIZE(pxa_resource_stuart),
211 };
212
213 static struct resource pxa_resource_hwuart[] = {
214 {
215 .start = 0x41600000,
216 .end = 0x4160002F,
217 .flags = IORESOURCE_MEM,
218 }, {
219 .start = IRQ_HWUART,
220 .end = IRQ_HWUART,
221 .flags = IORESOURCE_IRQ,
222 }
223 };
224
225 struct platform_device pxa_device_hwuart = {
226 .name = "pxa2xx-uart",
227 .id = 3,
228 .resource = pxa_resource_hwuart,
229 .num_resources = ARRAY_SIZE(pxa_resource_hwuart),
230 };
231
232 static struct resource pxai2c_resources[] = {
233 {
234 .start = 0x40301680,
235 .end = 0x403016a3,
236 .flags = IORESOURCE_MEM,
237 }, {
238 .start = IRQ_I2C,
239 .end = IRQ_I2C,
240 .flags = IORESOURCE_IRQ,
241 },
242 };
243
244 struct platform_device pxa_device_i2c = {
245 .name = "pxa2xx-i2c",
246 .id = 0,
247 .resource = pxai2c_resources,
248 .num_resources = ARRAY_SIZE(pxai2c_resources),
249 };
250
pxa_set_i2c_info(struct i2c_pxa_platform_data * info)251 void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
252 {
253 pxa_register_device(&pxa_device_i2c, info);
254 }
255
256 #ifdef CONFIG_PXA27x
257 static struct resource pxa27x_resources_i2c_power[] = {
258 {
259 .start = 0x40f00180,
260 .end = 0x40f001a3,
261 .flags = IORESOURCE_MEM,
262 }, {
263 .start = IRQ_PWRI2C,
264 .end = IRQ_PWRI2C,
265 .flags = IORESOURCE_IRQ,
266 },
267 };
268
269 struct platform_device pxa27x_device_i2c_power = {
270 .name = "pxa2xx-i2c",
271 .id = 1,
272 .resource = pxa27x_resources_i2c_power,
273 .num_resources = ARRAY_SIZE(pxa27x_resources_i2c_power),
274 };
275 #endif
276
277 #ifdef CONFIG_PXA3xx
278 static struct resource pxa3xx_resources_i2c_power[] = {
279 {
280 .start = 0x40f500c0,
281 .end = 0x40f500d3,
282 .flags = IORESOURCE_MEM,
283 }, {
284 .start = IRQ_PWRI2C,
285 .end = IRQ_PWRI2C,
286 .flags = IORESOURCE_IRQ,
287 },
288 };
289
290 struct platform_device pxa3xx_device_i2c_power = {
291 .name = "pxa2xx-i2c",
292 .id = 1,
293 .resource = pxa3xx_resources_i2c_power,
294 .num_resources = ARRAY_SIZE(pxa3xx_resources_i2c_power),
295 };
296 #endif
297
298 static struct resource pxai2s_resources[] = {
299 {
300 .start = 0x40400000,
301 .end = 0x40400083,
302 .flags = IORESOURCE_MEM,
303 }, {
304 .start = IRQ_I2S,
305 .end = IRQ_I2S,
306 .flags = IORESOURCE_IRQ,
307 },
308 };
309
310 struct platform_device pxa_device_i2s = {
311 .name = "pxa2xx-i2s",
312 .id = -1,
313 .resource = pxai2s_resources,
314 .num_resources = ARRAY_SIZE(pxai2s_resources),
315 };
316
317 static u64 pxaficp_dmamask = ~(u32)0;
318
319 struct platform_device pxa_device_ficp = {
320 .name = "pxa2xx-ir",
321 .id = -1,
322 .dev = {
323 .dma_mask = &pxaficp_dmamask,
324 .coherent_dma_mask = 0xffffffff,
325 },
326 };
327
pxa_set_ficp_info(struct pxaficp_platform_data * info)328 void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
329 {
330 pxa_register_device(&pxa_device_ficp, info);
331 }
332
333 static struct resource pxa_rtc_resources[] = {
334 [0] = {
335 .start = 0x40900000,
336 .end = 0x40900000 + 0x3b,
337 .flags = IORESOURCE_MEM,
338 },
339 [1] = {
340 .start = IRQ_RTC1Hz,
341 .end = IRQ_RTC1Hz,
342 .flags = IORESOURCE_IRQ,
343 },
344 [2] = {
345 .start = IRQ_RTCAlrm,
346 .end = IRQ_RTCAlrm,
347 .flags = IORESOURCE_IRQ,
348 },
349 };
350
351 struct platform_device sa1100_device_rtc = {
352 .name = "sa1100-rtc",
353 .id = -1,
354 };
355
356 struct platform_device pxa_device_rtc = {
357 .name = "pxa-rtc",
358 .id = -1,
359 .num_resources = ARRAY_SIZE(pxa_rtc_resources),
360 .resource = pxa_rtc_resources,
361 };
362
363 static struct resource pxa_ac97_resources[] = {
364 [0] = {
365 .start = 0x40500000,
366 .end = 0x40500000 + 0xfff,
367 .flags = IORESOURCE_MEM,
368 },
369 [1] = {
370 .start = IRQ_AC97,
371 .end = IRQ_AC97,
372 .flags = IORESOURCE_IRQ,
373 },
374 };
375
376 static u64 pxa_ac97_dmamask = 0xffffffffUL;
377
378 struct platform_device pxa_device_ac97 = {
379 .name = "pxa2xx-ac97",
380 .id = -1,
381 .dev = {
382 .dma_mask = &pxa_ac97_dmamask,
383 .coherent_dma_mask = 0xffffffff,
384 },
385 .num_resources = ARRAY_SIZE(pxa_ac97_resources),
386 .resource = pxa_ac97_resources,
387 };
388
pxa_set_ac97_info(pxa2xx_audio_ops_t * ops)389 void __init pxa_set_ac97_info(pxa2xx_audio_ops_t *ops)
390 {
391 pxa_register_device(&pxa_device_ac97, ops);
392 }
393
394 #ifdef CONFIG_PXA25x
395
396 static struct resource pxa25x_resource_pwm0[] = {
397 [0] = {
398 .start = 0x40b00000,
399 .end = 0x40b0000f,
400 .flags = IORESOURCE_MEM,
401 },
402 };
403
404 struct platform_device pxa25x_device_pwm0 = {
405 .name = "pxa25x-pwm",
406 .id = 0,
407 .resource = pxa25x_resource_pwm0,
408 .num_resources = ARRAY_SIZE(pxa25x_resource_pwm0),
409 };
410
411 static struct resource pxa25x_resource_pwm1[] = {
412 [0] = {
413 .start = 0x40c00000,
414 .end = 0x40c0000f,
415 .flags = IORESOURCE_MEM,
416 },
417 };
418
419 struct platform_device pxa25x_device_pwm1 = {
420 .name = "pxa25x-pwm",
421 .id = 1,
422 .resource = pxa25x_resource_pwm1,
423 .num_resources = ARRAY_SIZE(pxa25x_resource_pwm1),
424 };
425
426 static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32);
427
428 static struct resource pxa25x_resource_ssp[] = {
429 [0] = {
430 .start = 0x41000000,
431 .end = 0x4100001f,
432 .flags = IORESOURCE_MEM,
433 },
434 [1] = {
435 .start = IRQ_SSP,
436 .end = IRQ_SSP,
437 .flags = IORESOURCE_IRQ,
438 },
439 [2] = {
440 /* DRCMR for RX */
441 .start = 13,
442 .end = 13,
443 .flags = IORESOURCE_DMA,
444 },
445 [3] = {
446 /* DRCMR for TX */
447 .start = 14,
448 .end = 14,
449 .flags = IORESOURCE_DMA,
450 },
451 };
452
453 struct platform_device pxa25x_device_ssp = {
454 .name = "pxa25x-ssp",
455 .id = 0,
456 .dev = {
457 .dma_mask = &pxa25x_ssp_dma_mask,
458 .coherent_dma_mask = DMA_BIT_MASK(32),
459 },
460 .resource = pxa25x_resource_ssp,
461 .num_resources = ARRAY_SIZE(pxa25x_resource_ssp),
462 };
463
464 static u64 pxa25x_nssp_dma_mask = DMA_BIT_MASK(32);
465
466 static struct resource pxa25x_resource_nssp[] = {
467 [0] = {
468 .start = 0x41400000,
469 .end = 0x4140002f,
470 .flags = IORESOURCE_MEM,
471 },
472 [1] = {
473 .start = IRQ_NSSP,
474 .end = IRQ_NSSP,
475 .flags = IORESOURCE_IRQ,
476 },
477 [2] = {
478 /* DRCMR for RX */
479 .start = 15,
480 .end = 15,
481 .flags = IORESOURCE_DMA,
482 },
483 [3] = {
484 /* DRCMR for TX */
485 .start = 16,
486 .end = 16,
487 .flags = IORESOURCE_DMA,
488 },
489 };
490
491 struct platform_device pxa25x_device_nssp = {
492 .name = "pxa25x-nssp",
493 .id = 1,
494 .dev = {
495 .dma_mask = &pxa25x_nssp_dma_mask,
496 .coherent_dma_mask = DMA_BIT_MASK(32),
497 },
498 .resource = pxa25x_resource_nssp,
499 .num_resources = ARRAY_SIZE(pxa25x_resource_nssp),
500 };
501
502 static u64 pxa25x_assp_dma_mask = DMA_BIT_MASK(32);
503
504 static struct resource pxa25x_resource_assp[] = {
505 [0] = {
506 .start = 0x41500000,
507 .end = 0x4150002f,
508 .flags = IORESOURCE_MEM,
509 },
510 [1] = {
511 .start = IRQ_ASSP,
512 .end = IRQ_ASSP,
513 .flags = IORESOURCE_IRQ,
514 },
515 [2] = {
516 /* DRCMR for RX */
517 .start = 23,
518 .end = 23,
519 .flags = IORESOURCE_DMA,
520 },
521 [3] = {
522 /* DRCMR for TX */
523 .start = 24,
524 .end = 24,
525 .flags = IORESOURCE_DMA,
526 },
527 };
528
529 struct platform_device pxa25x_device_assp = {
530 /* ASSP is basically equivalent to NSSP */
531 .name = "pxa25x-nssp",
532 .id = 2,
533 .dev = {
534 .dma_mask = &pxa25x_assp_dma_mask,
535 .coherent_dma_mask = DMA_BIT_MASK(32),
536 },
537 .resource = pxa25x_resource_assp,
538 .num_resources = ARRAY_SIZE(pxa25x_resource_assp),
539 };
540 #endif /* CONFIG_PXA25x */
541
542 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
543
544 static struct resource pxa27x_resource_keypad[] = {
545 [0] = {
546 .start = 0x41500000,
547 .end = 0x4150004c,
548 .flags = IORESOURCE_MEM,
549 },
550 [1] = {
551 .start = IRQ_KEYPAD,
552 .end = IRQ_KEYPAD,
553 .flags = IORESOURCE_IRQ,
554 },
555 };
556
557 struct platform_device pxa27x_device_keypad = {
558 .name = "pxa27x-keypad",
559 .id = -1,
560 .resource = pxa27x_resource_keypad,
561 .num_resources = ARRAY_SIZE(pxa27x_resource_keypad),
562 };
563
pxa_set_keypad_info(struct pxa27x_keypad_platform_data * info)564 void __init pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info)
565 {
566 pxa_register_device(&pxa27x_device_keypad, info);
567 }
568
569 static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32);
570
571 static struct resource pxa27x_resource_ohci[] = {
572 [0] = {
573 .start = 0x4C000000,
574 .end = 0x4C00ff6f,
575 .flags = IORESOURCE_MEM,
576 },
577 [1] = {
578 .start = IRQ_USBH1,
579 .end = IRQ_USBH1,
580 .flags = IORESOURCE_IRQ,
581 },
582 };
583
584 struct platform_device pxa27x_device_ohci = {
585 .name = "pxa27x-ohci",
586 .id = -1,
587 .dev = {
588 .dma_mask = &pxa27x_ohci_dma_mask,
589 .coherent_dma_mask = DMA_BIT_MASK(32),
590 },
591 .num_resources = ARRAY_SIZE(pxa27x_resource_ohci),
592 .resource = pxa27x_resource_ohci,
593 };
594
pxa_set_ohci_info(struct pxaohci_platform_data * info)595 void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
596 {
597 pxa_register_device(&pxa27x_device_ohci, info);
598 }
599
600 static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32);
601
602 static struct resource pxa27x_resource_ssp1[] = {
603 [0] = {
604 .start = 0x41000000,
605 .end = 0x4100003f,
606 .flags = IORESOURCE_MEM,
607 },
608 [1] = {
609 .start = IRQ_SSP,
610 .end = IRQ_SSP,
611 .flags = IORESOURCE_IRQ,
612 },
613 [2] = {
614 /* DRCMR for RX */
615 .start = 13,
616 .end = 13,
617 .flags = IORESOURCE_DMA,
618 },
619 [3] = {
620 /* DRCMR for TX */
621 .start = 14,
622 .end = 14,
623 .flags = IORESOURCE_DMA,
624 },
625 };
626
627 struct platform_device pxa27x_device_ssp1 = {
628 .name = "pxa27x-ssp",
629 .id = 0,
630 .dev = {
631 .dma_mask = &pxa27x_ssp1_dma_mask,
632 .coherent_dma_mask = DMA_BIT_MASK(32),
633 },
634 .resource = pxa27x_resource_ssp1,
635 .num_resources = ARRAY_SIZE(pxa27x_resource_ssp1),
636 };
637
638 static u64 pxa27x_ssp2_dma_mask = DMA_BIT_MASK(32);
639
640 static struct resource pxa27x_resource_ssp2[] = {
641 [0] = {
642 .start = 0x41700000,
643 .end = 0x4170003f,
644 .flags = IORESOURCE_MEM,
645 },
646 [1] = {
647 .start = IRQ_SSP2,
648 .end = IRQ_SSP2,
649 .flags = IORESOURCE_IRQ,
650 },
651 [2] = {
652 /* DRCMR for RX */
653 .start = 15,
654 .end = 15,
655 .flags = IORESOURCE_DMA,
656 },
657 [3] = {
658 /* DRCMR for TX */
659 .start = 16,
660 .end = 16,
661 .flags = IORESOURCE_DMA,
662 },
663 };
664
665 struct platform_device pxa27x_device_ssp2 = {
666 .name = "pxa27x-ssp",
667 .id = 1,
668 .dev = {
669 .dma_mask = &pxa27x_ssp2_dma_mask,
670 .coherent_dma_mask = DMA_BIT_MASK(32),
671 },
672 .resource = pxa27x_resource_ssp2,
673 .num_resources = ARRAY_SIZE(pxa27x_resource_ssp2),
674 };
675
676 static u64 pxa27x_ssp3_dma_mask = DMA_BIT_MASK(32);
677
678 static struct resource pxa27x_resource_ssp3[] = {
679 [0] = {
680 .start = 0x41900000,
681 .end = 0x4190003f,
682 .flags = IORESOURCE_MEM,
683 },
684 [1] = {
685 .start = IRQ_SSP3,
686 .end = IRQ_SSP3,
687 .flags = IORESOURCE_IRQ,
688 },
689 [2] = {
690 /* DRCMR for RX */
691 .start = 66,
692 .end = 66,
693 .flags = IORESOURCE_DMA,
694 },
695 [3] = {
696 /* DRCMR for TX */
697 .start = 67,
698 .end = 67,
699 .flags = IORESOURCE_DMA,
700 },
701 };
702
703 struct platform_device pxa27x_device_ssp3 = {
704 .name = "pxa27x-ssp",
705 .id = 2,
706 .dev = {
707 .dma_mask = &pxa27x_ssp3_dma_mask,
708 .coherent_dma_mask = DMA_BIT_MASK(32),
709 },
710 .resource = pxa27x_resource_ssp3,
711 .num_resources = ARRAY_SIZE(pxa27x_resource_ssp3),
712 };
713
714 static struct resource pxa27x_resource_pwm0[] = {
715 [0] = {
716 .start = 0x40b00000,
717 .end = 0x40b0001f,
718 .flags = IORESOURCE_MEM,
719 },
720 };
721
722 struct platform_device pxa27x_device_pwm0 = {
723 .name = "pxa27x-pwm",
724 .id = 0,
725 .resource = pxa27x_resource_pwm0,
726 .num_resources = ARRAY_SIZE(pxa27x_resource_pwm0),
727 };
728
729 static struct resource pxa27x_resource_pwm1[] = {
730 [0] = {
731 .start = 0x40c00000,
732 .end = 0x40c0001f,
733 .flags = IORESOURCE_MEM,
734 },
735 };
736
737 struct platform_device pxa27x_device_pwm1 = {
738 .name = "pxa27x-pwm",
739 .id = 1,
740 .resource = pxa27x_resource_pwm1,
741 .num_resources = ARRAY_SIZE(pxa27x_resource_pwm1),
742 };
743
744 static struct resource pxa27x_resource_camera[] = {
745 [0] = {
746 .start = 0x50000000,
747 .end = 0x50000fff,
748 .flags = IORESOURCE_MEM,
749 },
750 [1] = {
751 .start = IRQ_CAMERA,
752 .end = IRQ_CAMERA,
753 .flags = IORESOURCE_IRQ,
754 },
755 };
756
757 static u64 pxa27x_dma_mask_camera = DMA_BIT_MASK(32);
758
759 static struct platform_device pxa27x_device_camera = {
760 .name = "pxa27x-camera",
761 .id = 0, /* This is used to put cameras on this interface */
762 .dev = {
763 .dma_mask = &pxa27x_dma_mask_camera,
764 .coherent_dma_mask = 0xffffffff,
765 },
766 .num_resources = ARRAY_SIZE(pxa27x_resource_camera),
767 .resource = pxa27x_resource_camera,
768 };
769
pxa_set_camera_info(struct pxacamera_platform_data * info)770 void __init pxa_set_camera_info(struct pxacamera_platform_data *info)
771 {
772 pxa_register_device(&pxa27x_device_camera, info);
773 }
774 #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
775
776 #ifdef CONFIG_PXA3xx
777 static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);
778
779 static struct resource pxa3xx_resource_ssp4[] = {
780 [0] = {
781 .start = 0x41a00000,
782 .end = 0x41a0003f,
783 .flags = IORESOURCE_MEM,
784 },
785 [1] = {
786 .start = IRQ_SSP4,
787 .end = IRQ_SSP4,
788 .flags = IORESOURCE_IRQ,
789 },
790 [2] = {
791 /* DRCMR for RX */
792 .start = 2,
793 .end = 2,
794 .flags = IORESOURCE_DMA,
795 },
796 [3] = {
797 /* DRCMR for TX */
798 .start = 3,
799 .end = 3,
800 .flags = IORESOURCE_DMA,
801 },
802 };
803
804 struct platform_device pxa3xx_device_ssp4 = {
805 /* PXA3xx SSP is basically equivalent to PXA27x */
806 .name = "pxa27x-ssp",
807 .id = 3,
808 .dev = {
809 .dma_mask = &pxa3xx_ssp4_dma_mask,
810 .coherent_dma_mask = DMA_BIT_MASK(32),
811 },
812 .resource = pxa3xx_resource_ssp4,
813 .num_resources = ARRAY_SIZE(pxa3xx_resource_ssp4),
814 };
815
816 static struct resource pxa3xx_resources_mci2[] = {
817 [0] = {
818 .start = 0x42000000,
819 .end = 0x42000fff,
820 .flags = IORESOURCE_MEM,
821 },
822 [1] = {
823 .start = IRQ_MMC2,
824 .end = IRQ_MMC2,
825 .flags = IORESOURCE_IRQ,
826 },
827 [2] = {
828 .start = 93,
829 .end = 93,
830 .flags = IORESOURCE_DMA,
831 },
832 [3] = {
833 .start = 94,
834 .end = 94,
835 .flags = IORESOURCE_DMA,
836 },
837 };
838
839 struct platform_device pxa3xx_device_mci2 = {
840 .name = "pxa2xx-mci",
841 .id = 1,
842 .dev = {
843 .dma_mask = &pxamci_dmamask,
844 .coherent_dma_mask = 0xffffffff,
845 },
846 .num_resources = ARRAY_SIZE(pxa3xx_resources_mci2),
847 .resource = pxa3xx_resources_mci2,
848 };
849
pxa3xx_set_mci2_info(struct pxamci_platform_data * info)850 void __init pxa3xx_set_mci2_info(struct pxamci_platform_data *info)
851 {
852 pxa_register_device(&pxa3xx_device_mci2, info);
853 }
854
855 static struct resource pxa3xx_resources_mci3[] = {
856 [0] = {
857 .start = 0x42500000,
858 .end = 0x42500fff,
859 .flags = IORESOURCE_MEM,
860 },
861 [1] = {
862 .start = IRQ_MMC3,
863 .end = IRQ_MMC3,
864 .flags = IORESOURCE_IRQ,
865 },
866 [2] = {
867 .start = 100,
868 .end = 100,
869 .flags = IORESOURCE_DMA,
870 },
871 [3] = {
872 .start = 101,
873 .end = 101,
874 .flags = IORESOURCE_DMA,
875 },
876 };
877
878 struct platform_device pxa3xx_device_mci3 = {
879 .name = "pxa2xx-mci",
880 .id = 2,
881 .dev = {
882 .dma_mask = &pxamci_dmamask,
883 .coherent_dma_mask = 0xffffffff,
884 },
885 .num_resources = ARRAY_SIZE(pxa3xx_resources_mci3),
886 .resource = pxa3xx_resources_mci3,
887 };
888
pxa3xx_set_mci3_info(struct pxamci_platform_data * info)889 void __init pxa3xx_set_mci3_info(struct pxamci_platform_data *info)
890 {
891 pxa_register_device(&pxa3xx_device_mci3, info);
892 }
893
894 static struct resource pxa3xx_resources_nand[] = {
895 [0] = {
896 .start = 0x43100000,
897 .end = 0x43100053,
898 .flags = IORESOURCE_MEM,
899 },
900 [1] = {
901 .start = IRQ_NAND,
902 .end = IRQ_NAND,
903 .flags = IORESOURCE_IRQ,
904 },
905 [2] = {
906 /* DRCMR for Data DMA */
907 .start = 97,
908 .end = 97,
909 .flags = IORESOURCE_DMA,
910 },
911 [3] = {
912 /* DRCMR for Command DMA */
913 .start = 99,
914 .end = 99,
915 .flags = IORESOURCE_DMA,
916 },
917 };
918
919 static u64 pxa3xx_nand_dma_mask = DMA_BIT_MASK(32);
920
921 struct platform_device pxa3xx_device_nand = {
922 .name = "pxa3xx-nand",
923 .id = -1,
924 .dev = {
925 .dma_mask = &pxa3xx_nand_dma_mask,
926 .coherent_dma_mask = DMA_BIT_MASK(32),
927 },
928 .num_resources = ARRAY_SIZE(pxa3xx_resources_nand),
929 .resource = pxa3xx_resources_nand,
930 };
931
pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data * info)932 void __init pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info)
933 {
934 pxa_register_device(&pxa3xx_device_nand, info);
935 }
936 #endif /* CONFIG_PXA3xx */
937
938 /* pxa2xx-spi platform-device ID equals respective SSP platform-device ID + 1.
939 * See comment in arch/arm/mach-pxa/ssp.c::ssp_probe() */
pxa2xx_set_spi_info(unsigned id,struct pxa2xx_spi_master * info)940 void __init pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info)
941 {
942 struct platform_device *pd;
943
944 pd = platform_device_alloc("pxa2xx-spi", id);
945 if (pd == NULL) {
946 printk(KERN_ERR "pxa2xx-spi: failed to allocate device id %d\n",
947 id);
948 return;
949 }
950
951 pd->dev.platform_data = info;
952 platform_device_add(pd);
953 }
954