1 /*
2 * drivers/s390/net/qeth_core_main.c
3 *
4 * Copyright IBM Corp. 2007
5 * Author(s): Utz Bacher <utz.bacher@de.ibm.com>,
6 * Frank Pavlic <fpavlic@de.ibm.com>,
7 * Thomas Spatzier <tspat@de.ibm.com>,
8 * Frank Blaschka <frank.blaschka@de.ibm.com>
9 */
10
11 #define KMSG_COMPONENT "qeth"
12 #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
13
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/string.h>
17 #include <linux/errno.h>
18 #include <linux/kernel.h>
19 #include <linux/ip.h>
20 #include <linux/ipv6.h>
21 #include <linux/tcp.h>
22 #include <linux/mii.h>
23 #include <linux/kthread.h>
24
25 #include <asm/ebcdic.h>
26 #include <asm/io.h>
27
28 #include "qeth_core.h"
29 #include "qeth_core_offl.h"
30
31 struct qeth_dbf_info qeth_dbf[QETH_DBF_INFOS] = {
32 /* define dbf - Name, Pages, Areas, Maxlen, Level, View, Handle */
33 /* N P A M L V H */
34 [QETH_DBF_SETUP] = {"qeth_setup",
35 8, 1, 8, 5, &debug_hex_ascii_view, NULL},
36 [QETH_DBF_QERR] = {"qeth_qerr",
37 2, 1, 8, 2, &debug_hex_ascii_view, NULL},
38 [QETH_DBF_TRACE] = {"qeth_trace",
39 4, 1, 8, 3, &debug_hex_ascii_view, NULL},
40 [QETH_DBF_MSG] = {"qeth_msg",
41 8, 1, 128, 3, &debug_sprintf_view, NULL},
42 [QETH_DBF_SENSE] = {"qeth_sense",
43 2, 1, 64, 2, &debug_hex_ascii_view, NULL},
44 [QETH_DBF_MISC] = {"qeth_misc",
45 2, 1, 256, 2, &debug_hex_ascii_view, NULL},
46 [QETH_DBF_CTRL] = {"qeth_control",
47 8, 1, QETH_DBF_CTRL_LEN, 5, &debug_hex_ascii_view, NULL},
48 };
49 EXPORT_SYMBOL_GPL(qeth_dbf);
50
51 struct qeth_card_list_struct qeth_core_card_list;
52 EXPORT_SYMBOL_GPL(qeth_core_card_list);
53 struct kmem_cache *qeth_core_header_cache;
54 EXPORT_SYMBOL_GPL(qeth_core_header_cache);
55
56 static struct device *qeth_core_root_dev;
57 static unsigned int known_devices[][10] = QETH_MODELLIST_ARRAY;
58 static struct lock_class_key qdio_out_skb_queue_key;
59
60 static void qeth_send_control_data_cb(struct qeth_channel *,
61 struct qeth_cmd_buffer *);
62 static int qeth_issue_next_read(struct qeth_card *);
63 static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *);
64 static void qeth_setup_ccw(struct qeth_channel *, unsigned char *, __u32);
65 static void qeth_free_buffer_pool(struct qeth_card *);
66 static int qeth_qdio_establish(struct qeth_card *);
67
68
__qeth_fill_buffer_frag(struct sk_buff * skb,struct qdio_buffer * buffer,int is_tso,int * next_element_to_fill)69 static inline void __qeth_fill_buffer_frag(struct sk_buff *skb,
70 struct qdio_buffer *buffer, int is_tso,
71 int *next_element_to_fill)
72 {
73 struct skb_frag_struct *frag;
74 int fragno;
75 unsigned long addr;
76 int element, cnt, dlen;
77
78 fragno = skb_shinfo(skb)->nr_frags;
79 element = *next_element_to_fill;
80 dlen = 0;
81
82 if (is_tso)
83 buffer->element[element].flags =
84 SBAL_FLAGS_MIDDLE_FRAG;
85 else
86 buffer->element[element].flags =
87 SBAL_FLAGS_FIRST_FRAG;
88 dlen = skb->len - skb->data_len;
89 if (dlen) {
90 buffer->element[element].addr = skb->data;
91 buffer->element[element].length = dlen;
92 element++;
93 }
94 for (cnt = 0; cnt < fragno; cnt++) {
95 frag = &skb_shinfo(skb)->frags[cnt];
96 addr = (page_to_pfn(frag->page) << PAGE_SHIFT) +
97 frag->page_offset;
98 buffer->element[element].addr = (char *)addr;
99 buffer->element[element].length = frag->size;
100 if (cnt < (fragno - 1))
101 buffer->element[element].flags =
102 SBAL_FLAGS_MIDDLE_FRAG;
103 else
104 buffer->element[element].flags =
105 SBAL_FLAGS_LAST_FRAG;
106 element++;
107 }
108 *next_element_to_fill = element;
109 }
110
qeth_get_cardname(struct qeth_card * card)111 static inline const char *qeth_get_cardname(struct qeth_card *card)
112 {
113 if (card->info.guestlan) {
114 switch (card->info.type) {
115 case QETH_CARD_TYPE_OSAE:
116 return " Guest LAN QDIO";
117 case QETH_CARD_TYPE_IQD:
118 return " Guest LAN Hiper";
119 default:
120 return " unknown";
121 }
122 } else {
123 switch (card->info.type) {
124 case QETH_CARD_TYPE_OSAE:
125 return " OSD Express";
126 case QETH_CARD_TYPE_IQD:
127 return " HiperSockets";
128 case QETH_CARD_TYPE_OSN:
129 return " OSN QDIO";
130 default:
131 return " unknown";
132 }
133 }
134 return " n/a";
135 }
136
137 /* max length to be returned: 14 */
qeth_get_cardname_short(struct qeth_card * card)138 const char *qeth_get_cardname_short(struct qeth_card *card)
139 {
140 if (card->info.guestlan) {
141 switch (card->info.type) {
142 case QETH_CARD_TYPE_OSAE:
143 return "GuestLAN QDIO";
144 case QETH_CARD_TYPE_IQD:
145 return "GuestLAN Hiper";
146 default:
147 return "unknown";
148 }
149 } else {
150 switch (card->info.type) {
151 case QETH_CARD_TYPE_OSAE:
152 switch (card->info.link_type) {
153 case QETH_LINK_TYPE_FAST_ETH:
154 return "OSD_100";
155 case QETH_LINK_TYPE_HSTR:
156 return "HSTR";
157 case QETH_LINK_TYPE_GBIT_ETH:
158 return "OSD_1000";
159 case QETH_LINK_TYPE_10GBIT_ETH:
160 return "OSD_10GIG";
161 case QETH_LINK_TYPE_LANE_ETH100:
162 return "OSD_FE_LANE";
163 case QETH_LINK_TYPE_LANE_TR:
164 return "OSD_TR_LANE";
165 case QETH_LINK_TYPE_LANE_ETH1000:
166 return "OSD_GbE_LANE";
167 case QETH_LINK_TYPE_LANE:
168 return "OSD_ATM_LANE";
169 default:
170 return "OSD_Express";
171 }
172 case QETH_CARD_TYPE_IQD:
173 return "HiperSockets";
174 case QETH_CARD_TYPE_OSN:
175 return "OSN";
176 default:
177 return "unknown";
178 }
179 }
180 return "n/a";
181 }
182
qeth_set_allowed_threads(struct qeth_card * card,unsigned long threads,int clear_start_mask)183 void qeth_set_allowed_threads(struct qeth_card *card, unsigned long threads,
184 int clear_start_mask)
185 {
186 unsigned long flags;
187
188 spin_lock_irqsave(&card->thread_mask_lock, flags);
189 card->thread_allowed_mask = threads;
190 if (clear_start_mask)
191 card->thread_start_mask &= threads;
192 spin_unlock_irqrestore(&card->thread_mask_lock, flags);
193 wake_up(&card->wait_q);
194 }
195 EXPORT_SYMBOL_GPL(qeth_set_allowed_threads);
196
qeth_threads_running(struct qeth_card * card,unsigned long threads)197 int qeth_threads_running(struct qeth_card *card, unsigned long threads)
198 {
199 unsigned long flags;
200 int rc = 0;
201
202 spin_lock_irqsave(&card->thread_mask_lock, flags);
203 rc = (card->thread_running_mask & threads);
204 spin_unlock_irqrestore(&card->thread_mask_lock, flags);
205 return rc;
206 }
207 EXPORT_SYMBOL_GPL(qeth_threads_running);
208
qeth_wait_for_threads(struct qeth_card * card,unsigned long threads)209 int qeth_wait_for_threads(struct qeth_card *card, unsigned long threads)
210 {
211 return wait_event_interruptible(card->wait_q,
212 qeth_threads_running(card, threads) == 0);
213 }
214 EXPORT_SYMBOL_GPL(qeth_wait_for_threads);
215
qeth_clear_working_pool_list(struct qeth_card * card)216 void qeth_clear_working_pool_list(struct qeth_card *card)
217 {
218 struct qeth_buffer_pool_entry *pool_entry, *tmp;
219
220 QETH_DBF_TEXT(TRACE, 5, "clwrklst");
221 list_for_each_entry_safe(pool_entry, tmp,
222 &card->qdio.in_buf_pool.entry_list, list){
223 list_del(&pool_entry->list);
224 }
225 }
226 EXPORT_SYMBOL_GPL(qeth_clear_working_pool_list);
227
qeth_alloc_buffer_pool(struct qeth_card * card)228 static int qeth_alloc_buffer_pool(struct qeth_card *card)
229 {
230 struct qeth_buffer_pool_entry *pool_entry;
231 void *ptr;
232 int i, j;
233
234 QETH_DBF_TEXT(TRACE, 5, "alocpool");
235 for (i = 0; i < card->qdio.init_pool.buf_count; ++i) {
236 pool_entry = kmalloc(sizeof(*pool_entry), GFP_KERNEL);
237 if (!pool_entry) {
238 qeth_free_buffer_pool(card);
239 return -ENOMEM;
240 }
241 for (j = 0; j < QETH_MAX_BUFFER_ELEMENTS(card); ++j) {
242 ptr = (void *) __get_free_page(GFP_KERNEL);
243 if (!ptr) {
244 while (j > 0)
245 free_page((unsigned long)
246 pool_entry->elements[--j]);
247 kfree(pool_entry);
248 qeth_free_buffer_pool(card);
249 return -ENOMEM;
250 }
251 pool_entry->elements[j] = ptr;
252 }
253 list_add(&pool_entry->init_list,
254 &card->qdio.init_pool.entry_list);
255 }
256 return 0;
257 }
258
qeth_realloc_buffer_pool(struct qeth_card * card,int bufcnt)259 int qeth_realloc_buffer_pool(struct qeth_card *card, int bufcnt)
260 {
261 QETH_DBF_TEXT(TRACE, 2, "realcbp");
262
263 if ((card->state != CARD_STATE_DOWN) &&
264 (card->state != CARD_STATE_RECOVER))
265 return -EPERM;
266
267 /* TODO: steel/add buffers from/to a running card's buffer pool (?) */
268 qeth_clear_working_pool_list(card);
269 qeth_free_buffer_pool(card);
270 card->qdio.in_buf_pool.buf_count = bufcnt;
271 card->qdio.init_pool.buf_count = bufcnt;
272 return qeth_alloc_buffer_pool(card);
273 }
274
qeth_set_large_send(struct qeth_card * card,enum qeth_large_send_types type)275 int qeth_set_large_send(struct qeth_card *card,
276 enum qeth_large_send_types type)
277 {
278 int rc = 0;
279
280 if (card->dev == NULL) {
281 card->options.large_send = type;
282 return 0;
283 }
284 if (card->state == CARD_STATE_UP)
285 netif_tx_disable(card->dev);
286 card->options.large_send = type;
287 switch (card->options.large_send) {
288 case QETH_LARGE_SEND_EDDP:
289 if (card->info.type != QETH_CARD_TYPE_IQD) {
290 card->dev->features |= NETIF_F_TSO | NETIF_F_SG |
291 NETIF_F_HW_CSUM;
292 } else {
293 card->dev->features &= ~(NETIF_F_TSO | NETIF_F_SG |
294 NETIF_F_HW_CSUM);
295 card->options.large_send = QETH_LARGE_SEND_NO;
296 rc = -EOPNOTSUPP;
297 }
298 break;
299 case QETH_LARGE_SEND_TSO:
300 if (qeth_is_supported(card, IPA_OUTBOUND_TSO)) {
301 card->dev->features |= NETIF_F_TSO | NETIF_F_SG |
302 NETIF_F_HW_CSUM;
303 } else {
304 card->dev->features &= ~(NETIF_F_TSO | NETIF_F_SG |
305 NETIF_F_HW_CSUM);
306 card->options.large_send = QETH_LARGE_SEND_NO;
307 rc = -EOPNOTSUPP;
308 }
309 break;
310 default: /* includes QETH_LARGE_SEND_NO */
311 card->dev->features &= ~(NETIF_F_TSO | NETIF_F_SG |
312 NETIF_F_HW_CSUM);
313 break;
314 }
315 if (card->state == CARD_STATE_UP)
316 netif_wake_queue(card->dev);
317 return rc;
318 }
319 EXPORT_SYMBOL_GPL(qeth_set_large_send);
320
qeth_issue_next_read(struct qeth_card * card)321 static int qeth_issue_next_read(struct qeth_card *card)
322 {
323 int rc;
324 struct qeth_cmd_buffer *iob;
325
326 QETH_DBF_TEXT(TRACE, 5, "issnxrd");
327 if (card->read.state != CH_STATE_UP)
328 return -EIO;
329 iob = qeth_get_buffer(&card->read);
330 if (!iob) {
331 dev_warn(&card->gdev->dev, "The qeth device driver "
332 "failed to recover an error on the device\n");
333 QETH_DBF_MESSAGE(2, "%s issue_next_read failed: no iob "
334 "available\n", dev_name(&card->gdev->dev));
335 return -ENOMEM;
336 }
337 qeth_setup_ccw(&card->read, iob->data, QETH_BUFSIZE);
338 QETH_DBF_TEXT(TRACE, 6, "noirqpnd");
339 rc = ccw_device_start(card->read.ccwdev, &card->read.ccw,
340 (addr_t) iob, 0, 0);
341 if (rc) {
342 QETH_DBF_MESSAGE(2, "%s error in starting next read ccw! "
343 "rc=%i\n", dev_name(&card->gdev->dev), rc);
344 atomic_set(&card->read.irq_pending, 0);
345 qeth_schedule_recovery(card);
346 wake_up(&card->wait_q);
347 }
348 return rc;
349 }
350
qeth_alloc_reply(struct qeth_card * card)351 static struct qeth_reply *qeth_alloc_reply(struct qeth_card *card)
352 {
353 struct qeth_reply *reply;
354
355 reply = kzalloc(sizeof(struct qeth_reply), GFP_ATOMIC);
356 if (reply) {
357 atomic_set(&reply->refcnt, 1);
358 atomic_set(&reply->received, 0);
359 reply->card = card;
360 };
361 return reply;
362 }
363
qeth_get_reply(struct qeth_reply * reply)364 static void qeth_get_reply(struct qeth_reply *reply)
365 {
366 WARN_ON(atomic_read(&reply->refcnt) <= 0);
367 atomic_inc(&reply->refcnt);
368 }
369
qeth_put_reply(struct qeth_reply * reply)370 static void qeth_put_reply(struct qeth_reply *reply)
371 {
372 WARN_ON(atomic_read(&reply->refcnt) <= 0);
373 if (atomic_dec_and_test(&reply->refcnt))
374 kfree(reply);
375 }
376
qeth_issue_ipa_msg(struct qeth_ipa_cmd * cmd,int rc,struct qeth_card * card)377 static void qeth_issue_ipa_msg(struct qeth_ipa_cmd *cmd, int rc,
378 struct qeth_card *card)
379 {
380 char *ipa_name;
381 int com = cmd->hdr.command;
382 ipa_name = qeth_get_ipa_cmd_name(com);
383 if (rc)
384 QETH_DBF_MESSAGE(2, "IPA: %s(x%X) for %s returned x%X \"%s\"\n",
385 ipa_name, com, QETH_CARD_IFNAME(card),
386 rc, qeth_get_ipa_msg(rc));
387 else
388 QETH_DBF_MESSAGE(5, "IPA: %s(x%X) for %s succeeded\n",
389 ipa_name, com, QETH_CARD_IFNAME(card));
390 }
391
qeth_check_ipa_data(struct qeth_card * card,struct qeth_cmd_buffer * iob)392 static struct qeth_ipa_cmd *qeth_check_ipa_data(struct qeth_card *card,
393 struct qeth_cmd_buffer *iob)
394 {
395 struct qeth_ipa_cmd *cmd = NULL;
396
397 QETH_DBF_TEXT(TRACE, 5, "chkipad");
398 if (IS_IPA(iob->data)) {
399 cmd = (struct qeth_ipa_cmd *) PDU_ENCAPSULATION(iob->data);
400 if (IS_IPA_REPLY(cmd)) {
401 if (cmd->hdr.command < IPA_CMD_SETCCID ||
402 cmd->hdr.command > IPA_CMD_MODCCID)
403 qeth_issue_ipa_msg(cmd,
404 cmd->hdr.return_code, card);
405 return cmd;
406 } else {
407 switch (cmd->hdr.command) {
408 case IPA_CMD_STOPLAN:
409 dev_warn(&card->gdev->dev,
410 "The link for interface %s on CHPID"
411 " 0x%X failed\n",
412 QETH_CARD_IFNAME(card),
413 card->info.chpid);
414 card->lan_online = 0;
415 if (card->dev && netif_carrier_ok(card->dev))
416 netif_carrier_off(card->dev);
417 return NULL;
418 case IPA_CMD_STARTLAN:
419 dev_info(&card->gdev->dev,
420 "The link for %s on CHPID 0x%X has"
421 " been restored\n",
422 QETH_CARD_IFNAME(card),
423 card->info.chpid);
424 netif_carrier_on(card->dev);
425 card->lan_online = 1;
426 qeth_schedule_recovery(card);
427 return NULL;
428 case IPA_CMD_MODCCID:
429 return cmd;
430 case IPA_CMD_REGISTER_LOCAL_ADDR:
431 QETH_DBF_TEXT(TRACE, 3, "irla");
432 break;
433 case IPA_CMD_UNREGISTER_LOCAL_ADDR:
434 QETH_DBF_TEXT(TRACE, 3, "urla");
435 break;
436 default:
437 QETH_DBF_MESSAGE(2, "Received data is IPA "
438 "but not a reply!\n");
439 break;
440 }
441 }
442 }
443 return cmd;
444 }
445
qeth_clear_ipacmd_list(struct qeth_card * card)446 void qeth_clear_ipacmd_list(struct qeth_card *card)
447 {
448 struct qeth_reply *reply, *r;
449 unsigned long flags;
450
451 QETH_DBF_TEXT(TRACE, 4, "clipalst");
452
453 spin_lock_irqsave(&card->lock, flags);
454 list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
455 qeth_get_reply(reply);
456 reply->rc = -EIO;
457 atomic_inc(&reply->received);
458 list_del_init(&reply->list);
459 wake_up(&reply->wait_q);
460 qeth_put_reply(reply);
461 }
462 spin_unlock_irqrestore(&card->lock, flags);
463 }
464 EXPORT_SYMBOL_GPL(qeth_clear_ipacmd_list);
465
qeth_check_idx_response(unsigned char * buffer)466 static int qeth_check_idx_response(unsigned char *buffer)
467 {
468 if (!buffer)
469 return 0;
470
471 QETH_DBF_HEX(CTRL, 2, buffer, QETH_DBF_CTRL_LEN);
472 if ((buffer[2] & 0xc0) == 0xc0) {
473 QETH_DBF_MESSAGE(2, "received an IDX TERMINATE "
474 "with cause code 0x%02x%s\n",
475 buffer[4],
476 ((buffer[4] == 0x22) ?
477 " -- try another portname" : ""));
478 QETH_DBF_TEXT(TRACE, 2, "ckidxres");
479 QETH_DBF_TEXT(TRACE, 2, " idxterm");
480 QETH_DBF_TEXT_(TRACE, 2, " rc%d", -EIO);
481 return -EIO;
482 }
483 return 0;
484 }
485
qeth_setup_ccw(struct qeth_channel * channel,unsigned char * iob,__u32 len)486 static void qeth_setup_ccw(struct qeth_channel *channel, unsigned char *iob,
487 __u32 len)
488 {
489 struct qeth_card *card;
490
491 QETH_DBF_TEXT(TRACE, 4, "setupccw");
492 card = CARD_FROM_CDEV(channel->ccwdev);
493 if (channel == &card->read)
494 memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
495 else
496 memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
497 channel->ccw.count = len;
498 channel->ccw.cda = (__u32) __pa(iob);
499 }
500
__qeth_get_buffer(struct qeth_channel * channel)501 static struct qeth_cmd_buffer *__qeth_get_buffer(struct qeth_channel *channel)
502 {
503 __u8 index;
504
505 QETH_DBF_TEXT(TRACE, 6, "getbuff");
506 index = channel->io_buf_no;
507 do {
508 if (channel->iob[index].state == BUF_STATE_FREE) {
509 channel->iob[index].state = BUF_STATE_LOCKED;
510 channel->io_buf_no = (channel->io_buf_no + 1) %
511 QETH_CMD_BUFFER_NO;
512 memset(channel->iob[index].data, 0, QETH_BUFSIZE);
513 return channel->iob + index;
514 }
515 index = (index + 1) % QETH_CMD_BUFFER_NO;
516 } while (index != channel->io_buf_no);
517
518 return NULL;
519 }
520
qeth_release_buffer(struct qeth_channel * channel,struct qeth_cmd_buffer * iob)521 void qeth_release_buffer(struct qeth_channel *channel,
522 struct qeth_cmd_buffer *iob)
523 {
524 unsigned long flags;
525
526 QETH_DBF_TEXT(TRACE, 6, "relbuff");
527 spin_lock_irqsave(&channel->iob_lock, flags);
528 memset(iob->data, 0, QETH_BUFSIZE);
529 iob->state = BUF_STATE_FREE;
530 iob->callback = qeth_send_control_data_cb;
531 iob->rc = 0;
532 spin_unlock_irqrestore(&channel->iob_lock, flags);
533 }
534 EXPORT_SYMBOL_GPL(qeth_release_buffer);
535
qeth_get_buffer(struct qeth_channel * channel)536 static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *channel)
537 {
538 struct qeth_cmd_buffer *buffer = NULL;
539 unsigned long flags;
540
541 spin_lock_irqsave(&channel->iob_lock, flags);
542 buffer = __qeth_get_buffer(channel);
543 spin_unlock_irqrestore(&channel->iob_lock, flags);
544 return buffer;
545 }
546
qeth_wait_for_buffer(struct qeth_channel * channel)547 struct qeth_cmd_buffer *qeth_wait_for_buffer(struct qeth_channel *channel)
548 {
549 struct qeth_cmd_buffer *buffer;
550 wait_event(channel->wait_q,
551 ((buffer = qeth_get_buffer(channel)) != NULL));
552 return buffer;
553 }
554 EXPORT_SYMBOL_GPL(qeth_wait_for_buffer);
555
qeth_clear_cmd_buffers(struct qeth_channel * channel)556 void qeth_clear_cmd_buffers(struct qeth_channel *channel)
557 {
558 int cnt;
559
560 for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
561 qeth_release_buffer(channel, &channel->iob[cnt]);
562 channel->buf_no = 0;
563 channel->io_buf_no = 0;
564 }
565 EXPORT_SYMBOL_GPL(qeth_clear_cmd_buffers);
566
qeth_send_control_data_cb(struct qeth_channel * channel,struct qeth_cmd_buffer * iob)567 static void qeth_send_control_data_cb(struct qeth_channel *channel,
568 struct qeth_cmd_buffer *iob)
569 {
570 struct qeth_card *card;
571 struct qeth_reply *reply, *r;
572 struct qeth_ipa_cmd *cmd;
573 unsigned long flags;
574 int keep_reply;
575
576 QETH_DBF_TEXT(TRACE, 4, "sndctlcb");
577
578 card = CARD_FROM_CDEV(channel->ccwdev);
579 if (qeth_check_idx_response(iob->data)) {
580 qeth_clear_ipacmd_list(card);
581 if (((iob->data[2] & 0xc0) == 0xc0) && iob->data[4] == 0xf6)
582 dev_err(&card->gdev->dev,
583 "The qeth device is not configured "
584 "for the OSI layer required by z/VM\n");
585 qeth_schedule_recovery(card);
586 goto out;
587 }
588
589 cmd = qeth_check_ipa_data(card, iob);
590 if ((cmd == NULL) && (card->state != CARD_STATE_DOWN))
591 goto out;
592 /*in case of OSN : check if cmd is set */
593 if (card->info.type == QETH_CARD_TYPE_OSN &&
594 cmd &&
595 cmd->hdr.command != IPA_CMD_STARTLAN &&
596 card->osn_info.assist_cb != NULL) {
597 card->osn_info.assist_cb(card->dev, cmd);
598 goto out;
599 }
600
601 spin_lock_irqsave(&card->lock, flags);
602 list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
603 if ((reply->seqno == QETH_IDX_COMMAND_SEQNO) ||
604 ((cmd) && (reply->seqno == cmd->hdr.seqno))) {
605 qeth_get_reply(reply);
606 list_del_init(&reply->list);
607 spin_unlock_irqrestore(&card->lock, flags);
608 keep_reply = 0;
609 if (reply->callback != NULL) {
610 if (cmd) {
611 reply->offset = (__u16)((char *)cmd -
612 (char *)iob->data);
613 keep_reply = reply->callback(card,
614 reply,
615 (unsigned long)cmd);
616 } else
617 keep_reply = reply->callback(card,
618 reply,
619 (unsigned long)iob);
620 }
621 if (cmd)
622 reply->rc = (u16) cmd->hdr.return_code;
623 else if (iob->rc)
624 reply->rc = iob->rc;
625 if (keep_reply) {
626 spin_lock_irqsave(&card->lock, flags);
627 list_add_tail(&reply->list,
628 &card->cmd_waiter_list);
629 spin_unlock_irqrestore(&card->lock, flags);
630 } else {
631 atomic_inc(&reply->received);
632 wake_up(&reply->wait_q);
633 }
634 qeth_put_reply(reply);
635 goto out;
636 }
637 }
638 spin_unlock_irqrestore(&card->lock, flags);
639 out:
640 memcpy(&card->seqno.pdu_hdr_ack,
641 QETH_PDU_HEADER_SEQ_NO(iob->data),
642 QETH_SEQ_NO_LENGTH);
643 qeth_release_buffer(channel, iob);
644 }
645
qeth_setup_channel(struct qeth_channel * channel)646 static int qeth_setup_channel(struct qeth_channel *channel)
647 {
648 int cnt;
649
650 QETH_DBF_TEXT(SETUP, 2, "setupch");
651 for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++) {
652 channel->iob[cnt].data = (char *)
653 kmalloc(QETH_BUFSIZE, GFP_DMA|GFP_KERNEL);
654 if (channel->iob[cnt].data == NULL)
655 break;
656 channel->iob[cnt].state = BUF_STATE_FREE;
657 channel->iob[cnt].channel = channel;
658 channel->iob[cnt].callback = qeth_send_control_data_cb;
659 channel->iob[cnt].rc = 0;
660 }
661 if (cnt < QETH_CMD_BUFFER_NO) {
662 while (cnt-- > 0)
663 kfree(channel->iob[cnt].data);
664 return -ENOMEM;
665 }
666 channel->buf_no = 0;
667 channel->io_buf_no = 0;
668 atomic_set(&channel->irq_pending, 0);
669 spin_lock_init(&channel->iob_lock);
670
671 init_waitqueue_head(&channel->wait_q);
672 return 0;
673 }
674
qeth_set_thread_start_bit(struct qeth_card * card,unsigned long thread)675 static int qeth_set_thread_start_bit(struct qeth_card *card,
676 unsigned long thread)
677 {
678 unsigned long flags;
679
680 spin_lock_irqsave(&card->thread_mask_lock, flags);
681 if (!(card->thread_allowed_mask & thread) ||
682 (card->thread_start_mask & thread)) {
683 spin_unlock_irqrestore(&card->thread_mask_lock, flags);
684 return -EPERM;
685 }
686 card->thread_start_mask |= thread;
687 spin_unlock_irqrestore(&card->thread_mask_lock, flags);
688 return 0;
689 }
690
qeth_clear_thread_start_bit(struct qeth_card * card,unsigned long thread)691 void qeth_clear_thread_start_bit(struct qeth_card *card, unsigned long thread)
692 {
693 unsigned long flags;
694
695 spin_lock_irqsave(&card->thread_mask_lock, flags);
696 card->thread_start_mask &= ~thread;
697 spin_unlock_irqrestore(&card->thread_mask_lock, flags);
698 wake_up(&card->wait_q);
699 }
700 EXPORT_SYMBOL_GPL(qeth_clear_thread_start_bit);
701
qeth_clear_thread_running_bit(struct qeth_card * card,unsigned long thread)702 void qeth_clear_thread_running_bit(struct qeth_card *card, unsigned long thread)
703 {
704 unsigned long flags;
705
706 spin_lock_irqsave(&card->thread_mask_lock, flags);
707 card->thread_running_mask &= ~thread;
708 spin_unlock_irqrestore(&card->thread_mask_lock, flags);
709 wake_up(&card->wait_q);
710 }
711 EXPORT_SYMBOL_GPL(qeth_clear_thread_running_bit);
712
__qeth_do_run_thread(struct qeth_card * card,unsigned long thread)713 static int __qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
714 {
715 unsigned long flags;
716 int rc = 0;
717
718 spin_lock_irqsave(&card->thread_mask_lock, flags);
719 if (card->thread_start_mask & thread) {
720 if ((card->thread_allowed_mask & thread) &&
721 !(card->thread_running_mask & thread)) {
722 rc = 1;
723 card->thread_start_mask &= ~thread;
724 card->thread_running_mask |= thread;
725 } else
726 rc = -EPERM;
727 }
728 spin_unlock_irqrestore(&card->thread_mask_lock, flags);
729 return rc;
730 }
731
qeth_do_run_thread(struct qeth_card * card,unsigned long thread)732 int qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
733 {
734 int rc = 0;
735
736 wait_event(card->wait_q,
737 (rc = __qeth_do_run_thread(card, thread)) >= 0);
738 return rc;
739 }
740 EXPORT_SYMBOL_GPL(qeth_do_run_thread);
741
qeth_schedule_recovery(struct qeth_card * card)742 void qeth_schedule_recovery(struct qeth_card *card)
743 {
744 QETH_DBF_TEXT(TRACE, 2, "startrec");
745 if (qeth_set_thread_start_bit(card, QETH_RECOVER_THREAD) == 0)
746 schedule_work(&card->kernel_thread_starter);
747 }
748 EXPORT_SYMBOL_GPL(qeth_schedule_recovery);
749
qeth_get_problem(struct ccw_device * cdev,struct irb * irb)750 static int qeth_get_problem(struct ccw_device *cdev, struct irb *irb)
751 {
752 int dstat, cstat;
753 char *sense;
754
755 sense = (char *) irb->ecw;
756 cstat = irb->scsw.cmd.cstat;
757 dstat = irb->scsw.cmd.dstat;
758
759 if (cstat & (SCHN_STAT_CHN_CTRL_CHK | SCHN_STAT_INTF_CTRL_CHK |
760 SCHN_STAT_CHN_DATA_CHK | SCHN_STAT_CHAIN_CHECK |
761 SCHN_STAT_PROT_CHECK | SCHN_STAT_PROG_CHECK)) {
762 QETH_DBF_TEXT(TRACE, 2, "CGENCHK");
763 dev_warn(&cdev->dev, "The qeth device driver "
764 "failed to recover an error on the device\n");
765 QETH_DBF_MESSAGE(2, "%s check on device dstat=x%x, cstat=x%x ",
766 dev_name(&cdev->dev), dstat, cstat);
767 print_hex_dump(KERN_WARNING, "qeth: irb ", DUMP_PREFIX_OFFSET,
768 16, 1, irb, 64, 1);
769 return 1;
770 }
771
772 if (dstat & DEV_STAT_UNIT_CHECK) {
773 if (sense[SENSE_RESETTING_EVENT_BYTE] &
774 SENSE_RESETTING_EVENT_FLAG) {
775 QETH_DBF_TEXT(TRACE, 2, "REVIND");
776 return 1;
777 }
778 if (sense[SENSE_COMMAND_REJECT_BYTE] &
779 SENSE_COMMAND_REJECT_FLAG) {
780 QETH_DBF_TEXT(TRACE, 2, "CMDREJi");
781 return 1;
782 }
783 if ((sense[2] == 0xaf) && (sense[3] == 0xfe)) {
784 QETH_DBF_TEXT(TRACE, 2, "AFFE");
785 return 1;
786 }
787 if ((!sense[0]) && (!sense[1]) && (!sense[2]) && (!sense[3])) {
788 QETH_DBF_TEXT(TRACE, 2, "ZEROSEN");
789 return 0;
790 }
791 QETH_DBF_TEXT(TRACE, 2, "DGENCHK");
792 return 1;
793 }
794 return 0;
795 }
796
__qeth_check_irb_error(struct ccw_device * cdev,unsigned long intparm,struct irb * irb)797 static long __qeth_check_irb_error(struct ccw_device *cdev,
798 unsigned long intparm, struct irb *irb)
799 {
800 if (!IS_ERR(irb))
801 return 0;
802
803 switch (PTR_ERR(irb)) {
804 case -EIO:
805 QETH_DBF_MESSAGE(2, "%s i/o-error on device\n",
806 dev_name(&cdev->dev));
807 QETH_DBF_TEXT(TRACE, 2, "ckirberr");
808 QETH_DBF_TEXT_(TRACE, 2, " rc%d", -EIO);
809 break;
810 case -ETIMEDOUT:
811 dev_warn(&cdev->dev, "A hardware operation timed out"
812 " on the device\n");
813 QETH_DBF_TEXT(TRACE, 2, "ckirberr");
814 QETH_DBF_TEXT_(TRACE, 2, " rc%d", -ETIMEDOUT);
815 if (intparm == QETH_RCD_PARM) {
816 struct qeth_card *card = CARD_FROM_CDEV(cdev);
817
818 if (card && (card->data.ccwdev == cdev)) {
819 card->data.state = CH_STATE_DOWN;
820 wake_up(&card->wait_q);
821 }
822 }
823 break;
824 default:
825 QETH_DBF_MESSAGE(2, "%s unknown error %ld on device\n",
826 dev_name(&cdev->dev), PTR_ERR(irb));
827 QETH_DBF_TEXT(TRACE, 2, "ckirberr");
828 QETH_DBF_TEXT(TRACE, 2, " rc???");
829 }
830 return PTR_ERR(irb);
831 }
832
qeth_irq(struct ccw_device * cdev,unsigned long intparm,struct irb * irb)833 static void qeth_irq(struct ccw_device *cdev, unsigned long intparm,
834 struct irb *irb)
835 {
836 int rc;
837 int cstat, dstat;
838 struct qeth_cmd_buffer *buffer;
839 struct qeth_channel *channel;
840 struct qeth_card *card;
841 struct qeth_cmd_buffer *iob;
842 __u8 index;
843
844 QETH_DBF_TEXT(TRACE, 5, "irq");
845
846 if (__qeth_check_irb_error(cdev, intparm, irb))
847 return;
848 cstat = irb->scsw.cmd.cstat;
849 dstat = irb->scsw.cmd.dstat;
850
851 card = CARD_FROM_CDEV(cdev);
852 if (!card)
853 return;
854
855 if (card->read.ccwdev == cdev) {
856 channel = &card->read;
857 QETH_DBF_TEXT(TRACE, 5, "read");
858 } else if (card->write.ccwdev == cdev) {
859 channel = &card->write;
860 QETH_DBF_TEXT(TRACE, 5, "write");
861 } else {
862 channel = &card->data;
863 QETH_DBF_TEXT(TRACE, 5, "data");
864 }
865 atomic_set(&channel->irq_pending, 0);
866
867 if (irb->scsw.cmd.fctl & (SCSW_FCTL_CLEAR_FUNC))
868 channel->state = CH_STATE_STOPPED;
869
870 if (irb->scsw.cmd.fctl & (SCSW_FCTL_HALT_FUNC))
871 channel->state = CH_STATE_HALTED;
872
873 /*let's wake up immediately on data channel*/
874 if ((channel == &card->data) && (intparm != 0) &&
875 (intparm != QETH_RCD_PARM))
876 goto out;
877
878 if (intparm == QETH_CLEAR_CHANNEL_PARM) {
879 QETH_DBF_TEXT(TRACE, 6, "clrchpar");
880 /* we don't have to handle this further */
881 intparm = 0;
882 }
883 if (intparm == QETH_HALT_CHANNEL_PARM) {
884 QETH_DBF_TEXT(TRACE, 6, "hltchpar");
885 /* we don't have to handle this further */
886 intparm = 0;
887 }
888 if ((dstat & DEV_STAT_UNIT_EXCEP) ||
889 (dstat & DEV_STAT_UNIT_CHECK) ||
890 (cstat)) {
891 if (irb->esw.esw0.erw.cons) {
892 dev_warn(&channel->ccwdev->dev,
893 "The qeth device driver failed to recover "
894 "an error on the device\n");
895 QETH_DBF_MESSAGE(2, "%s sense data available. cstat "
896 "0x%X dstat 0x%X\n",
897 dev_name(&channel->ccwdev->dev), cstat, dstat);
898 print_hex_dump(KERN_WARNING, "qeth: irb ",
899 DUMP_PREFIX_OFFSET, 16, 1, irb, 32, 1);
900 print_hex_dump(KERN_WARNING, "qeth: sense data ",
901 DUMP_PREFIX_OFFSET, 16, 1, irb->ecw, 32, 1);
902 }
903 if (intparm == QETH_RCD_PARM) {
904 channel->state = CH_STATE_DOWN;
905 goto out;
906 }
907 rc = qeth_get_problem(cdev, irb);
908 if (rc) {
909 qeth_clear_ipacmd_list(card);
910 qeth_schedule_recovery(card);
911 goto out;
912 }
913 }
914
915 if (intparm == QETH_RCD_PARM) {
916 channel->state = CH_STATE_RCD_DONE;
917 goto out;
918 }
919 if (intparm) {
920 buffer = (struct qeth_cmd_buffer *) __va((addr_t)intparm);
921 buffer->state = BUF_STATE_PROCESSED;
922 }
923 if (channel == &card->data)
924 return;
925 if (channel == &card->read &&
926 channel->state == CH_STATE_UP)
927 qeth_issue_next_read(card);
928
929 iob = channel->iob;
930 index = channel->buf_no;
931 while (iob[index].state == BUF_STATE_PROCESSED) {
932 if (iob[index].callback != NULL)
933 iob[index].callback(channel, iob + index);
934
935 index = (index + 1) % QETH_CMD_BUFFER_NO;
936 }
937 channel->buf_no = index;
938 out:
939 wake_up(&card->wait_q);
940 return;
941 }
942
qeth_clear_output_buffer(struct qeth_qdio_out_q * queue,struct qeth_qdio_out_buffer * buf)943 static void qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
944 struct qeth_qdio_out_buffer *buf)
945 {
946 int i;
947 struct sk_buff *skb;
948
949 /* is PCI flag set on buffer? */
950 if (buf->buffer->element[0].flags & 0x40)
951 atomic_dec(&queue->set_pci_flags_count);
952
953 skb = skb_dequeue(&buf->skb_list);
954 while (skb) {
955 atomic_dec(&skb->users);
956 dev_kfree_skb_any(skb);
957 skb = skb_dequeue(&buf->skb_list);
958 }
959 qeth_eddp_buf_release_contexts(buf);
960 for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(queue->card); ++i) {
961 if (buf->buffer->element[i].addr && buf->is_header[i])
962 kmem_cache_free(qeth_core_header_cache,
963 buf->buffer->element[i].addr);
964 buf->is_header[i] = 0;
965 buf->buffer->element[i].length = 0;
966 buf->buffer->element[i].addr = NULL;
967 buf->buffer->element[i].flags = 0;
968 }
969 buf->next_element_to_fill = 0;
970 atomic_set(&buf->state, QETH_QDIO_BUF_EMPTY);
971 }
972
qeth_clear_qdio_buffers(struct qeth_card * card)973 void qeth_clear_qdio_buffers(struct qeth_card *card)
974 {
975 int i, j;
976
977 QETH_DBF_TEXT(TRACE, 2, "clearqdbf");
978 /* clear outbound buffers to free skbs */
979 for (i = 0; i < card->qdio.no_out_queues; ++i)
980 if (card->qdio.out_qs[i]) {
981 for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
982 qeth_clear_output_buffer(card->qdio.out_qs[i],
983 &card->qdio.out_qs[i]->bufs[j]);
984 }
985 }
986 EXPORT_SYMBOL_GPL(qeth_clear_qdio_buffers);
987
qeth_free_buffer_pool(struct qeth_card * card)988 static void qeth_free_buffer_pool(struct qeth_card *card)
989 {
990 struct qeth_buffer_pool_entry *pool_entry, *tmp;
991 int i = 0;
992 QETH_DBF_TEXT(TRACE, 5, "freepool");
993 list_for_each_entry_safe(pool_entry, tmp,
994 &card->qdio.init_pool.entry_list, init_list){
995 for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i)
996 free_page((unsigned long)pool_entry->elements[i]);
997 list_del(&pool_entry->init_list);
998 kfree(pool_entry);
999 }
1000 }
1001
qeth_free_qdio_buffers(struct qeth_card * card)1002 static void qeth_free_qdio_buffers(struct qeth_card *card)
1003 {
1004 int i, j;
1005
1006 QETH_DBF_TEXT(TRACE, 2, "freeqdbf");
1007 if (atomic_xchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED) ==
1008 QETH_QDIO_UNINITIALIZED)
1009 return;
1010 kfree(card->qdio.in_q);
1011 card->qdio.in_q = NULL;
1012 /* inbound buffer pool */
1013 qeth_free_buffer_pool(card);
1014 /* free outbound qdio_qs */
1015 if (card->qdio.out_qs) {
1016 for (i = 0; i < card->qdio.no_out_queues; ++i) {
1017 for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
1018 qeth_clear_output_buffer(card->qdio.out_qs[i],
1019 &card->qdio.out_qs[i]->bufs[j]);
1020 kfree(card->qdio.out_qs[i]);
1021 }
1022 kfree(card->qdio.out_qs);
1023 card->qdio.out_qs = NULL;
1024 }
1025 }
1026
qeth_clean_channel(struct qeth_channel * channel)1027 static void qeth_clean_channel(struct qeth_channel *channel)
1028 {
1029 int cnt;
1030
1031 QETH_DBF_TEXT(SETUP, 2, "freech");
1032 for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
1033 kfree(channel->iob[cnt].data);
1034 }
1035
qeth_is_1920_device(struct qeth_card * card)1036 static int qeth_is_1920_device(struct qeth_card *card)
1037 {
1038 int single_queue = 0;
1039 struct ccw_device *ccwdev;
1040 struct channelPath_dsc {
1041 u8 flags;
1042 u8 lsn;
1043 u8 desc;
1044 u8 chpid;
1045 u8 swla;
1046 u8 zeroes;
1047 u8 chla;
1048 u8 chpp;
1049 } *chp_dsc;
1050
1051 QETH_DBF_TEXT(SETUP, 2, "chk_1920");
1052
1053 ccwdev = card->data.ccwdev;
1054 chp_dsc = (struct channelPath_dsc *)ccw_device_get_chp_desc(ccwdev, 0);
1055 if (chp_dsc != NULL) {
1056 /* CHPP field bit 6 == 1 -> single queue */
1057 single_queue = ((chp_dsc->chpp & 0x02) == 0x02);
1058 kfree(chp_dsc);
1059 }
1060 QETH_DBF_TEXT_(SETUP, 2, "rc:%x", single_queue);
1061 return single_queue;
1062 }
1063
qeth_init_qdio_info(struct qeth_card * card)1064 static void qeth_init_qdio_info(struct qeth_card *card)
1065 {
1066 QETH_DBF_TEXT(SETUP, 4, "intqdinf");
1067 atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
1068 /* inbound */
1069 card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
1070 card->qdio.init_pool.buf_count = QETH_IN_BUF_COUNT_DEFAULT;
1071 card->qdio.in_buf_pool.buf_count = card->qdio.init_pool.buf_count;
1072 INIT_LIST_HEAD(&card->qdio.in_buf_pool.entry_list);
1073 INIT_LIST_HEAD(&card->qdio.init_pool.entry_list);
1074 }
1075
qeth_set_intial_options(struct qeth_card * card)1076 static void qeth_set_intial_options(struct qeth_card *card)
1077 {
1078 card->options.route4.type = NO_ROUTER;
1079 card->options.route6.type = NO_ROUTER;
1080 card->options.checksum_type = QETH_CHECKSUM_DEFAULT;
1081 card->options.broadcast_mode = QETH_TR_BROADCAST_ALLRINGS;
1082 card->options.macaddr_mode = QETH_TR_MACADDR_NONCANONICAL;
1083 card->options.fake_broadcast = 0;
1084 card->options.add_hhlen = DEFAULT_ADD_HHLEN;
1085 card->options.performance_stats = 0;
1086 card->options.rx_sg_cb = QETH_RX_SG_CB;
1087 }
1088
qeth_do_start_thread(struct qeth_card * card,unsigned long thread)1089 static int qeth_do_start_thread(struct qeth_card *card, unsigned long thread)
1090 {
1091 unsigned long flags;
1092 int rc = 0;
1093
1094 spin_lock_irqsave(&card->thread_mask_lock, flags);
1095 QETH_DBF_TEXT_(TRACE, 4, " %02x%02x%02x",
1096 (u8) card->thread_start_mask,
1097 (u8) card->thread_allowed_mask,
1098 (u8) card->thread_running_mask);
1099 rc = (card->thread_start_mask & thread);
1100 spin_unlock_irqrestore(&card->thread_mask_lock, flags);
1101 return rc;
1102 }
1103
qeth_start_kernel_thread(struct work_struct * work)1104 static void qeth_start_kernel_thread(struct work_struct *work)
1105 {
1106 struct qeth_card *card = container_of(work, struct qeth_card,
1107 kernel_thread_starter);
1108 QETH_DBF_TEXT(TRACE , 2, "strthrd");
1109
1110 if (card->read.state != CH_STATE_UP &&
1111 card->write.state != CH_STATE_UP)
1112 return;
1113 if (qeth_do_start_thread(card, QETH_RECOVER_THREAD))
1114 kthread_run(card->discipline.recover, (void *) card,
1115 "qeth_recover");
1116 }
1117
qeth_setup_card(struct qeth_card * card)1118 static int qeth_setup_card(struct qeth_card *card)
1119 {
1120
1121 QETH_DBF_TEXT(SETUP, 2, "setupcrd");
1122 QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
1123
1124 card->read.state = CH_STATE_DOWN;
1125 card->write.state = CH_STATE_DOWN;
1126 card->data.state = CH_STATE_DOWN;
1127 card->state = CARD_STATE_DOWN;
1128 card->lan_online = 0;
1129 card->use_hard_stop = 0;
1130 card->dev = NULL;
1131 spin_lock_init(&card->vlanlock);
1132 spin_lock_init(&card->mclock);
1133 card->vlangrp = NULL;
1134 spin_lock_init(&card->lock);
1135 spin_lock_init(&card->ip_lock);
1136 spin_lock_init(&card->thread_mask_lock);
1137 card->thread_start_mask = 0;
1138 card->thread_allowed_mask = 0;
1139 card->thread_running_mask = 0;
1140 INIT_WORK(&card->kernel_thread_starter, qeth_start_kernel_thread);
1141 INIT_LIST_HEAD(&card->ip_list);
1142 card->ip_tbd_list = kmalloc(sizeof(struct list_head), GFP_KERNEL);
1143 if (!card->ip_tbd_list) {
1144 QETH_DBF_TEXT(SETUP, 0, "iptbdnom");
1145 return -ENOMEM;
1146 }
1147 INIT_LIST_HEAD(card->ip_tbd_list);
1148 INIT_LIST_HEAD(&card->cmd_waiter_list);
1149 init_waitqueue_head(&card->wait_q);
1150 /* intial options */
1151 qeth_set_intial_options(card);
1152 /* IP address takeover */
1153 INIT_LIST_HEAD(&card->ipato.entries);
1154 card->ipato.enabled = 0;
1155 card->ipato.invert4 = 0;
1156 card->ipato.invert6 = 0;
1157 /* init QDIO stuff */
1158 qeth_init_qdio_info(card);
1159 return 0;
1160 }
1161
qeth_core_sl_print(struct seq_file * m,struct service_level * slr)1162 static void qeth_core_sl_print(struct seq_file *m, struct service_level *slr)
1163 {
1164 struct qeth_card *card = container_of(slr, struct qeth_card,
1165 qeth_service_level);
1166 seq_printf(m, "qeth: %s firmware level %s\n", CARD_BUS_ID(card),
1167 card->info.mcl_level);
1168 }
1169
qeth_alloc_card(void)1170 static struct qeth_card *qeth_alloc_card(void)
1171 {
1172 struct qeth_card *card;
1173
1174 QETH_DBF_TEXT(SETUP, 2, "alloccrd");
1175 card = kzalloc(sizeof(struct qeth_card), GFP_DMA|GFP_KERNEL);
1176 if (!card)
1177 return NULL;
1178 QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
1179 if (qeth_setup_channel(&card->read)) {
1180 kfree(card);
1181 return NULL;
1182 }
1183 if (qeth_setup_channel(&card->write)) {
1184 qeth_clean_channel(&card->read);
1185 kfree(card);
1186 return NULL;
1187 }
1188 card->options.layer2 = -1;
1189 card->qeth_service_level.seq_print = qeth_core_sl_print;
1190 register_service_level(&card->qeth_service_level);
1191 return card;
1192 }
1193
qeth_determine_card_type(struct qeth_card * card)1194 static int qeth_determine_card_type(struct qeth_card *card)
1195 {
1196 int i = 0;
1197
1198 QETH_DBF_TEXT(SETUP, 2, "detcdtyp");
1199
1200 card->qdio.do_prio_queueing = QETH_PRIOQ_DEFAULT;
1201 card->qdio.default_out_queue = QETH_DEFAULT_QUEUE;
1202 while (known_devices[i][4]) {
1203 if ((CARD_RDEV(card)->id.dev_type == known_devices[i][2]) &&
1204 (CARD_RDEV(card)->id.dev_model == known_devices[i][3])) {
1205 card->info.type = known_devices[i][4];
1206 card->qdio.no_out_queues = known_devices[i][8];
1207 card->info.is_multicast_different = known_devices[i][9];
1208 if (qeth_is_1920_device(card)) {
1209 dev_info(&card->gdev->dev,
1210 "Priority Queueing not supported\n");
1211 card->qdio.no_out_queues = 1;
1212 card->qdio.default_out_queue = 0;
1213 }
1214 return 0;
1215 }
1216 i++;
1217 }
1218 card->info.type = QETH_CARD_TYPE_UNKNOWN;
1219 dev_err(&card->gdev->dev, "The adapter hardware is of an "
1220 "unknown type\n");
1221 return -ENOENT;
1222 }
1223
qeth_clear_channel(struct qeth_channel * channel)1224 static int qeth_clear_channel(struct qeth_channel *channel)
1225 {
1226 unsigned long flags;
1227 struct qeth_card *card;
1228 int rc;
1229
1230 QETH_DBF_TEXT(TRACE, 3, "clearch");
1231 card = CARD_FROM_CDEV(channel->ccwdev);
1232 spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
1233 rc = ccw_device_clear(channel->ccwdev, QETH_CLEAR_CHANNEL_PARM);
1234 spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
1235
1236 if (rc)
1237 return rc;
1238 rc = wait_event_interruptible_timeout(card->wait_q,
1239 channel->state == CH_STATE_STOPPED, QETH_TIMEOUT);
1240 if (rc == -ERESTARTSYS)
1241 return rc;
1242 if (channel->state != CH_STATE_STOPPED)
1243 return -ETIME;
1244 channel->state = CH_STATE_DOWN;
1245 return 0;
1246 }
1247
qeth_halt_channel(struct qeth_channel * channel)1248 static int qeth_halt_channel(struct qeth_channel *channel)
1249 {
1250 unsigned long flags;
1251 struct qeth_card *card;
1252 int rc;
1253
1254 QETH_DBF_TEXT(TRACE, 3, "haltch");
1255 card = CARD_FROM_CDEV(channel->ccwdev);
1256 spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
1257 rc = ccw_device_halt(channel->ccwdev, QETH_HALT_CHANNEL_PARM);
1258 spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
1259
1260 if (rc)
1261 return rc;
1262 rc = wait_event_interruptible_timeout(card->wait_q,
1263 channel->state == CH_STATE_HALTED, QETH_TIMEOUT);
1264 if (rc == -ERESTARTSYS)
1265 return rc;
1266 if (channel->state != CH_STATE_HALTED)
1267 return -ETIME;
1268 return 0;
1269 }
1270
qeth_halt_channels(struct qeth_card * card)1271 static int qeth_halt_channels(struct qeth_card *card)
1272 {
1273 int rc1 = 0, rc2 = 0, rc3 = 0;
1274
1275 QETH_DBF_TEXT(TRACE, 3, "haltchs");
1276 rc1 = qeth_halt_channel(&card->read);
1277 rc2 = qeth_halt_channel(&card->write);
1278 rc3 = qeth_halt_channel(&card->data);
1279 if (rc1)
1280 return rc1;
1281 if (rc2)
1282 return rc2;
1283 return rc3;
1284 }
1285
qeth_clear_channels(struct qeth_card * card)1286 static int qeth_clear_channels(struct qeth_card *card)
1287 {
1288 int rc1 = 0, rc2 = 0, rc3 = 0;
1289
1290 QETH_DBF_TEXT(TRACE, 3, "clearchs");
1291 rc1 = qeth_clear_channel(&card->read);
1292 rc2 = qeth_clear_channel(&card->write);
1293 rc3 = qeth_clear_channel(&card->data);
1294 if (rc1)
1295 return rc1;
1296 if (rc2)
1297 return rc2;
1298 return rc3;
1299 }
1300
qeth_clear_halt_card(struct qeth_card * card,int halt)1301 static int qeth_clear_halt_card(struct qeth_card *card, int halt)
1302 {
1303 int rc = 0;
1304
1305 QETH_DBF_TEXT(TRACE, 3, "clhacrd");
1306 QETH_DBF_HEX(TRACE, 3, &card, sizeof(void *));
1307
1308 if (halt)
1309 rc = qeth_halt_channels(card);
1310 if (rc)
1311 return rc;
1312 return qeth_clear_channels(card);
1313 }
1314
qeth_qdio_clear_card(struct qeth_card * card,int use_halt)1315 int qeth_qdio_clear_card(struct qeth_card *card, int use_halt)
1316 {
1317 int rc = 0;
1318
1319 QETH_DBF_TEXT(TRACE, 3, "qdioclr");
1320 switch (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ESTABLISHED,
1321 QETH_QDIO_CLEANING)) {
1322 case QETH_QDIO_ESTABLISHED:
1323 if (card->info.type == QETH_CARD_TYPE_IQD)
1324 rc = qdio_cleanup(CARD_DDEV(card),
1325 QDIO_FLAG_CLEANUP_USING_HALT);
1326 else
1327 rc = qdio_cleanup(CARD_DDEV(card),
1328 QDIO_FLAG_CLEANUP_USING_CLEAR);
1329 if (rc)
1330 QETH_DBF_TEXT_(TRACE, 3, "1err%d", rc);
1331 atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
1332 break;
1333 case QETH_QDIO_CLEANING:
1334 return rc;
1335 default:
1336 break;
1337 }
1338 rc = qeth_clear_halt_card(card, use_halt);
1339 if (rc)
1340 QETH_DBF_TEXT_(TRACE, 3, "2err%d", rc);
1341 card->state = CARD_STATE_DOWN;
1342 return rc;
1343 }
1344 EXPORT_SYMBOL_GPL(qeth_qdio_clear_card);
1345
qeth_read_conf_data(struct qeth_card * card,void ** buffer,int * length)1346 static int qeth_read_conf_data(struct qeth_card *card, void **buffer,
1347 int *length)
1348 {
1349 struct ciw *ciw;
1350 char *rcd_buf;
1351 int ret;
1352 struct qeth_channel *channel = &card->data;
1353 unsigned long flags;
1354
1355 /*
1356 * scan for RCD command in extended SenseID data
1357 */
1358 ciw = ccw_device_get_ciw(channel->ccwdev, CIW_TYPE_RCD);
1359 if (!ciw || ciw->cmd == 0)
1360 return -EOPNOTSUPP;
1361 rcd_buf = kzalloc(ciw->count, GFP_KERNEL | GFP_DMA);
1362 if (!rcd_buf)
1363 return -ENOMEM;
1364
1365 channel->ccw.cmd_code = ciw->cmd;
1366 channel->ccw.cda = (__u32) __pa(rcd_buf);
1367 channel->ccw.count = ciw->count;
1368 channel->ccw.flags = CCW_FLAG_SLI;
1369 channel->state = CH_STATE_RCD;
1370 spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
1371 ret = ccw_device_start_timeout(channel->ccwdev, &channel->ccw,
1372 QETH_RCD_PARM, LPM_ANYPATH, 0,
1373 QETH_RCD_TIMEOUT);
1374 spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
1375 if (!ret)
1376 wait_event(card->wait_q,
1377 (channel->state == CH_STATE_RCD_DONE ||
1378 channel->state == CH_STATE_DOWN));
1379 if (channel->state == CH_STATE_DOWN)
1380 ret = -EIO;
1381 else
1382 channel->state = CH_STATE_DOWN;
1383 if (ret) {
1384 kfree(rcd_buf);
1385 *buffer = NULL;
1386 *length = 0;
1387 } else {
1388 *length = ciw->count;
1389 *buffer = rcd_buf;
1390 }
1391 return ret;
1392 }
1393
qeth_get_unitaddr(struct qeth_card * card)1394 static int qeth_get_unitaddr(struct qeth_card *card)
1395 {
1396 int length;
1397 char *prcd;
1398 int rc;
1399
1400 QETH_DBF_TEXT(SETUP, 2, "getunit");
1401 rc = qeth_read_conf_data(card, (void **) &prcd, &length);
1402 if (rc) {
1403 QETH_DBF_MESSAGE(2, "%s qeth_read_conf_data returned %i\n",
1404 dev_name(&card->gdev->dev), rc);
1405 return rc;
1406 }
1407 card->info.chpid = prcd[30];
1408 card->info.unit_addr2 = prcd[31];
1409 card->info.cula = prcd[63];
1410 card->info.guestlan = ((prcd[0x10] == _ascebc['V']) &&
1411 (prcd[0x11] == _ascebc['M']));
1412 kfree(prcd);
1413 return 0;
1414 }
1415
qeth_init_tokens(struct qeth_card * card)1416 static void qeth_init_tokens(struct qeth_card *card)
1417 {
1418 card->token.issuer_rm_w = 0x00010103UL;
1419 card->token.cm_filter_w = 0x00010108UL;
1420 card->token.cm_connection_w = 0x0001010aUL;
1421 card->token.ulp_filter_w = 0x0001010bUL;
1422 card->token.ulp_connection_w = 0x0001010dUL;
1423 }
1424
qeth_init_func_level(struct qeth_card * card)1425 static void qeth_init_func_level(struct qeth_card *card)
1426 {
1427 if (card->ipato.enabled) {
1428 if (card->info.type == QETH_CARD_TYPE_IQD)
1429 card->info.func_level =
1430 QETH_IDX_FUNC_LEVEL_IQD_ENA_IPAT;
1431 else
1432 card->info.func_level =
1433 QETH_IDX_FUNC_LEVEL_OSAE_ENA_IPAT;
1434 } else {
1435 if (card->info.type == QETH_CARD_TYPE_IQD)
1436 /*FIXME:why do we have same values for dis and ena for
1437 osae??? */
1438 card->info.func_level =
1439 QETH_IDX_FUNC_LEVEL_IQD_DIS_IPAT;
1440 else
1441 card->info.func_level =
1442 QETH_IDX_FUNC_LEVEL_OSAE_DIS_IPAT;
1443 }
1444 }
1445
qeth_idx_activate_get_answer(struct qeth_channel * channel,void (* idx_reply_cb)(struct qeth_channel *,struct qeth_cmd_buffer *))1446 static int qeth_idx_activate_get_answer(struct qeth_channel *channel,
1447 void (*idx_reply_cb)(struct qeth_channel *,
1448 struct qeth_cmd_buffer *))
1449 {
1450 struct qeth_cmd_buffer *iob;
1451 unsigned long flags;
1452 int rc;
1453 struct qeth_card *card;
1454
1455 QETH_DBF_TEXT(SETUP, 2, "idxanswr");
1456 card = CARD_FROM_CDEV(channel->ccwdev);
1457 iob = qeth_get_buffer(channel);
1458 iob->callback = idx_reply_cb;
1459 memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
1460 channel->ccw.count = QETH_BUFSIZE;
1461 channel->ccw.cda = (__u32) __pa(iob->data);
1462
1463 wait_event(card->wait_q,
1464 atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
1465 QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
1466 spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
1467 rc = ccw_device_start(channel->ccwdev,
1468 &channel->ccw, (addr_t) iob, 0, 0);
1469 spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
1470
1471 if (rc) {
1472 QETH_DBF_MESSAGE(2, "Error2 in activating channel rc=%d\n", rc);
1473 QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
1474 atomic_set(&channel->irq_pending, 0);
1475 wake_up(&card->wait_q);
1476 return rc;
1477 }
1478 rc = wait_event_interruptible_timeout(card->wait_q,
1479 channel->state == CH_STATE_UP, QETH_TIMEOUT);
1480 if (rc == -ERESTARTSYS)
1481 return rc;
1482 if (channel->state != CH_STATE_UP) {
1483 rc = -ETIME;
1484 QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
1485 qeth_clear_cmd_buffers(channel);
1486 } else
1487 rc = 0;
1488 return rc;
1489 }
1490
qeth_idx_activate_channel(struct qeth_channel * channel,void (* idx_reply_cb)(struct qeth_channel *,struct qeth_cmd_buffer *))1491 static int qeth_idx_activate_channel(struct qeth_channel *channel,
1492 void (*idx_reply_cb)(struct qeth_channel *,
1493 struct qeth_cmd_buffer *))
1494 {
1495 struct qeth_card *card;
1496 struct qeth_cmd_buffer *iob;
1497 unsigned long flags;
1498 __u16 temp;
1499 __u8 tmp;
1500 int rc;
1501 struct ccw_dev_id temp_devid;
1502
1503 card = CARD_FROM_CDEV(channel->ccwdev);
1504
1505 QETH_DBF_TEXT(SETUP, 2, "idxactch");
1506
1507 iob = qeth_get_buffer(channel);
1508 iob->callback = idx_reply_cb;
1509 memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
1510 channel->ccw.count = IDX_ACTIVATE_SIZE;
1511 channel->ccw.cda = (__u32) __pa(iob->data);
1512 if (channel == &card->write) {
1513 memcpy(iob->data, IDX_ACTIVATE_WRITE, IDX_ACTIVATE_SIZE);
1514 memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
1515 &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
1516 card->seqno.trans_hdr++;
1517 } else {
1518 memcpy(iob->data, IDX_ACTIVATE_READ, IDX_ACTIVATE_SIZE);
1519 memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
1520 &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
1521 }
1522 tmp = ((__u8)card->info.portno) | 0x80;
1523 memcpy(QETH_IDX_ACT_PNO(iob->data), &tmp, 1);
1524 memcpy(QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
1525 &card->token.issuer_rm_w, QETH_MPC_TOKEN_LENGTH);
1526 memcpy(QETH_IDX_ACT_FUNC_LEVEL(iob->data),
1527 &card->info.func_level, sizeof(__u16));
1528 ccw_device_get_id(CARD_DDEV(card), &temp_devid);
1529 memcpy(QETH_IDX_ACT_QDIO_DEV_CUA(iob->data), &temp_devid.devno, 2);
1530 temp = (card->info.cula << 8) + card->info.unit_addr2;
1531 memcpy(QETH_IDX_ACT_QDIO_DEV_REALADDR(iob->data), &temp, 2);
1532
1533 wait_event(card->wait_q,
1534 atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
1535 QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
1536 spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
1537 rc = ccw_device_start(channel->ccwdev,
1538 &channel->ccw, (addr_t) iob, 0, 0);
1539 spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
1540
1541 if (rc) {
1542 QETH_DBF_MESSAGE(2, "Error1 in activating channel. rc=%d\n",
1543 rc);
1544 QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
1545 atomic_set(&channel->irq_pending, 0);
1546 wake_up(&card->wait_q);
1547 return rc;
1548 }
1549 rc = wait_event_interruptible_timeout(card->wait_q,
1550 channel->state == CH_STATE_ACTIVATING, QETH_TIMEOUT);
1551 if (rc == -ERESTARTSYS)
1552 return rc;
1553 if (channel->state != CH_STATE_ACTIVATING) {
1554 dev_warn(&channel->ccwdev->dev, "The qeth device driver"
1555 " failed to recover an error on the device\n");
1556 QETH_DBF_MESSAGE(2, "%s IDX activate timed out\n",
1557 dev_name(&channel->ccwdev->dev));
1558 QETH_DBF_TEXT_(SETUP, 2, "2err%d", -ETIME);
1559 qeth_clear_cmd_buffers(channel);
1560 return -ETIME;
1561 }
1562 return qeth_idx_activate_get_answer(channel, idx_reply_cb);
1563 }
1564
qeth_peer_func_level(int level)1565 static int qeth_peer_func_level(int level)
1566 {
1567 if ((level & 0xff) == 8)
1568 return (level & 0xff) + 0x400;
1569 if (((level >> 8) & 3) == 1)
1570 return (level & 0xff) + 0x200;
1571 return level;
1572 }
1573
qeth_idx_write_cb(struct qeth_channel * channel,struct qeth_cmd_buffer * iob)1574 static void qeth_idx_write_cb(struct qeth_channel *channel,
1575 struct qeth_cmd_buffer *iob)
1576 {
1577 struct qeth_card *card;
1578 __u16 temp;
1579
1580 QETH_DBF_TEXT(SETUP , 2, "idxwrcb");
1581
1582 if (channel->state == CH_STATE_DOWN) {
1583 channel->state = CH_STATE_ACTIVATING;
1584 goto out;
1585 }
1586 card = CARD_FROM_CDEV(channel->ccwdev);
1587
1588 if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
1589 if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == 0x19)
1590 dev_err(&card->write.ccwdev->dev,
1591 "The adapter is used exclusively by another "
1592 "host\n");
1593 else
1594 QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel:"
1595 " negative reply\n",
1596 dev_name(&card->write.ccwdev->dev));
1597 goto out;
1598 }
1599 memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
1600 if ((temp & ~0x0100) != qeth_peer_func_level(card->info.func_level)) {
1601 QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel: "
1602 "function level mismatch (sent: 0x%x, received: "
1603 "0x%x)\n", dev_name(&card->write.ccwdev->dev),
1604 card->info.func_level, temp);
1605 goto out;
1606 }
1607 channel->state = CH_STATE_UP;
1608 out:
1609 qeth_release_buffer(channel, iob);
1610 }
1611
qeth_idx_read_cb(struct qeth_channel * channel,struct qeth_cmd_buffer * iob)1612 static void qeth_idx_read_cb(struct qeth_channel *channel,
1613 struct qeth_cmd_buffer *iob)
1614 {
1615 struct qeth_card *card;
1616 __u16 temp;
1617
1618 QETH_DBF_TEXT(SETUP , 2, "idxrdcb");
1619 if (channel->state == CH_STATE_DOWN) {
1620 channel->state = CH_STATE_ACTIVATING;
1621 goto out;
1622 }
1623
1624 card = CARD_FROM_CDEV(channel->ccwdev);
1625 if (qeth_check_idx_response(iob->data))
1626 goto out;
1627
1628 if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
1629 if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == 0x19)
1630 dev_err(&card->write.ccwdev->dev,
1631 "The adapter is used exclusively by another "
1632 "host\n");
1633 else
1634 QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel:"
1635 " negative reply\n",
1636 dev_name(&card->read.ccwdev->dev));
1637 goto out;
1638 }
1639
1640 /**
1641 * temporary fix for microcode bug
1642 * to revert it,replace OR by AND
1643 */
1644 if ((!QETH_IDX_NO_PORTNAME_REQUIRED(iob->data)) ||
1645 (card->info.type == QETH_CARD_TYPE_OSAE))
1646 card->info.portname_required = 1;
1647
1648 memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
1649 if (temp != qeth_peer_func_level(card->info.func_level)) {
1650 QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel: function "
1651 "level mismatch (sent: 0x%x, received: 0x%x)\n",
1652 dev_name(&card->read.ccwdev->dev),
1653 card->info.func_level, temp);
1654 goto out;
1655 }
1656 memcpy(&card->token.issuer_rm_r,
1657 QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
1658 QETH_MPC_TOKEN_LENGTH);
1659 memcpy(&card->info.mcl_level[0],
1660 QETH_IDX_REPLY_LEVEL(iob->data), QETH_MCL_LENGTH);
1661 channel->state = CH_STATE_UP;
1662 out:
1663 qeth_release_buffer(channel, iob);
1664 }
1665
qeth_prepare_control_data(struct qeth_card * card,int len,struct qeth_cmd_buffer * iob)1666 void qeth_prepare_control_data(struct qeth_card *card, int len,
1667 struct qeth_cmd_buffer *iob)
1668 {
1669 qeth_setup_ccw(&card->write, iob->data, len);
1670 iob->callback = qeth_release_buffer;
1671
1672 memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
1673 &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
1674 card->seqno.trans_hdr++;
1675 memcpy(QETH_PDU_HEADER_SEQ_NO(iob->data),
1676 &card->seqno.pdu_hdr, QETH_SEQ_NO_LENGTH);
1677 card->seqno.pdu_hdr++;
1678 memcpy(QETH_PDU_HEADER_ACK_SEQ_NO(iob->data),
1679 &card->seqno.pdu_hdr_ack, QETH_SEQ_NO_LENGTH);
1680 QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
1681 }
1682 EXPORT_SYMBOL_GPL(qeth_prepare_control_data);
1683
qeth_send_control_data(struct qeth_card * card,int len,struct qeth_cmd_buffer * iob,int (* reply_cb)(struct qeth_card *,struct qeth_reply *,unsigned long),void * reply_param)1684 int qeth_send_control_data(struct qeth_card *card, int len,
1685 struct qeth_cmd_buffer *iob,
1686 int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
1687 unsigned long),
1688 void *reply_param)
1689 {
1690 int rc;
1691 unsigned long flags;
1692 struct qeth_reply *reply = NULL;
1693 unsigned long timeout;
1694 struct qeth_ipa_cmd *cmd;
1695
1696 QETH_DBF_TEXT(TRACE, 2, "sendctl");
1697
1698 reply = qeth_alloc_reply(card);
1699 if (!reply) {
1700 return -ENOMEM;
1701 }
1702 reply->callback = reply_cb;
1703 reply->param = reply_param;
1704 if (card->state == CARD_STATE_DOWN)
1705 reply->seqno = QETH_IDX_COMMAND_SEQNO;
1706 else
1707 reply->seqno = card->seqno.ipa++;
1708 init_waitqueue_head(&reply->wait_q);
1709 spin_lock_irqsave(&card->lock, flags);
1710 list_add_tail(&reply->list, &card->cmd_waiter_list);
1711 spin_unlock_irqrestore(&card->lock, flags);
1712 QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
1713
1714 while (atomic_cmpxchg(&card->write.irq_pending, 0, 1)) ;
1715 qeth_prepare_control_data(card, len, iob);
1716
1717 if (IS_IPA(iob->data))
1718 timeout = jiffies + QETH_IPA_TIMEOUT;
1719 else
1720 timeout = jiffies + QETH_TIMEOUT;
1721
1722 QETH_DBF_TEXT(TRACE, 6, "noirqpnd");
1723 spin_lock_irqsave(get_ccwdev_lock(card->write.ccwdev), flags);
1724 rc = ccw_device_start(card->write.ccwdev, &card->write.ccw,
1725 (addr_t) iob, 0, 0);
1726 spin_unlock_irqrestore(get_ccwdev_lock(card->write.ccwdev), flags);
1727 if (rc) {
1728 QETH_DBF_MESSAGE(2, "%s qeth_send_control_data: "
1729 "ccw_device_start rc = %i\n",
1730 dev_name(&card->write.ccwdev->dev), rc);
1731 QETH_DBF_TEXT_(TRACE, 2, " err%d", rc);
1732 spin_lock_irqsave(&card->lock, flags);
1733 list_del_init(&reply->list);
1734 qeth_put_reply(reply);
1735 spin_unlock_irqrestore(&card->lock, flags);
1736 qeth_release_buffer(iob->channel, iob);
1737 atomic_set(&card->write.irq_pending, 0);
1738 wake_up(&card->wait_q);
1739 return rc;
1740 }
1741
1742 /* we have only one long running ipassist, since we can ensure
1743 process context of this command we can sleep */
1744 cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
1745 if ((cmd->hdr.command == IPA_CMD_SETIP) &&
1746 (cmd->hdr.prot_version == QETH_PROT_IPV4)) {
1747 if (!wait_event_timeout(reply->wait_q,
1748 atomic_read(&reply->received), timeout))
1749 goto time_err;
1750 } else {
1751 while (!atomic_read(&reply->received)) {
1752 if (time_after(jiffies, timeout))
1753 goto time_err;
1754 cpu_relax();
1755 };
1756 }
1757
1758 rc = reply->rc;
1759 qeth_put_reply(reply);
1760 return rc;
1761
1762 time_err:
1763 spin_lock_irqsave(&reply->card->lock, flags);
1764 list_del_init(&reply->list);
1765 spin_unlock_irqrestore(&reply->card->lock, flags);
1766 reply->rc = -ETIME;
1767 atomic_inc(&reply->received);
1768 wake_up(&reply->wait_q);
1769 rc = reply->rc;
1770 qeth_put_reply(reply);
1771 return rc;
1772 }
1773 EXPORT_SYMBOL_GPL(qeth_send_control_data);
1774
qeth_cm_enable_cb(struct qeth_card * card,struct qeth_reply * reply,unsigned long data)1775 static int qeth_cm_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
1776 unsigned long data)
1777 {
1778 struct qeth_cmd_buffer *iob;
1779
1780 QETH_DBF_TEXT(SETUP, 2, "cmenblcb");
1781
1782 iob = (struct qeth_cmd_buffer *) data;
1783 memcpy(&card->token.cm_filter_r,
1784 QETH_CM_ENABLE_RESP_FILTER_TOKEN(iob->data),
1785 QETH_MPC_TOKEN_LENGTH);
1786 QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
1787 return 0;
1788 }
1789
qeth_cm_enable(struct qeth_card * card)1790 static int qeth_cm_enable(struct qeth_card *card)
1791 {
1792 int rc;
1793 struct qeth_cmd_buffer *iob;
1794
1795 QETH_DBF_TEXT(SETUP, 2, "cmenable");
1796
1797 iob = qeth_wait_for_buffer(&card->write);
1798 memcpy(iob->data, CM_ENABLE, CM_ENABLE_SIZE);
1799 memcpy(QETH_CM_ENABLE_ISSUER_RM_TOKEN(iob->data),
1800 &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
1801 memcpy(QETH_CM_ENABLE_FILTER_TOKEN(iob->data),
1802 &card->token.cm_filter_w, QETH_MPC_TOKEN_LENGTH);
1803
1804 rc = qeth_send_control_data(card, CM_ENABLE_SIZE, iob,
1805 qeth_cm_enable_cb, NULL);
1806 return rc;
1807 }
1808
qeth_cm_setup_cb(struct qeth_card * card,struct qeth_reply * reply,unsigned long data)1809 static int qeth_cm_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
1810 unsigned long data)
1811 {
1812
1813 struct qeth_cmd_buffer *iob;
1814
1815 QETH_DBF_TEXT(SETUP, 2, "cmsetpcb");
1816
1817 iob = (struct qeth_cmd_buffer *) data;
1818 memcpy(&card->token.cm_connection_r,
1819 QETH_CM_SETUP_RESP_DEST_ADDR(iob->data),
1820 QETH_MPC_TOKEN_LENGTH);
1821 QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
1822 return 0;
1823 }
1824
qeth_cm_setup(struct qeth_card * card)1825 static int qeth_cm_setup(struct qeth_card *card)
1826 {
1827 int rc;
1828 struct qeth_cmd_buffer *iob;
1829
1830 QETH_DBF_TEXT(SETUP, 2, "cmsetup");
1831
1832 iob = qeth_wait_for_buffer(&card->write);
1833 memcpy(iob->data, CM_SETUP, CM_SETUP_SIZE);
1834 memcpy(QETH_CM_SETUP_DEST_ADDR(iob->data),
1835 &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
1836 memcpy(QETH_CM_SETUP_CONNECTION_TOKEN(iob->data),
1837 &card->token.cm_connection_w, QETH_MPC_TOKEN_LENGTH);
1838 memcpy(QETH_CM_SETUP_FILTER_TOKEN(iob->data),
1839 &card->token.cm_filter_r, QETH_MPC_TOKEN_LENGTH);
1840 rc = qeth_send_control_data(card, CM_SETUP_SIZE, iob,
1841 qeth_cm_setup_cb, NULL);
1842 return rc;
1843
1844 }
1845
qeth_get_initial_mtu_for_card(struct qeth_card * card)1846 static inline int qeth_get_initial_mtu_for_card(struct qeth_card *card)
1847 {
1848 switch (card->info.type) {
1849 case QETH_CARD_TYPE_UNKNOWN:
1850 return 1500;
1851 case QETH_CARD_TYPE_IQD:
1852 return card->info.max_mtu;
1853 case QETH_CARD_TYPE_OSAE:
1854 switch (card->info.link_type) {
1855 case QETH_LINK_TYPE_HSTR:
1856 case QETH_LINK_TYPE_LANE_TR:
1857 return 2000;
1858 default:
1859 return 1492;
1860 }
1861 default:
1862 return 1500;
1863 }
1864 }
1865
qeth_get_max_mtu_for_card(int cardtype)1866 static inline int qeth_get_max_mtu_for_card(int cardtype)
1867 {
1868 switch (cardtype) {
1869
1870 case QETH_CARD_TYPE_UNKNOWN:
1871 case QETH_CARD_TYPE_OSAE:
1872 case QETH_CARD_TYPE_OSN:
1873 return 61440;
1874 case QETH_CARD_TYPE_IQD:
1875 return 57344;
1876 default:
1877 return 1500;
1878 }
1879 }
1880
qeth_get_mtu_out_of_mpc(int cardtype)1881 static inline int qeth_get_mtu_out_of_mpc(int cardtype)
1882 {
1883 switch (cardtype) {
1884 case QETH_CARD_TYPE_IQD:
1885 return 1;
1886 default:
1887 return 0;
1888 }
1889 }
1890
qeth_get_mtu_outof_framesize(int framesize)1891 static inline int qeth_get_mtu_outof_framesize(int framesize)
1892 {
1893 switch (framesize) {
1894 case 0x4000:
1895 return 8192;
1896 case 0x6000:
1897 return 16384;
1898 case 0xa000:
1899 return 32768;
1900 case 0xffff:
1901 return 57344;
1902 default:
1903 return 0;
1904 }
1905 }
1906
qeth_mtu_is_valid(struct qeth_card * card,int mtu)1907 static inline int qeth_mtu_is_valid(struct qeth_card *card, int mtu)
1908 {
1909 switch (card->info.type) {
1910 case QETH_CARD_TYPE_OSAE:
1911 return ((mtu >= 576) && (mtu <= 61440));
1912 case QETH_CARD_TYPE_IQD:
1913 return ((mtu >= 576) &&
1914 (mtu <= card->info.max_mtu + 4096 - 32));
1915 case QETH_CARD_TYPE_OSN:
1916 case QETH_CARD_TYPE_UNKNOWN:
1917 default:
1918 return 1;
1919 }
1920 }
1921
qeth_ulp_enable_cb(struct qeth_card * card,struct qeth_reply * reply,unsigned long data)1922 static int qeth_ulp_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
1923 unsigned long data)
1924 {
1925
1926 __u16 mtu, framesize;
1927 __u16 len;
1928 __u8 link_type;
1929 struct qeth_cmd_buffer *iob;
1930
1931 QETH_DBF_TEXT(SETUP, 2, "ulpenacb");
1932
1933 iob = (struct qeth_cmd_buffer *) data;
1934 memcpy(&card->token.ulp_filter_r,
1935 QETH_ULP_ENABLE_RESP_FILTER_TOKEN(iob->data),
1936 QETH_MPC_TOKEN_LENGTH);
1937 if (qeth_get_mtu_out_of_mpc(card->info.type)) {
1938 memcpy(&framesize, QETH_ULP_ENABLE_RESP_MAX_MTU(iob->data), 2);
1939 mtu = qeth_get_mtu_outof_framesize(framesize);
1940 if (!mtu) {
1941 iob->rc = -EINVAL;
1942 QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
1943 return 0;
1944 }
1945 card->info.max_mtu = mtu;
1946 card->info.initial_mtu = mtu;
1947 card->qdio.in_buf_size = mtu + 2 * PAGE_SIZE;
1948 } else {
1949 card->info.initial_mtu = qeth_get_initial_mtu_for_card(card);
1950 card->info.max_mtu = qeth_get_max_mtu_for_card(card->info.type);
1951 card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
1952 }
1953
1954 memcpy(&len, QETH_ULP_ENABLE_RESP_DIFINFO_LEN(iob->data), 2);
1955 if (len >= QETH_MPC_DIFINFO_LEN_INDICATES_LINK_TYPE) {
1956 memcpy(&link_type,
1957 QETH_ULP_ENABLE_RESP_LINK_TYPE(iob->data), 1);
1958 card->info.link_type = link_type;
1959 } else
1960 card->info.link_type = 0;
1961 QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
1962 return 0;
1963 }
1964
qeth_ulp_enable(struct qeth_card * card)1965 static int qeth_ulp_enable(struct qeth_card *card)
1966 {
1967 int rc;
1968 char prot_type;
1969 struct qeth_cmd_buffer *iob;
1970
1971 /*FIXME: trace view callbacks*/
1972 QETH_DBF_TEXT(SETUP, 2, "ulpenabl");
1973
1974 iob = qeth_wait_for_buffer(&card->write);
1975 memcpy(iob->data, ULP_ENABLE, ULP_ENABLE_SIZE);
1976
1977 *(QETH_ULP_ENABLE_LINKNUM(iob->data)) =
1978 (__u8) card->info.portno;
1979 if (card->options.layer2)
1980 if (card->info.type == QETH_CARD_TYPE_OSN)
1981 prot_type = QETH_PROT_OSN2;
1982 else
1983 prot_type = QETH_PROT_LAYER2;
1984 else
1985 prot_type = QETH_PROT_TCPIP;
1986
1987 memcpy(QETH_ULP_ENABLE_PROT_TYPE(iob->data), &prot_type, 1);
1988 memcpy(QETH_ULP_ENABLE_DEST_ADDR(iob->data),
1989 &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
1990 memcpy(QETH_ULP_ENABLE_FILTER_TOKEN(iob->data),
1991 &card->token.ulp_filter_w, QETH_MPC_TOKEN_LENGTH);
1992 memcpy(QETH_ULP_ENABLE_PORTNAME_AND_LL(iob->data),
1993 card->info.portname, 9);
1994 rc = qeth_send_control_data(card, ULP_ENABLE_SIZE, iob,
1995 qeth_ulp_enable_cb, NULL);
1996 return rc;
1997
1998 }
1999
qeth_ulp_setup_cb(struct qeth_card * card,struct qeth_reply * reply,unsigned long data)2000 static int qeth_ulp_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
2001 unsigned long data)
2002 {
2003 struct qeth_cmd_buffer *iob;
2004
2005 QETH_DBF_TEXT(SETUP, 2, "ulpstpcb");
2006
2007 iob = (struct qeth_cmd_buffer *) data;
2008 memcpy(&card->token.ulp_connection_r,
2009 QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
2010 QETH_MPC_TOKEN_LENGTH);
2011 QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
2012 return 0;
2013 }
2014
qeth_ulp_setup(struct qeth_card * card)2015 static int qeth_ulp_setup(struct qeth_card *card)
2016 {
2017 int rc;
2018 __u16 temp;
2019 struct qeth_cmd_buffer *iob;
2020 struct ccw_dev_id dev_id;
2021
2022 QETH_DBF_TEXT(SETUP, 2, "ulpsetup");
2023
2024 iob = qeth_wait_for_buffer(&card->write);
2025 memcpy(iob->data, ULP_SETUP, ULP_SETUP_SIZE);
2026
2027 memcpy(QETH_ULP_SETUP_DEST_ADDR(iob->data),
2028 &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
2029 memcpy(QETH_ULP_SETUP_CONNECTION_TOKEN(iob->data),
2030 &card->token.ulp_connection_w, QETH_MPC_TOKEN_LENGTH);
2031 memcpy(QETH_ULP_SETUP_FILTER_TOKEN(iob->data),
2032 &card->token.ulp_filter_r, QETH_MPC_TOKEN_LENGTH);
2033
2034 ccw_device_get_id(CARD_DDEV(card), &dev_id);
2035 memcpy(QETH_ULP_SETUP_CUA(iob->data), &dev_id.devno, 2);
2036 temp = (card->info.cula << 8) + card->info.unit_addr2;
2037 memcpy(QETH_ULP_SETUP_REAL_DEVADDR(iob->data), &temp, 2);
2038 rc = qeth_send_control_data(card, ULP_SETUP_SIZE, iob,
2039 qeth_ulp_setup_cb, NULL);
2040 return rc;
2041 }
2042
qeth_alloc_qdio_buffers(struct qeth_card * card)2043 static int qeth_alloc_qdio_buffers(struct qeth_card *card)
2044 {
2045 int i, j;
2046
2047 QETH_DBF_TEXT(SETUP, 2, "allcqdbf");
2048
2049 if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED,
2050 QETH_QDIO_ALLOCATED) != QETH_QDIO_UNINITIALIZED)
2051 return 0;
2052
2053 card->qdio.in_q = kmalloc(sizeof(struct qeth_qdio_q),
2054 GFP_KERNEL);
2055 if (!card->qdio.in_q)
2056 goto out_nomem;
2057 QETH_DBF_TEXT(SETUP, 2, "inq");
2058 QETH_DBF_HEX(SETUP, 2, &card->qdio.in_q, sizeof(void *));
2059 memset(card->qdio.in_q, 0, sizeof(struct qeth_qdio_q));
2060 /* give inbound qeth_qdio_buffers their qdio_buffers */
2061 for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
2062 card->qdio.in_q->bufs[i].buffer =
2063 &card->qdio.in_q->qdio_bufs[i];
2064 /* inbound buffer pool */
2065 if (qeth_alloc_buffer_pool(card))
2066 goto out_freeinq;
2067 /* outbound */
2068 card->qdio.out_qs =
2069 kmalloc(card->qdio.no_out_queues *
2070 sizeof(struct qeth_qdio_out_q *), GFP_KERNEL);
2071 if (!card->qdio.out_qs)
2072 goto out_freepool;
2073 for (i = 0; i < card->qdio.no_out_queues; ++i) {
2074 card->qdio.out_qs[i] = kmalloc(sizeof(struct qeth_qdio_out_q),
2075 GFP_KERNEL);
2076 if (!card->qdio.out_qs[i])
2077 goto out_freeoutq;
2078 QETH_DBF_TEXT_(SETUP, 2, "outq %i", i);
2079 QETH_DBF_HEX(SETUP, 2, &card->qdio.out_qs[i], sizeof(void *));
2080 memset(card->qdio.out_qs[i], 0, sizeof(struct qeth_qdio_out_q));
2081 card->qdio.out_qs[i]->queue_no = i;
2082 /* give outbound qeth_qdio_buffers their qdio_buffers */
2083 for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
2084 card->qdio.out_qs[i]->bufs[j].buffer =
2085 &card->qdio.out_qs[i]->qdio_bufs[j];
2086 skb_queue_head_init(&card->qdio.out_qs[i]->bufs[j].
2087 skb_list);
2088 lockdep_set_class(
2089 &card->qdio.out_qs[i]->bufs[j].skb_list.lock,
2090 &qdio_out_skb_queue_key);
2091 INIT_LIST_HEAD(&card->qdio.out_qs[i]->bufs[j].ctx_list);
2092 }
2093 }
2094 return 0;
2095
2096 out_freeoutq:
2097 while (i > 0)
2098 kfree(card->qdio.out_qs[--i]);
2099 kfree(card->qdio.out_qs);
2100 card->qdio.out_qs = NULL;
2101 out_freepool:
2102 qeth_free_buffer_pool(card);
2103 out_freeinq:
2104 kfree(card->qdio.in_q);
2105 card->qdio.in_q = NULL;
2106 out_nomem:
2107 atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
2108 return -ENOMEM;
2109 }
2110
qeth_create_qib_param_field(struct qeth_card * card,char * param_field)2111 static void qeth_create_qib_param_field(struct qeth_card *card,
2112 char *param_field)
2113 {
2114
2115 param_field[0] = _ascebc['P'];
2116 param_field[1] = _ascebc['C'];
2117 param_field[2] = _ascebc['I'];
2118 param_field[3] = _ascebc['T'];
2119 *((unsigned int *) (¶m_field[4])) = QETH_PCI_THRESHOLD_A(card);
2120 *((unsigned int *) (¶m_field[8])) = QETH_PCI_THRESHOLD_B(card);
2121 *((unsigned int *) (¶m_field[12])) = QETH_PCI_TIMER_VALUE(card);
2122 }
2123
qeth_create_qib_param_field_blkt(struct qeth_card * card,char * param_field)2124 static void qeth_create_qib_param_field_blkt(struct qeth_card *card,
2125 char *param_field)
2126 {
2127 param_field[16] = _ascebc['B'];
2128 param_field[17] = _ascebc['L'];
2129 param_field[18] = _ascebc['K'];
2130 param_field[19] = _ascebc['T'];
2131 *((unsigned int *) (¶m_field[20])) = card->info.blkt.time_total;
2132 *((unsigned int *) (¶m_field[24])) = card->info.blkt.inter_packet;
2133 *((unsigned int *) (¶m_field[28])) =
2134 card->info.blkt.inter_packet_jumbo;
2135 }
2136
qeth_qdio_activate(struct qeth_card * card)2137 static int qeth_qdio_activate(struct qeth_card *card)
2138 {
2139 QETH_DBF_TEXT(SETUP, 3, "qdioact");
2140 return qdio_activate(CARD_DDEV(card));
2141 }
2142
qeth_dm_act(struct qeth_card * card)2143 static int qeth_dm_act(struct qeth_card *card)
2144 {
2145 int rc;
2146 struct qeth_cmd_buffer *iob;
2147
2148 QETH_DBF_TEXT(SETUP, 2, "dmact");
2149
2150 iob = qeth_wait_for_buffer(&card->write);
2151 memcpy(iob->data, DM_ACT, DM_ACT_SIZE);
2152
2153 memcpy(QETH_DM_ACT_DEST_ADDR(iob->data),
2154 &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
2155 memcpy(QETH_DM_ACT_CONNECTION_TOKEN(iob->data),
2156 &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
2157 rc = qeth_send_control_data(card, DM_ACT_SIZE, iob, NULL, NULL);
2158 return rc;
2159 }
2160
qeth_mpc_initialize(struct qeth_card * card)2161 static int qeth_mpc_initialize(struct qeth_card *card)
2162 {
2163 int rc;
2164
2165 QETH_DBF_TEXT(SETUP, 2, "mpcinit");
2166
2167 rc = qeth_issue_next_read(card);
2168 if (rc) {
2169 QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
2170 return rc;
2171 }
2172 rc = qeth_cm_enable(card);
2173 if (rc) {
2174 QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
2175 goto out_qdio;
2176 }
2177 rc = qeth_cm_setup(card);
2178 if (rc) {
2179 QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
2180 goto out_qdio;
2181 }
2182 rc = qeth_ulp_enable(card);
2183 if (rc) {
2184 QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
2185 goto out_qdio;
2186 }
2187 rc = qeth_ulp_setup(card);
2188 if (rc) {
2189 QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
2190 goto out_qdio;
2191 }
2192 rc = qeth_alloc_qdio_buffers(card);
2193 if (rc) {
2194 QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
2195 goto out_qdio;
2196 }
2197 rc = qeth_qdio_establish(card);
2198 if (rc) {
2199 QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
2200 qeth_free_qdio_buffers(card);
2201 goto out_qdio;
2202 }
2203 rc = qeth_qdio_activate(card);
2204 if (rc) {
2205 QETH_DBF_TEXT_(SETUP, 2, "7err%d", rc);
2206 goto out_qdio;
2207 }
2208 rc = qeth_dm_act(card);
2209 if (rc) {
2210 QETH_DBF_TEXT_(SETUP, 2, "8err%d", rc);
2211 goto out_qdio;
2212 }
2213
2214 return 0;
2215 out_qdio:
2216 qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
2217 return rc;
2218 }
2219
qeth_print_status_with_portname(struct qeth_card * card)2220 static void qeth_print_status_with_portname(struct qeth_card *card)
2221 {
2222 char dbf_text[15];
2223 int i;
2224
2225 sprintf(dbf_text, "%s", card->info.portname + 1);
2226 for (i = 0; i < 8; i++)
2227 dbf_text[i] =
2228 (char) _ebcasc[(__u8) dbf_text[i]];
2229 dbf_text[8] = 0;
2230 dev_info(&card->gdev->dev, "Device is a%s card%s%s%s\n"
2231 "with link type %s (portname: %s)\n",
2232 qeth_get_cardname(card),
2233 (card->info.mcl_level[0]) ? " (level: " : "",
2234 (card->info.mcl_level[0]) ? card->info.mcl_level : "",
2235 (card->info.mcl_level[0]) ? ")" : "",
2236 qeth_get_cardname_short(card),
2237 dbf_text);
2238
2239 }
2240
qeth_print_status_no_portname(struct qeth_card * card)2241 static void qeth_print_status_no_portname(struct qeth_card *card)
2242 {
2243 if (card->info.portname[0])
2244 dev_info(&card->gdev->dev, "Device is a%s "
2245 "card%s%s%s\nwith link type %s "
2246 "(no portname needed by interface).\n",
2247 qeth_get_cardname(card),
2248 (card->info.mcl_level[0]) ? " (level: " : "",
2249 (card->info.mcl_level[0]) ? card->info.mcl_level : "",
2250 (card->info.mcl_level[0]) ? ")" : "",
2251 qeth_get_cardname_short(card));
2252 else
2253 dev_info(&card->gdev->dev, "Device is a%s "
2254 "card%s%s%s\nwith link type %s.\n",
2255 qeth_get_cardname(card),
2256 (card->info.mcl_level[0]) ? " (level: " : "",
2257 (card->info.mcl_level[0]) ? card->info.mcl_level : "",
2258 (card->info.mcl_level[0]) ? ")" : "",
2259 qeth_get_cardname_short(card));
2260 }
2261
qeth_print_status_message(struct qeth_card * card)2262 void qeth_print_status_message(struct qeth_card *card)
2263 {
2264 switch (card->info.type) {
2265 case QETH_CARD_TYPE_OSAE:
2266 /* VM will use a non-zero first character
2267 * to indicate a HiperSockets like reporting
2268 * of the level OSA sets the first character to zero
2269 * */
2270 if (!card->info.mcl_level[0]) {
2271 sprintf(card->info.mcl_level, "%02x%02x",
2272 card->info.mcl_level[2],
2273 card->info.mcl_level[3]);
2274
2275 card->info.mcl_level[QETH_MCL_LENGTH] = 0;
2276 break;
2277 }
2278 /* fallthrough */
2279 case QETH_CARD_TYPE_IQD:
2280 if ((card->info.guestlan) ||
2281 (card->info.mcl_level[0] & 0x80)) {
2282 card->info.mcl_level[0] = (char) _ebcasc[(__u8)
2283 card->info.mcl_level[0]];
2284 card->info.mcl_level[1] = (char) _ebcasc[(__u8)
2285 card->info.mcl_level[1]];
2286 card->info.mcl_level[2] = (char) _ebcasc[(__u8)
2287 card->info.mcl_level[2]];
2288 card->info.mcl_level[3] = (char) _ebcasc[(__u8)
2289 card->info.mcl_level[3]];
2290 card->info.mcl_level[QETH_MCL_LENGTH] = 0;
2291 }
2292 break;
2293 default:
2294 memset(&card->info.mcl_level[0], 0, QETH_MCL_LENGTH + 1);
2295 }
2296 if (card->info.portname_required)
2297 qeth_print_status_with_portname(card);
2298 else
2299 qeth_print_status_no_portname(card);
2300 }
2301 EXPORT_SYMBOL_GPL(qeth_print_status_message);
2302
qeth_initialize_working_pool_list(struct qeth_card * card)2303 static void qeth_initialize_working_pool_list(struct qeth_card *card)
2304 {
2305 struct qeth_buffer_pool_entry *entry;
2306
2307 QETH_DBF_TEXT(TRACE, 5, "inwrklst");
2308
2309 list_for_each_entry(entry,
2310 &card->qdio.init_pool.entry_list, init_list) {
2311 qeth_put_buffer_pool_entry(card, entry);
2312 }
2313 }
2314
qeth_find_free_buffer_pool_entry(struct qeth_card * card)2315 static inline struct qeth_buffer_pool_entry *qeth_find_free_buffer_pool_entry(
2316 struct qeth_card *card)
2317 {
2318 struct list_head *plh;
2319 struct qeth_buffer_pool_entry *entry;
2320 int i, free;
2321 struct page *page;
2322
2323 if (list_empty(&card->qdio.in_buf_pool.entry_list))
2324 return NULL;
2325
2326 list_for_each(plh, &card->qdio.in_buf_pool.entry_list) {
2327 entry = list_entry(plh, struct qeth_buffer_pool_entry, list);
2328 free = 1;
2329 for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
2330 if (page_count(virt_to_page(entry->elements[i])) > 1) {
2331 free = 0;
2332 break;
2333 }
2334 }
2335 if (free) {
2336 list_del_init(&entry->list);
2337 return entry;
2338 }
2339 }
2340
2341 /* no free buffer in pool so take first one and swap pages */
2342 entry = list_entry(card->qdio.in_buf_pool.entry_list.next,
2343 struct qeth_buffer_pool_entry, list);
2344 for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
2345 if (page_count(virt_to_page(entry->elements[i])) > 1) {
2346 page = alloc_page(GFP_ATOMIC);
2347 if (!page) {
2348 return NULL;
2349 } else {
2350 free_page((unsigned long)entry->elements[i]);
2351 entry->elements[i] = page_address(page);
2352 if (card->options.performance_stats)
2353 card->perf_stats.sg_alloc_page_rx++;
2354 }
2355 }
2356 }
2357 list_del_init(&entry->list);
2358 return entry;
2359 }
2360
qeth_init_input_buffer(struct qeth_card * card,struct qeth_qdio_buffer * buf)2361 static int qeth_init_input_buffer(struct qeth_card *card,
2362 struct qeth_qdio_buffer *buf)
2363 {
2364 struct qeth_buffer_pool_entry *pool_entry;
2365 int i;
2366
2367 pool_entry = qeth_find_free_buffer_pool_entry(card);
2368 if (!pool_entry)
2369 return 1;
2370
2371 /*
2372 * since the buffer is accessed only from the input_tasklet
2373 * there shouldn't be a need to synchronize; also, since we use
2374 * the QETH_IN_BUF_REQUEUE_THRESHOLD we should never run out off
2375 * buffers
2376 */
2377
2378 buf->pool_entry = pool_entry;
2379 for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
2380 buf->buffer->element[i].length = PAGE_SIZE;
2381 buf->buffer->element[i].addr = pool_entry->elements[i];
2382 if (i == QETH_MAX_BUFFER_ELEMENTS(card) - 1)
2383 buf->buffer->element[i].flags = SBAL_FLAGS_LAST_ENTRY;
2384 else
2385 buf->buffer->element[i].flags = 0;
2386 }
2387 return 0;
2388 }
2389
qeth_init_qdio_queues(struct qeth_card * card)2390 int qeth_init_qdio_queues(struct qeth_card *card)
2391 {
2392 int i, j;
2393 int rc;
2394
2395 QETH_DBF_TEXT(SETUP, 2, "initqdqs");
2396
2397 /* inbound queue */
2398 memset(card->qdio.in_q->qdio_bufs, 0,
2399 QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
2400 qeth_initialize_working_pool_list(card);
2401 /*give only as many buffers to hardware as we have buffer pool entries*/
2402 for (i = 0; i < card->qdio.in_buf_pool.buf_count - 1; ++i)
2403 qeth_init_input_buffer(card, &card->qdio.in_q->bufs[i]);
2404 card->qdio.in_q->next_buf_to_init =
2405 card->qdio.in_buf_pool.buf_count - 1;
2406 rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0, 0,
2407 card->qdio.in_buf_pool.buf_count - 1);
2408 if (rc) {
2409 QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
2410 return rc;
2411 }
2412 /* outbound queue */
2413 for (i = 0; i < card->qdio.no_out_queues; ++i) {
2414 memset(card->qdio.out_qs[i]->qdio_bufs, 0,
2415 QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
2416 for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
2417 qeth_clear_output_buffer(card->qdio.out_qs[i],
2418 &card->qdio.out_qs[i]->bufs[j]);
2419 }
2420 card->qdio.out_qs[i]->card = card;
2421 card->qdio.out_qs[i]->next_buf_to_fill = 0;
2422 card->qdio.out_qs[i]->do_pack = 0;
2423 atomic_set(&card->qdio.out_qs[i]->used_buffers, 0);
2424 atomic_set(&card->qdio.out_qs[i]->set_pci_flags_count, 0);
2425 atomic_set(&card->qdio.out_qs[i]->state,
2426 QETH_OUT_Q_UNLOCKED);
2427 }
2428 return 0;
2429 }
2430 EXPORT_SYMBOL_GPL(qeth_init_qdio_queues);
2431
qeth_get_ipa_adp_type(enum qeth_link_types link_type)2432 static inline __u8 qeth_get_ipa_adp_type(enum qeth_link_types link_type)
2433 {
2434 switch (link_type) {
2435 case QETH_LINK_TYPE_HSTR:
2436 return 2;
2437 default:
2438 return 1;
2439 }
2440 }
2441
qeth_fill_ipacmd_header(struct qeth_card * card,struct qeth_ipa_cmd * cmd,__u8 command,enum qeth_prot_versions prot)2442 static void qeth_fill_ipacmd_header(struct qeth_card *card,
2443 struct qeth_ipa_cmd *cmd, __u8 command,
2444 enum qeth_prot_versions prot)
2445 {
2446 memset(cmd, 0, sizeof(struct qeth_ipa_cmd));
2447 cmd->hdr.command = command;
2448 cmd->hdr.initiator = IPA_CMD_INITIATOR_HOST;
2449 cmd->hdr.seqno = card->seqno.ipa;
2450 cmd->hdr.adapter_type = qeth_get_ipa_adp_type(card->info.link_type);
2451 cmd->hdr.rel_adapter_no = (__u8) card->info.portno;
2452 if (card->options.layer2)
2453 cmd->hdr.prim_version_no = 2;
2454 else
2455 cmd->hdr.prim_version_no = 1;
2456 cmd->hdr.param_count = 1;
2457 cmd->hdr.prot_version = prot;
2458 cmd->hdr.ipa_supported = 0;
2459 cmd->hdr.ipa_enabled = 0;
2460 }
2461
qeth_get_ipacmd_buffer(struct qeth_card * card,enum qeth_ipa_cmds ipacmd,enum qeth_prot_versions prot)2462 struct qeth_cmd_buffer *qeth_get_ipacmd_buffer(struct qeth_card *card,
2463 enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
2464 {
2465 struct qeth_cmd_buffer *iob;
2466 struct qeth_ipa_cmd *cmd;
2467
2468 iob = qeth_wait_for_buffer(&card->write);
2469 cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
2470 qeth_fill_ipacmd_header(card, cmd, ipacmd, prot);
2471
2472 return iob;
2473 }
2474 EXPORT_SYMBOL_GPL(qeth_get_ipacmd_buffer);
2475
qeth_prepare_ipa_cmd(struct qeth_card * card,struct qeth_cmd_buffer * iob,char prot_type)2476 void qeth_prepare_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
2477 char prot_type)
2478 {
2479 memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
2480 memcpy(QETH_IPA_CMD_PROT_TYPE(iob->data), &prot_type, 1);
2481 memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
2482 &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
2483 }
2484 EXPORT_SYMBOL_GPL(qeth_prepare_ipa_cmd);
2485
qeth_send_ipa_cmd(struct qeth_card * card,struct qeth_cmd_buffer * iob,int (* reply_cb)(struct qeth_card *,struct qeth_reply *,unsigned long),void * reply_param)2486 int qeth_send_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
2487 int (*reply_cb)(struct qeth_card *, struct qeth_reply*,
2488 unsigned long),
2489 void *reply_param)
2490 {
2491 int rc;
2492 char prot_type;
2493
2494 QETH_DBF_TEXT(TRACE, 4, "sendipa");
2495
2496 if (card->options.layer2)
2497 if (card->info.type == QETH_CARD_TYPE_OSN)
2498 prot_type = QETH_PROT_OSN2;
2499 else
2500 prot_type = QETH_PROT_LAYER2;
2501 else
2502 prot_type = QETH_PROT_TCPIP;
2503 qeth_prepare_ipa_cmd(card, iob, prot_type);
2504 rc = qeth_send_control_data(card, IPA_CMD_LENGTH,
2505 iob, reply_cb, reply_param);
2506 return rc;
2507 }
2508 EXPORT_SYMBOL_GPL(qeth_send_ipa_cmd);
2509
qeth_send_startstoplan(struct qeth_card * card,enum qeth_ipa_cmds ipacmd,enum qeth_prot_versions prot)2510 static int qeth_send_startstoplan(struct qeth_card *card,
2511 enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
2512 {
2513 int rc;
2514 struct qeth_cmd_buffer *iob;
2515
2516 iob = qeth_get_ipacmd_buffer(card, ipacmd, prot);
2517 rc = qeth_send_ipa_cmd(card, iob, NULL, NULL);
2518
2519 return rc;
2520 }
2521
qeth_send_startlan(struct qeth_card * card)2522 int qeth_send_startlan(struct qeth_card *card)
2523 {
2524 int rc;
2525
2526 QETH_DBF_TEXT(SETUP, 2, "strtlan");
2527
2528 rc = qeth_send_startstoplan(card, IPA_CMD_STARTLAN, 0);
2529 return rc;
2530 }
2531 EXPORT_SYMBOL_GPL(qeth_send_startlan);
2532
qeth_send_stoplan(struct qeth_card * card)2533 int qeth_send_stoplan(struct qeth_card *card)
2534 {
2535 int rc = 0;
2536
2537 /*
2538 * TODO: according to the IPA format document page 14,
2539 * TCP/IP (we!) never issue a STOPLAN
2540 * is this right ?!?
2541 */
2542 QETH_DBF_TEXT(SETUP, 2, "stoplan");
2543
2544 rc = qeth_send_startstoplan(card, IPA_CMD_STOPLAN, 0);
2545 return rc;
2546 }
2547 EXPORT_SYMBOL_GPL(qeth_send_stoplan);
2548
qeth_default_setadapterparms_cb(struct qeth_card * card,struct qeth_reply * reply,unsigned long data)2549 int qeth_default_setadapterparms_cb(struct qeth_card *card,
2550 struct qeth_reply *reply, unsigned long data)
2551 {
2552 struct qeth_ipa_cmd *cmd;
2553
2554 QETH_DBF_TEXT(TRACE, 4, "defadpcb");
2555
2556 cmd = (struct qeth_ipa_cmd *) data;
2557 if (cmd->hdr.return_code == 0)
2558 cmd->hdr.return_code =
2559 cmd->data.setadapterparms.hdr.return_code;
2560 return 0;
2561 }
2562 EXPORT_SYMBOL_GPL(qeth_default_setadapterparms_cb);
2563
qeth_query_setadapterparms_cb(struct qeth_card * card,struct qeth_reply * reply,unsigned long data)2564 static int qeth_query_setadapterparms_cb(struct qeth_card *card,
2565 struct qeth_reply *reply, unsigned long data)
2566 {
2567 struct qeth_ipa_cmd *cmd;
2568
2569 QETH_DBF_TEXT(TRACE, 3, "quyadpcb");
2570
2571 cmd = (struct qeth_ipa_cmd *) data;
2572 if (cmd->data.setadapterparms.data.query_cmds_supp.lan_type & 0x7f)
2573 card->info.link_type =
2574 cmd->data.setadapterparms.data.query_cmds_supp.lan_type;
2575 card->options.adp.supported_funcs =
2576 cmd->data.setadapterparms.data.query_cmds_supp.supported_cmds;
2577 return qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
2578 }
2579
qeth_get_adapter_cmd(struct qeth_card * card,__u32 command,__u32 cmdlen)2580 struct qeth_cmd_buffer *qeth_get_adapter_cmd(struct qeth_card *card,
2581 __u32 command, __u32 cmdlen)
2582 {
2583 struct qeth_cmd_buffer *iob;
2584 struct qeth_ipa_cmd *cmd;
2585
2586 iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SETADAPTERPARMS,
2587 QETH_PROT_IPV4);
2588 cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
2589 cmd->data.setadapterparms.hdr.cmdlength = cmdlen;
2590 cmd->data.setadapterparms.hdr.command_code = command;
2591 cmd->data.setadapterparms.hdr.used_total = 1;
2592 cmd->data.setadapterparms.hdr.seq_no = 1;
2593
2594 return iob;
2595 }
2596 EXPORT_SYMBOL_GPL(qeth_get_adapter_cmd);
2597
qeth_query_setadapterparms(struct qeth_card * card)2598 int qeth_query_setadapterparms(struct qeth_card *card)
2599 {
2600 int rc;
2601 struct qeth_cmd_buffer *iob;
2602
2603 QETH_DBF_TEXT(TRACE, 3, "queryadp");
2604 iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_COMMANDS_SUPPORTED,
2605 sizeof(struct qeth_ipacmd_setadpparms));
2606 rc = qeth_send_ipa_cmd(card, iob, qeth_query_setadapterparms_cb, NULL);
2607 return rc;
2608 }
2609 EXPORT_SYMBOL_GPL(qeth_query_setadapterparms);
2610
qeth_check_qdio_errors(struct qdio_buffer * buf,unsigned int qdio_error,const char * dbftext)2611 int qeth_check_qdio_errors(struct qdio_buffer *buf, unsigned int qdio_error,
2612 const char *dbftext)
2613 {
2614 if (qdio_error) {
2615 QETH_DBF_TEXT(TRACE, 2, dbftext);
2616 QETH_DBF_TEXT(QERR, 2, dbftext);
2617 QETH_DBF_TEXT_(QERR, 2, " F15=%02X",
2618 buf->element[15].flags & 0xff);
2619 QETH_DBF_TEXT_(QERR, 2, " F14=%02X",
2620 buf->element[14].flags & 0xff);
2621 QETH_DBF_TEXT_(QERR, 2, " qerr=%X", qdio_error);
2622 return 1;
2623 }
2624 return 0;
2625 }
2626 EXPORT_SYMBOL_GPL(qeth_check_qdio_errors);
2627
qeth_queue_input_buffer(struct qeth_card * card,int index)2628 void qeth_queue_input_buffer(struct qeth_card *card, int index)
2629 {
2630 struct qeth_qdio_q *queue = card->qdio.in_q;
2631 int count;
2632 int i;
2633 int rc;
2634 int newcount = 0;
2635
2636 count = (index < queue->next_buf_to_init)?
2637 card->qdio.in_buf_pool.buf_count -
2638 (queue->next_buf_to_init - index) :
2639 card->qdio.in_buf_pool.buf_count -
2640 (queue->next_buf_to_init + QDIO_MAX_BUFFERS_PER_Q - index);
2641 /* only requeue at a certain threshold to avoid SIGAs */
2642 if (count >= QETH_IN_BUF_REQUEUE_THRESHOLD(card)) {
2643 for (i = queue->next_buf_to_init;
2644 i < queue->next_buf_to_init + count; ++i) {
2645 if (qeth_init_input_buffer(card,
2646 &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q])) {
2647 break;
2648 } else {
2649 newcount++;
2650 }
2651 }
2652
2653 if (newcount < count) {
2654 /* we are in memory shortage so we switch back to
2655 traditional skb allocation and drop packages */
2656 atomic_set(&card->force_alloc_skb, 3);
2657 count = newcount;
2658 } else {
2659 atomic_add_unless(&card->force_alloc_skb, -1, 0);
2660 }
2661
2662 /*
2663 * according to old code it should be avoided to requeue all
2664 * 128 buffers in order to benefit from PCI avoidance.
2665 * this function keeps at least one buffer (the buffer at
2666 * 'index') un-requeued -> this buffer is the first buffer that
2667 * will be requeued the next time
2668 */
2669 if (card->options.performance_stats) {
2670 card->perf_stats.inbound_do_qdio_cnt++;
2671 card->perf_stats.inbound_do_qdio_start_time =
2672 qeth_get_micros();
2673 }
2674 rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0,
2675 queue->next_buf_to_init, count);
2676 if (card->options.performance_stats)
2677 card->perf_stats.inbound_do_qdio_time +=
2678 qeth_get_micros() -
2679 card->perf_stats.inbound_do_qdio_start_time;
2680 if (rc) {
2681 dev_warn(&card->gdev->dev,
2682 "QDIO reported an error, rc=%i\n", rc);
2683 QETH_DBF_TEXT(TRACE, 2, "qinberr");
2684 QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
2685 }
2686 queue->next_buf_to_init = (queue->next_buf_to_init + count) %
2687 QDIO_MAX_BUFFERS_PER_Q;
2688 }
2689 }
2690 EXPORT_SYMBOL_GPL(qeth_queue_input_buffer);
2691
qeth_handle_send_error(struct qeth_card * card,struct qeth_qdio_out_buffer * buffer,unsigned int qdio_err)2692 static int qeth_handle_send_error(struct qeth_card *card,
2693 struct qeth_qdio_out_buffer *buffer, unsigned int qdio_err)
2694 {
2695 int sbalf15 = buffer->buffer->element[15].flags & 0xff;
2696 int cc = qdio_err & 3;
2697
2698 QETH_DBF_TEXT(TRACE, 6, "hdsnderr");
2699 qeth_check_qdio_errors(buffer->buffer, qdio_err, "qouterr");
2700 switch (cc) {
2701 case 0:
2702 if (qdio_err) {
2703 QETH_DBF_TEXT(TRACE, 1, "lnkfail");
2704 QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card));
2705 QETH_DBF_TEXT_(TRACE, 1, "%04x %02x",
2706 (u16)qdio_err, (u8)sbalf15);
2707 return QETH_SEND_ERROR_LINK_FAILURE;
2708 }
2709 return QETH_SEND_ERROR_NONE;
2710 case 2:
2711 if (qdio_err & QDIO_ERROR_SIGA_BUSY) {
2712 QETH_DBF_TEXT(TRACE, 1, "SIGAcc2B");
2713 QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card));
2714 return QETH_SEND_ERROR_KICK_IT;
2715 }
2716 if ((sbalf15 >= 15) && (sbalf15 <= 31))
2717 return QETH_SEND_ERROR_RETRY;
2718 return QETH_SEND_ERROR_LINK_FAILURE;
2719 /* look at qdio_error and sbalf 15 */
2720 case 1:
2721 QETH_DBF_TEXT(TRACE, 1, "SIGAcc1");
2722 QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card));
2723 return QETH_SEND_ERROR_LINK_FAILURE;
2724 case 3:
2725 default:
2726 QETH_DBF_TEXT(TRACE, 1, "SIGAcc3");
2727 QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card));
2728 return QETH_SEND_ERROR_KICK_IT;
2729 }
2730 }
2731
2732 /*
2733 * Switched to packing state if the number of used buffers on a queue
2734 * reaches a certain limit.
2735 */
qeth_switch_to_packing_if_needed(struct qeth_qdio_out_q * queue)2736 static void qeth_switch_to_packing_if_needed(struct qeth_qdio_out_q *queue)
2737 {
2738 if (!queue->do_pack) {
2739 if (atomic_read(&queue->used_buffers)
2740 >= QETH_HIGH_WATERMARK_PACK){
2741 /* switch non-PACKING -> PACKING */
2742 QETH_DBF_TEXT(TRACE, 6, "np->pack");
2743 if (queue->card->options.performance_stats)
2744 queue->card->perf_stats.sc_dp_p++;
2745 queue->do_pack = 1;
2746 }
2747 }
2748 }
2749
2750 /*
2751 * Switches from packing to non-packing mode. If there is a packing
2752 * buffer on the queue this buffer will be prepared to be flushed.
2753 * In that case 1 is returned to inform the caller. If no buffer
2754 * has to be flushed, zero is returned.
2755 */
qeth_switch_to_nonpacking_if_needed(struct qeth_qdio_out_q * queue)2756 static int qeth_switch_to_nonpacking_if_needed(struct qeth_qdio_out_q *queue)
2757 {
2758 struct qeth_qdio_out_buffer *buffer;
2759 int flush_count = 0;
2760
2761 if (queue->do_pack) {
2762 if (atomic_read(&queue->used_buffers)
2763 <= QETH_LOW_WATERMARK_PACK) {
2764 /* switch PACKING -> non-PACKING */
2765 QETH_DBF_TEXT(TRACE, 6, "pack->np");
2766 if (queue->card->options.performance_stats)
2767 queue->card->perf_stats.sc_p_dp++;
2768 queue->do_pack = 0;
2769 /* flush packing buffers */
2770 buffer = &queue->bufs[queue->next_buf_to_fill];
2771 if ((atomic_read(&buffer->state) ==
2772 QETH_QDIO_BUF_EMPTY) &&
2773 (buffer->next_element_to_fill > 0)) {
2774 atomic_set(&buffer->state,
2775 QETH_QDIO_BUF_PRIMED);
2776 flush_count++;
2777 queue->next_buf_to_fill =
2778 (queue->next_buf_to_fill + 1) %
2779 QDIO_MAX_BUFFERS_PER_Q;
2780 }
2781 }
2782 }
2783 return flush_count;
2784 }
2785
2786 /*
2787 * Called to flush a packing buffer if no more pci flags are on the queue.
2788 * Checks if there is a packing buffer and prepares it to be flushed.
2789 * In that case returns 1, otherwise zero.
2790 */
qeth_flush_buffers_on_no_pci(struct qeth_qdio_out_q * queue)2791 static int qeth_flush_buffers_on_no_pci(struct qeth_qdio_out_q *queue)
2792 {
2793 struct qeth_qdio_out_buffer *buffer;
2794
2795 buffer = &queue->bufs[queue->next_buf_to_fill];
2796 if ((atomic_read(&buffer->state) == QETH_QDIO_BUF_EMPTY) &&
2797 (buffer->next_element_to_fill > 0)) {
2798 /* it's a packing buffer */
2799 atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
2800 queue->next_buf_to_fill =
2801 (queue->next_buf_to_fill + 1) % QDIO_MAX_BUFFERS_PER_Q;
2802 return 1;
2803 }
2804 return 0;
2805 }
2806
qeth_flush_buffers(struct qeth_qdio_out_q * queue,int index,int count)2807 static void qeth_flush_buffers(struct qeth_qdio_out_q *queue, int index,
2808 int count)
2809 {
2810 struct qeth_qdio_out_buffer *buf;
2811 int rc;
2812 int i;
2813 unsigned int qdio_flags;
2814
2815 for (i = index; i < index + count; ++i) {
2816 buf = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
2817 buf->buffer->element[buf->next_element_to_fill - 1].flags |=
2818 SBAL_FLAGS_LAST_ENTRY;
2819
2820 if (queue->card->info.type == QETH_CARD_TYPE_IQD)
2821 continue;
2822
2823 if (!queue->do_pack) {
2824 if ((atomic_read(&queue->used_buffers) >=
2825 (QETH_HIGH_WATERMARK_PACK -
2826 QETH_WATERMARK_PACK_FUZZ)) &&
2827 !atomic_read(&queue->set_pci_flags_count)) {
2828 /* it's likely that we'll go to packing
2829 * mode soon */
2830 atomic_inc(&queue->set_pci_flags_count);
2831 buf->buffer->element[0].flags |= 0x40;
2832 }
2833 } else {
2834 if (!atomic_read(&queue->set_pci_flags_count)) {
2835 /*
2836 * there's no outstanding PCI any more, so we
2837 * have to request a PCI to be sure the the PCI
2838 * will wake at some time in the future then we
2839 * can flush packed buffers that might still be
2840 * hanging around, which can happen if no
2841 * further send was requested by the stack
2842 */
2843 atomic_inc(&queue->set_pci_flags_count);
2844 buf->buffer->element[0].flags |= 0x40;
2845 }
2846 }
2847 }
2848
2849 queue->card->dev->trans_start = jiffies;
2850 if (queue->card->options.performance_stats) {
2851 queue->card->perf_stats.outbound_do_qdio_cnt++;
2852 queue->card->perf_stats.outbound_do_qdio_start_time =
2853 qeth_get_micros();
2854 }
2855 qdio_flags = QDIO_FLAG_SYNC_OUTPUT;
2856 if (atomic_read(&queue->set_pci_flags_count))
2857 qdio_flags |= QDIO_FLAG_PCI_OUT;
2858 rc = do_QDIO(CARD_DDEV(queue->card), qdio_flags,
2859 queue->queue_no, index, count);
2860 if (queue->card->options.performance_stats)
2861 queue->card->perf_stats.outbound_do_qdio_time +=
2862 qeth_get_micros() -
2863 queue->card->perf_stats.outbound_do_qdio_start_time;
2864 if (rc) {
2865 QETH_DBF_TEXT(TRACE, 2, "flushbuf");
2866 QETH_DBF_TEXT_(TRACE, 2, " err%d", rc);
2867 QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_DDEV_ID(queue->card));
2868 queue->card->stats.tx_errors += count;
2869 /* this must not happen under normal circumstances. if it
2870 * happens something is really wrong -> recover */
2871 qeth_schedule_recovery(queue->card);
2872 return;
2873 }
2874 atomic_add(count, &queue->used_buffers);
2875 if (queue->card->options.performance_stats)
2876 queue->card->perf_stats.bufs_sent += count;
2877 }
2878
qeth_check_outbound_queue(struct qeth_qdio_out_q * queue)2879 static void qeth_check_outbound_queue(struct qeth_qdio_out_q *queue)
2880 {
2881 int index;
2882 int flush_cnt = 0;
2883 int q_was_packing = 0;
2884
2885 /*
2886 * check if weed have to switch to non-packing mode or if
2887 * we have to get a pci flag out on the queue
2888 */
2889 if ((atomic_read(&queue->used_buffers) <= QETH_LOW_WATERMARK_PACK) ||
2890 !atomic_read(&queue->set_pci_flags_count)) {
2891 if (atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH) ==
2892 QETH_OUT_Q_UNLOCKED) {
2893 /*
2894 * If we get in here, there was no action in
2895 * do_send_packet. So, we check if there is a
2896 * packing buffer to be flushed here.
2897 */
2898 netif_stop_queue(queue->card->dev);
2899 index = queue->next_buf_to_fill;
2900 q_was_packing = queue->do_pack;
2901 /* queue->do_pack may change */
2902 barrier();
2903 flush_cnt += qeth_switch_to_nonpacking_if_needed(queue);
2904 if (!flush_cnt &&
2905 !atomic_read(&queue->set_pci_flags_count))
2906 flush_cnt +=
2907 qeth_flush_buffers_on_no_pci(queue);
2908 if (queue->card->options.performance_stats &&
2909 q_was_packing)
2910 queue->card->perf_stats.bufs_sent_pack +=
2911 flush_cnt;
2912 if (flush_cnt)
2913 qeth_flush_buffers(queue, index, flush_cnt);
2914 atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
2915 }
2916 }
2917 }
2918
qeth_qdio_output_handler(struct ccw_device * ccwdev,unsigned int qdio_error,int __queue,int first_element,int count,unsigned long card_ptr)2919 void qeth_qdio_output_handler(struct ccw_device *ccwdev,
2920 unsigned int qdio_error, int __queue, int first_element,
2921 int count, unsigned long card_ptr)
2922 {
2923 struct qeth_card *card = (struct qeth_card *) card_ptr;
2924 struct qeth_qdio_out_q *queue = card->qdio.out_qs[__queue];
2925 struct qeth_qdio_out_buffer *buffer;
2926 int i;
2927
2928 QETH_DBF_TEXT(TRACE, 6, "qdouhdl");
2929 if (qdio_error & QDIO_ERROR_ACTIVATE_CHECK_CONDITION) {
2930 QETH_DBF_TEXT(TRACE, 2, "achkcond");
2931 QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
2932 netif_stop_queue(card->dev);
2933 qeth_schedule_recovery(card);
2934 return;
2935 }
2936 if (card->options.performance_stats) {
2937 card->perf_stats.outbound_handler_cnt++;
2938 card->perf_stats.outbound_handler_start_time =
2939 qeth_get_micros();
2940 }
2941 for (i = first_element; i < (first_element + count); ++i) {
2942 buffer = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
2943 /*we only handle the KICK_IT error by doing a recovery */
2944 if (qeth_handle_send_error(card, buffer, qdio_error)
2945 == QETH_SEND_ERROR_KICK_IT){
2946 netif_stop_queue(card->dev);
2947 qeth_schedule_recovery(card);
2948 return;
2949 }
2950 qeth_clear_output_buffer(queue, buffer);
2951 }
2952 atomic_sub(count, &queue->used_buffers);
2953 /* check if we need to do something on this outbound queue */
2954 if (card->info.type != QETH_CARD_TYPE_IQD)
2955 qeth_check_outbound_queue(queue);
2956
2957 netif_wake_queue(queue->card->dev);
2958 if (card->options.performance_stats)
2959 card->perf_stats.outbound_handler_time += qeth_get_micros() -
2960 card->perf_stats.outbound_handler_start_time;
2961 }
2962 EXPORT_SYMBOL_GPL(qeth_qdio_output_handler);
2963
qeth_get_cast_type(struct qeth_card * card,struct sk_buff * skb)2964 int qeth_get_cast_type(struct qeth_card *card, struct sk_buff *skb)
2965 {
2966 int cast_type = RTN_UNSPEC;
2967
2968 if (card->info.type == QETH_CARD_TYPE_OSN)
2969 return cast_type;
2970
2971 if (skb->dst && skb->dst->neighbour) {
2972 cast_type = skb->dst->neighbour->type;
2973 if ((cast_type == RTN_BROADCAST) ||
2974 (cast_type == RTN_MULTICAST) ||
2975 (cast_type == RTN_ANYCAST))
2976 return cast_type;
2977 else
2978 return RTN_UNSPEC;
2979 }
2980 /* try something else */
2981 if (skb->protocol == ETH_P_IPV6)
2982 return (skb_network_header(skb)[24] == 0xff) ?
2983 RTN_MULTICAST : 0;
2984 else if (skb->protocol == ETH_P_IP)
2985 return ((skb_network_header(skb)[16] & 0xf0) == 0xe0) ?
2986 RTN_MULTICAST : 0;
2987 /* ... */
2988 if (!memcmp(skb->data, skb->dev->broadcast, 6))
2989 return RTN_BROADCAST;
2990 else {
2991 u16 hdr_mac;
2992
2993 hdr_mac = *((u16 *)skb->data);
2994 /* tr multicast? */
2995 switch (card->info.link_type) {
2996 case QETH_LINK_TYPE_HSTR:
2997 case QETH_LINK_TYPE_LANE_TR:
2998 if ((hdr_mac == QETH_TR_MAC_NC) ||
2999 (hdr_mac == QETH_TR_MAC_C))
3000 return RTN_MULTICAST;
3001 break;
3002 /* eth or so multicast? */
3003 default:
3004 if ((hdr_mac == QETH_ETH_MAC_V4) ||
3005 (hdr_mac == QETH_ETH_MAC_V6))
3006 return RTN_MULTICAST;
3007 }
3008 }
3009 return cast_type;
3010 }
3011 EXPORT_SYMBOL_GPL(qeth_get_cast_type);
3012
qeth_get_priority_queue(struct qeth_card * card,struct sk_buff * skb,int ipv,int cast_type)3013 int qeth_get_priority_queue(struct qeth_card *card, struct sk_buff *skb,
3014 int ipv, int cast_type)
3015 {
3016 if (!ipv && (card->info.type == QETH_CARD_TYPE_OSAE))
3017 return card->qdio.default_out_queue;
3018 switch (card->qdio.no_out_queues) {
3019 case 4:
3020 if (cast_type && card->info.is_multicast_different)
3021 return card->info.is_multicast_different &
3022 (card->qdio.no_out_queues - 1);
3023 if (card->qdio.do_prio_queueing && (ipv == 4)) {
3024 const u8 tos = ip_hdr(skb)->tos;
3025
3026 if (card->qdio.do_prio_queueing ==
3027 QETH_PRIO_Q_ING_TOS) {
3028 if (tos & IP_TOS_NOTIMPORTANT)
3029 return 3;
3030 if (tos & IP_TOS_HIGHRELIABILITY)
3031 return 2;
3032 if (tos & IP_TOS_HIGHTHROUGHPUT)
3033 return 1;
3034 if (tos & IP_TOS_LOWDELAY)
3035 return 0;
3036 }
3037 if (card->qdio.do_prio_queueing ==
3038 QETH_PRIO_Q_ING_PREC)
3039 return 3 - (tos >> 6);
3040 } else if (card->qdio.do_prio_queueing && (ipv == 6)) {
3041 /* TODO: IPv6!!! */
3042 }
3043 return card->qdio.default_out_queue;
3044 case 1: /* fallthrough for single-out-queue 1920-device */
3045 default:
3046 return card->qdio.default_out_queue;
3047 }
3048 }
3049 EXPORT_SYMBOL_GPL(qeth_get_priority_queue);
3050
qeth_get_elements_no(struct qeth_card * card,void * hdr,struct sk_buff * skb,int elems)3051 int qeth_get_elements_no(struct qeth_card *card, void *hdr,
3052 struct sk_buff *skb, int elems)
3053 {
3054 int elements_needed = 0;
3055
3056 if (skb_shinfo(skb)->nr_frags > 0)
3057 elements_needed = (skb_shinfo(skb)->nr_frags + 1);
3058 if (elements_needed == 0)
3059 elements_needed = 1 + (((((unsigned long) skb->data) %
3060 PAGE_SIZE) + skb->len) >> PAGE_SHIFT);
3061 if ((elements_needed + elems) > QETH_MAX_BUFFER_ELEMENTS(card)) {
3062 QETH_DBF_MESSAGE(2, "Invalid size of IP packet "
3063 "(Number=%d / Length=%d). Discarded.\n",
3064 (elements_needed+elems), skb->len);
3065 return 0;
3066 }
3067 return elements_needed;
3068 }
3069 EXPORT_SYMBOL_GPL(qeth_get_elements_no);
3070
__qeth_fill_buffer(struct sk_buff * skb,struct qdio_buffer * buffer,int is_tso,int * next_element_to_fill,int offset)3071 static inline void __qeth_fill_buffer(struct sk_buff *skb,
3072 struct qdio_buffer *buffer, int is_tso, int *next_element_to_fill,
3073 int offset)
3074 {
3075 int length = skb->len;
3076 int length_here;
3077 int element;
3078 char *data;
3079 int first_lap ;
3080
3081 element = *next_element_to_fill;
3082 data = skb->data;
3083 first_lap = (is_tso == 0 ? 1 : 0);
3084
3085 if (offset >= 0) {
3086 data = skb->data + offset;
3087 length -= offset;
3088 first_lap = 0;
3089 }
3090
3091 while (length > 0) {
3092 /* length_here is the remaining amount of data in this page */
3093 length_here = PAGE_SIZE - ((unsigned long) data % PAGE_SIZE);
3094 if (length < length_here)
3095 length_here = length;
3096
3097 buffer->element[element].addr = data;
3098 buffer->element[element].length = length_here;
3099 length -= length_here;
3100 if (!length) {
3101 if (first_lap)
3102 buffer->element[element].flags = 0;
3103 else
3104 buffer->element[element].flags =
3105 SBAL_FLAGS_LAST_FRAG;
3106 } else {
3107 if (first_lap)
3108 buffer->element[element].flags =
3109 SBAL_FLAGS_FIRST_FRAG;
3110 else
3111 buffer->element[element].flags =
3112 SBAL_FLAGS_MIDDLE_FRAG;
3113 }
3114 data += length_here;
3115 element++;
3116 first_lap = 0;
3117 }
3118 *next_element_to_fill = element;
3119 }
3120
qeth_fill_buffer(struct qeth_qdio_out_q * queue,struct qeth_qdio_out_buffer * buf,struct sk_buff * skb,struct qeth_hdr * hdr,int offset,int hd_len)3121 static inline int qeth_fill_buffer(struct qeth_qdio_out_q *queue,
3122 struct qeth_qdio_out_buffer *buf, struct sk_buff *skb,
3123 struct qeth_hdr *hdr, int offset, int hd_len)
3124 {
3125 struct qdio_buffer *buffer;
3126 int flush_cnt = 0, hdr_len, large_send = 0;
3127
3128 buffer = buf->buffer;
3129 atomic_inc(&skb->users);
3130 skb_queue_tail(&buf->skb_list, skb);
3131
3132 /*check first on TSO ....*/
3133 if (hdr->hdr.l3.id == QETH_HEADER_TYPE_TSO) {
3134 int element = buf->next_element_to_fill;
3135
3136 hdr_len = sizeof(struct qeth_hdr_tso) +
3137 ((struct qeth_hdr_tso *)hdr)->ext.dg_hdr_len;
3138 /*fill first buffer entry only with header information */
3139 buffer->element[element].addr = skb->data;
3140 buffer->element[element].length = hdr_len;
3141 buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG;
3142 buf->next_element_to_fill++;
3143 skb->data += hdr_len;
3144 skb->len -= hdr_len;
3145 large_send = 1;
3146 }
3147
3148 if (offset >= 0) {
3149 int element = buf->next_element_to_fill;
3150 buffer->element[element].addr = hdr;
3151 buffer->element[element].length = sizeof(struct qeth_hdr) +
3152 hd_len;
3153 buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG;
3154 buf->is_header[element] = 1;
3155 buf->next_element_to_fill++;
3156 }
3157
3158 if (skb_shinfo(skb)->nr_frags == 0)
3159 __qeth_fill_buffer(skb, buffer, large_send,
3160 (int *)&buf->next_element_to_fill, offset);
3161 else
3162 __qeth_fill_buffer_frag(skb, buffer, large_send,
3163 (int *)&buf->next_element_to_fill);
3164
3165 if (!queue->do_pack) {
3166 QETH_DBF_TEXT(TRACE, 6, "fillbfnp");
3167 /* set state to PRIMED -> will be flushed */
3168 atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
3169 flush_cnt = 1;
3170 } else {
3171 QETH_DBF_TEXT(TRACE, 6, "fillbfpa");
3172 if (queue->card->options.performance_stats)
3173 queue->card->perf_stats.skbs_sent_pack++;
3174 if (buf->next_element_to_fill >=
3175 QETH_MAX_BUFFER_ELEMENTS(queue->card)) {
3176 /*
3177 * packed buffer if full -> set state PRIMED
3178 * -> will be flushed
3179 */
3180 atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
3181 flush_cnt = 1;
3182 }
3183 }
3184 return flush_cnt;
3185 }
3186
qeth_do_send_packet_fast(struct qeth_card * card,struct qeth_qdio_out_q * queue,struct sk_buff * skb,struct qeth_hdr * hdr,int elements_needed,struct qeth_eddp_context * ctx,int offset,int hd_len)3187 int qeth_do_send_packet_fast(struct qeth_card *card,
3188 struct qeth_qdio_out_q *queue, struct sk_buff *skb,
3189 struct qeth_hdr *hdr, int elements_needed,
3190 struct qeth_eddp_context *ctx, int offset, int hd_len)
3191 {
3192 struct qeth_qdio_out_buffer *buffer;
3193 int buffers_needed = 0;
3194 int flush_cnt = 0;
3195 int index;
3196
3197 /* spin until we get the queue ... */
3198 while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
3199 QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
3200 /* ... now we've got the queue */
3201 index = queue->next_buf_to_fill;
3202 buffer = &queue->bufs[queue->next_buf_to_fill];
3203 /*
3204 * check if buffer is empty to make sure that we do not 'overtake'
3205 * ourselves and try to fill a buffer that is already primed
3206 */
3207 if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY)
3208 goto out;
3209 if (ctx == NULL)
3210 queue->next_buf_to_fill = (queue->next_buf_to_fill + 1) %
3211 QDIO_MAX_BUFFERS_PER_Q;
3212 else {
3213 buffers_needed = qeth_eddp_check_buffers_for_context(queue,
3214 ctx);
3215 if (buffers_needed < 0)
3216 goto out;
3217 queue->next_buf_to_fill =
3218 (queue->next_buf_to_fill + buffers_needed) %
3219 QDIO_MAX_BUFFERS_PER_Q;
3220 }
3221 atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
3222 if (ctx == NULL) {
3223 qeth_fill_buffer(queue, buffer, skb, hdr, offset, hd_len);
3224 qeth_flush_buffers(queue, index, 1);
3225 } else {
3226 flush_cnt = qeth_eddp_fill_buffer(queue, ctx, index);
3227 WARN_ON(buffers_needed != flush_cnt);
3228 qeth_flush_buffers(queue, index, flush_cnt);
3229 }
3230 return 0;
3231 out:
3232 atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
3233 return -EBUSY;
3234 }
3235 EXPORT_SYMBOL_GPL(qeth_do_send_packet_fast);
3236
qeth_do_send_packet(struct qeth_card * card,struct qeth_qdio_out_q * queue,struct sk_buff * skb,struct qeth_hdr * hdr,int elements_needed,struct qeth_eddp_context * ctx)3237 int qeth_do_send_packet(struct qeth_card *card, struct qeth_qdio_out_q *queue,
3238 struct sk_buff *skb, struct qeth_hdr *hdr,
3239 int elements_needed, struct qeth_eddp_context *ctx)
3240 {
3241 struct qeth_qdio_out_buffer *buffer;
3242 int start_index;
3243 int flush_count = 0;
3244 int do_pack = 0;
3245 int tmp;
3246 int rc = 0;
3247
3248 /* spin until we get the queue ... */
3249 while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
3250 QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
3251 start_index = queue->next_buf_to_fill;
3252 buffer = &queue->bufs[queue->next_buf_to_fill];
3253 /*
3254 * check if buffer is empty to make sure that we do not 'overtake'
3255 * ourselves and try to fill a buffer that is already primed
3256 */
3257 if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY) {
3258 atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
3259 return -EBUSY;
3260 }
3261 /* check if we need to switch packing state of this queue */
3262 qeth_switch_to_packing_if_needed(queue);
3263 if (queue->do_pack) {
3264 do_pack = 1;
3265 if (ctx == NULL) {
3266 /* does packet fit in current buffer? */
3267 if ((QETH_MAX_BUFFER_ELEMENTS(card) -
3268 buffer->next_element_to_fill) < elements_needed) {
3269 /* ... no -> set state PRIMED */
3270 atomic_set(&buffer->state,
3271 QETH_QDIO_BUF_PRIMED);
3272 flush_count++;
3273 queue->next_buf_to_fill =
3274 (queue->next_buf_to_fill + 1) %
3275 QDIO_MAX_BUFFERS_PER_Q;
3276 buffer = &queue->bufs[queue->next_buf_to_fill];
3277 /* we did a step forward, so check buffer state
3278 * again */
3279 if (atomic_read(&buffer->state) !=
3280 QETH_QDIO_BUF_EMPTY){
3281 qeth_flush_buffers(queue, start_index,
3282 flush_count);
3283 atomic_set(&queue->state,
3284 QETH_OUT_Q_UNLOCKED);
3285 return -EBUSY;
3286 }
3287 }
3288 } else {
3289 /* check if we have enough elements (including following
3290 * free buffers) to handle eddp context */
3291 if (qeth_eddp_check_buffers_for_context(queue, ctx)
3292 < 0) {
3293 rc = -EBUSY;
3294 goto out;
3295 }
3296 }
3297 }
3298 if (ctx == NULL)
3299 tmp = qeth_fill_buffer(queue, buffer, skb, hdr, -1, 0);
3300 else {
3301 tmp = qeth_eddp_fill_buffer(queue, ctx,
3302 queue->next_buf_to_fill);
3303 if (tmp < 0) {
3304 rc = -EBUSY;
3305 goto out;
3306 }
3307 }
3308 queue->next_buf_to_fill = (queue->next_buf_to_fill + tmp) %
3309 QDIO_MAX_BUFFERS_PER_Q;
3310 flush_count += tmp;
3311 out:
3312 if (flush_count)
3313 qeth_flush_buffers(queue, start_index, flush_count);
3314 else if (!atomic_read(&queue->set_pci_flags_count))
3315 atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH);
3316 /*
3317 * queue->state will go from LOCKED -> UNLOCKED or from
3318 * LOCKED_FLUSH -> LOCKED if output_handler wanted to 'notify' us
3319 * (switch packing state or flush buffer to get another pci flag out).
3320 * In that case we will enter this loop
3321 */
3322 while (atomic_dec_return(&queue->state)) {
3323 flush_count = 0;
3324 start_index = queue->next_buf_to_fill;
3325 /* check if we can go back to non-packing state */
3326 flush_count += qeth_switch_to_nonpacking_if_needed(queue);
3327 /*
3328 * check if we need to flush a packing buffer to get a pci
3329 * flag out on the queue
3330 */
3331 if (!flush_count && !atomic_read(&queue->set_pci_flags_count))
3332 flush_count += qeth_flush_buffers_on_no_pci(queue);
3333 if (flush_count)
3334 qeth_flush_buffers(queue, start_index, flush_count);
3335 }
3336 /* at this point the queue is UNLOCKED again */
3337 if (queue->card->options.performance_stats && do_pack)
3338 queue->card->perf_stats.bufs_sent_pack += flush_count;
3339
3340 return rc;
3341 }
3342 EXPORT_SYMBOL_GPL(qeth_do_send_packet);
3343
qeth_setadp_promisc_mode_cb(struct qeth_card * card,struct qeth_reply * reply,unsigned long data)3344 static int qeth_setadp_promisc_mode_cb(struct qeth_card *card,
3345 struct qeth_reply *reply, unsigned long data)
3346 {
3347 struct qeth_ipa_cmd *cmd;
3348 struct qeth_ipacmd_setadpparms *setparms;
3349
3350 QETH_DBF_TEXT(TRACE, 4, "prmadpcb");
3351
3352 cmd = (struct qeth_ipa_cmd *) data;
3353 setparms = &(cmd->data.setadapterparms);
3354
3355 qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
3356 if (cmd->hdr.return_code) {
3357 QETH_DBF_TEXT_(TRACE, 4, "prmrc%2.2x", cmd->hdr.return_code);
3358 setparms->data.mode = SET_PROMISC_MODE_OFF;
3359 }
3360 card->info.promisc_mode = setparms->data.mode;
3361 return 0;
3362 }
3363
qeth_setadp_promisc_mode(struct qeth_card * card)3364 void qeth_setadp_promisc_mode(struct qeth_card *card)
3365 {
3366 enum qeth_ipa_promisc_modes mode;
3367 struct net_device *dev = card->dev;
3368 struct qeth_cmd_buffer *iob;
3369 struct qeth_ipa_cmd *cmd;
3370
3371 QETH_DBF_TEXT(TRACE, 4, "setprom");
3372
3373 if (((dev->flags & IFF_PROMISC) &&
3374 (card->info.promisc_mode == SET_PROMISC_MODE_ON)) ||
3375 (!(dev->flags & IFF_PROMISC) &&
3376 (card->info.promisc_mode == SET_PROMISC_MODE_OFF)))
3377 return;
3378 mode = SET_PROMISC_MODE_OFF;
3379 if (dev->flags & IFF_PROMISC)
3380 mode = SET_PROMISC_MODE_ON;
3381 QETH_DBF_TEXT_(TRACE, 4, "mode:%x", mode);
3382
3383 iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_PROMISC_MODE,
3384 sizeof(struct qeth_ipacmd_setadpparms));
3385 cmd = (struct qeth_ipa_cmd *)(iob->data + IPA_PDU_HEADER_SIZE);
3386 cmd->data.setadapterparms.data.mode = mode;
3387 qeth_send_ipa_cmd(card, iob, qeth_setadp_promisc_mode_cb, NULL);
3388 }
3389 EXPORT_SYMBOL_GPL(qeth_setadp_promisc_mode);
3390
qeth_change_mtu(struct net_device * dev,int new_mtu)3391 int qeth_change_mtu(struct net_device *dev, int new_mtu)
3392 {
3393 struct qeth_card *card;
3394 char dbf_text[15];
3395
3396 card = dev->ml_priv;
3397
3398 QETH_DBF_TEXT(TRACE, 4, "chgmtu");
3399 sprintf(dbf_text, "%8x", new_mtu);
3400 QETH_DBF_TEXT(TRACE, 4, dbf_text);
3401
3402 if (new_mtu < 64)
3403 return -EINVAL;
3404 if (new_mtu > 65535)
3405 return -EINVAL;
3406 if ((!qeth_is_supported(card, IPA_IP_FRAGMENTATION)) &&
3407 (!qeth_mtu_is_valid(card, new_mtu)))
3408 return -EINVAL;
3409 dev->mtu = new_mtu;
3410 return 0;
3411 }
3412 EXPORT_SYMBOL_GPL(qeth_change_mtu);
3413
qeth_get_stats(struct net_device * dev)3414 struct net_device_stats *qeth_get_stats(struct net_device *dev)
3415 {
3416 struct qeth_card *card;
3417
3418 card = dev->ml_priv;
3419
3420 QETH_DBF_TEXT(TRACE, 5, "getstat");
3421
3422 return &card->stats;
3423 }
3424 EXPORT_SYMBOL_GPL(qeth_get_stats);
3425
qeth_setadpparms_change_macaddr_cb(struct qeth_card * card,struct qeth_reply * reply,unsigned long data)3426 static int qeth_setadpparms_change_macaddr_cb(struct qeth_card *card,
3427 struct qeth_reply *reply, unsigned long data)
3428 {
3429 struct qeth_ipa_cmd *cmd;
3430
3431 QETH_DBF_TEXT(TRACE, 4, "chgmaccb");
3432
3433 cmd = (struct qeth_ipa_cmd *) data;
3434 if (!card->options.layer2 ||
3435 !(card->info.mac_bits & QETH_LAYER2_MAC_READ)) {
3436 memcpy(card->dev->dev_addr,
3437 &cmd->data.setadapterparms.data.change_addr.addr,
3438 OSA_ADDR_LEN);
3439 card->info.mac_bits |= QETH_LAYER2_MAC_READ;
3440 }
3441 qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
3442 return 0;
3443 }
3444
qeth_setadpparms_change_macaddr(struct qeth_card * card)3445 int qeth_setadpparms_change_macaddr(struct qeth_card *card)
3446 {
3447 int rc;
3448 struct qeth_cmd_buffer *iob;
3449 struct qeth_ipa_cmd *cmd;
3450
3451 QETH_DBF_TEXT(TRACE, 4, "chgmac");
3452
3453 iob = qeth_get_adapter_cmd(card, IPA_SETADP_ALTER_MAC_ADDRESS,
3454 sizeof(struct qeth_ipacmd_setadpparms));
3455 cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
3456 cmd->data.setadapterparms.data.change_addr.cmd = CHANGE_ADDR_READ_MAC;
3457 cmd->data.setadapterparms.data.change_addr.addr_size = OSA_ADDR_LEN;
3458 memcpy(&cmd->data.setadapterparms.data.change_addr.addr,
3459 card->dev->dev_addr, OSA_ADDR_LEN);
3460 rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_change_macaddr_cb,
3461 NULL);
3462 return rc;
3463 }
3464 EXPORT_SYMBOL_GPL(qeth_setadpparms_change_macaddr);
3465
qeth_tx_timeout(struct net_device * dev)3466 void qeth_tx_timeout(struct net_device *dev)
3467 {
3468 struct qeth_card *card;
3469
3470 card = dev->ml_priv;
3471 card->stats.tx_errors++;
3472 qeth_schedule_recovery(card);
3473 }
3474 EXPORT_SYMBOL_GPL(qeth_tx_timeout);
3475
qeth_mdio_read(struct net_device * dev,int phy_id,int regnum)3476 int qeth_mdio_read(struct net_device *dev, int phy_id, int regnum)
3477 {
3478 struct qeth_card *card = dev->ml_priv;
3479 int rc = 0;
3480
3481 switch (regnum) {
3482 case MII_BMCR: /* Basic mode control register */
3483 rc = BMCR_FULLDPLX;
3484 if ((card->info.link_type != QETH_LINK_TYPE_GBIT_ETH) &&
3485 (card->info.link_type != QETH_LINK_TYPE_OSN) &&
3486 (card->info.link_type != QETH_LINK_TYPE_10GBIT_ETH))
3487 rc |= BMCR_SPEED100;
3488 break;
3489 case MII_BMSR: /* Basic mode status register */
3490 rc = BMSR_ERCAP | BMSR_ANEGCOMPLETE | BMSR_LSTATUS |
3491 BMSR_10HALF | BMSR_10FULL | BMSR_100HALF | BMSR_100FULL |
3492 BMSR_100BASE4;
3493 break;
3494 case MII_PHYSID1: /* PHYS ID 1 */
3495 rc = (dev->dev_addr[0] << 16) | (dev->dev_addr[1] << 8) |
3496 dev->dev_addr[2];
3497 rc = (rc >> 5) & 0xFFFF;
3498 break;
3499 case MII_PHYSID2: /* PHYS ID 2 */
3500 rc = (dev->dev_addr[2] << 10) & 0xFFFF;
3501 break;
3502 case MII_ADVERTISE: /* Advertisement control reg */
3503 rc = ADVERTISE_ALL;
3504 break;
3505 case MII_LPA: /* Link partner ability reg */
3506 rc = LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL |
3507 LPA_100BASE4 | LPA_LPACK;
3508 break;
3509 case MII_EXPANSION: /* Expansion register */
3510 break;
3511 case MII_DCOUNTER: /* disconnect counter */
3512 break;
3513 case MII_FCSCOUNTER: /* false carrier counter */
3514 break;
3515 case MII_NWAYTEST: /* N-way auto-neg test register */
3516 break;
3517 case MII_RERRCOUNTER: /* rx error counter */
3518 rc = card->stats.rx_errors;
3519 break;
3520 case MII_SREVISION: /* silicon revision */
3521 break;
3522 case MII_RESV1: /* reserved 1 */
3523 break;
3524 case MII_LBRERROR: /* loopback, rx, bypass error */
3525 break;
3526 case MII_PHYADDR: /* physical address */
3527 break;
3528 case MII_RESV2: /* reserved 2 */
3529 break;
3530 case MII_TPISTATUS: /* TPI status for 10mbps */
3531 break;
3532 case MII_NCONFIG: /* network interface config */
3533 break;
3534 default:
3535 break;
3536 }
3537 return rc;
3538 }
3539 EXPORT_SYMBOL_GPL(qeth_mdio_read);
3540
qeth_send_ipa_snmp_cmd(struct qeth_card * card,struct qeth_cmd_buffer * iob,int len,int (* reply_cb)(struct qeth_card *,struct qeth_reply *,unsigned long),void * reply_param)3541 static int qeth_send_ipa_snmp_cmd(struct qeth_card *card,
3542 struct qeth_cmd_buffer *iob, int len,
3543 int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
3544 unsigned long),
3545 void *reply_param)
3546 {
3547 u16 s1, s2;
3548
3549 QETH_DBF_TEXT(TRACE, 4, "sendsnmp");
3550
3551 memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
3552 memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
3553 &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
3554 /* adjust PDU length fields in IPA_PDU_HEADER */
3555 s1 = (u32) IPA_PDU_HEADER_SIZE + len;
3556 s2 = (u32) len;
3557 memcpy(QETH_IPA_PDU_LEN_TOTAL(iob->data), &s1, 2);
3558 memcpy(QETH_IPA_PDU_LEN_PDU1(iob->data), &s2, 2);
3559 memcpy(QETH_IPA_PDU_LEN_PDU2(iob->data), &s2, 2);
3560 memcpy(QETH_IPA_PDU_LEN_PDU3(iob->data), &s2, 2);
3561 return qeth_send_control_data(card, IPA_PDU_HEADER_SIZE + len, iob,
3562 reply_cb, reply_param);
3563 }
3564
qeth_snmp_command_cb(struct qeth_card * card,struct qeth_reply * reply,unsigned long sdata)3565 static int qeth_snmp_command_cb(struct qeth_card *card,
3566 struct qeth_reply *reply, unsigned long sdata)
3567 {
3568 struct qeth_ipa_cmd *cmd;
3569 struct qeth_arp_query_info *qinfo;
3570 struct qeth_snmp_cmd *snmp;
3571 unsigned char *data;
3572 __u16 data_len;
3573
3574 QETH_DBF_TEXT(TRACE, 3, "snpcmdcb");
3575
3576 cmd = (struct qeth_ipa_cmd *) sdata;
3577 data = (unsigned char *)((char *)cmd - reply->offset);
3578 qinfo = (struct qeth_arp_query_info *) reply->param;
3579 snmp = &cmd->data.setadapterparms.data.snmp;
3580
3581 if (cmd->hdr.return_code) {
3582 QETH_DBF_TEXT_(TRACE, 4, "scer1%i", cmd->hdr.return_code);
3583 return 0;
3584 }
3585 if (cmd->data.setadapterparms.hdr.return_code) {
3586 cmd->hdr.return_code =
3587 cmd->data.setadapterparms.hdr.return_code;
3588 QETH_DBF_TEXT_(TRACE, 4, "scer2%i", cmd->hdr.return_code);
3589 return 0;
3590 }
3591 data_len = *((__u16 *)QETH_IPA_PDU_LEN_PDU1(data));
3592 if (cmd->data.setadapterparms.hdr.seq_no == 1)
3593 data_len -= (__u16)((char *)&snmp->data - (char *)cmd);
3594 else
3595 data_len -= (__u16)((char *)&snmp->request - (char *)cmd);
3596
3597 /* check if there is enough room in userspace */
3598 if ((qinfo->udata_len - qinfo->udata_offset) < data_len) {
3599 QETH_DBF_TEXT_(TRACE, 4, "scer3%i", -ENOMEM);
3600 cmd->hdr.return_code = -ENOMEM;
3601 return 0;
3602 }
3603 QETH_DBF_TEXT_(TRACE, 4, "snore%i",
3604 cmd->data.setadapterparms.hdr.used_total);
3605 QETH_DBF_TEXT_(TRACE, 4, "sseqn%i",
3606 cmd->data.setadapterparms.hdr.seq_no);
3607 /*copy entries to user buffer*/
3608 if (cmd->data.setadapterparms.hdr.seq_no == 1) {
3609 memcpy(qinfo->udata + qinfo->udata_offset,
3610 (char *)snmp,
3611 data_len + offsetof(struct qeth_snmp_cmd, data));
3612 qinfo->udata_offset += offsetof(struct qeth_snmp_cmd, data);
3613 } else {
3614 memcpy(qinfo->udata + qinfo->udata_offset,
3615 (char *)&snmp->request, data_len);
3616 }
3617 qinfo->udata_offset += data_len;
3618 /* check if all replies received ... */
3619 QETH_DBF_TEXT_(TRACE, 4, "srtot%i",
3620 cmd->data.setadapterparms.hdr.used_total);
3621 QETH_DBF_TEXT_(TRACE, 4, "srseq%i",
3622 cmd->data.setadapterparms.hdr.seq_no);
3623 if (cmd->data.setadapterparms.hdr.seq_no <
3624 cmd->data.setadapterparms.hdr.used_total)
3625 return 1;
3626 return 0;
3627 }
3628
qeth_snmp_command(struct qeth_card * card,char __user * udata)3629 int qeth_snmp_command(struct qeth_card *card, char __user *udata)
3630 {
3631 struct qeth_cmd_buffer *iob;
3632 struct qeth_ipa_cmd *cmd;
3633 struct qeth_snmp_ureq *ureq;
3634 int req_len;
3635 struct qeth_arp_query_info qinfo = {0, };
3636 int rc = 0;
3637
3638 QETH_DBF_TEXT(TRACE, 3, "snmpcmd");
3639
3640 if (card->info.guestlan)
3641 return -EOPNOTSUPP;
3642
3643 if ((!qeth_adp_supported(card, IPA_SETADP_SET_SNMP_CONTROL)) &&
3644 (!card->options.layer2)) {
3645 return -EOPNOTSUPP;
3646 }
3647 /* skip 4 bytes (data_len struct member) to get req_len */
3648 if (copy_from_user(&req_len, udata + sizeof(int), sizeof(int)))
3649 return -EFAULT;
3650 ureq = kmalloc(req_len+sizeof(struct qeth_snmp_ureq_hdr), GFP_KERNEL);
3651 if (!ureq) {
3652 QETH_DBF_TEXT(TRACE, 2, "snmpnome");
3653 return -ENOMEM;
3654 }
3655 if (copy_from_user(ureq, udata,
3656 req_len + sizeof(struct qeth_snmp_ureq_hdr))) {
3657 kfree(ureq);
3658 return -EFAULT;
3659 }
3660 qinfo.udata_len = ureq->hdr.data_len;
3661 qinfo.udata = kzalloc(qinfo.udata_len, GFP_KERNEL);
3662 if (!qinfo.udata) {
3663 kfree(ureq);
3664 return -ENOMEM;
3665 }
3666 qinfo.udata_offset = sizeof(struct qeth_snmp_ureq_hdr);
3667
3668 iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_SNMP_CONTROL,
3669 QETH_SNMP_SETADP_CMDLENGTH + req_len);
3670 cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
3671 memcpy(&cmd->data.setadapterparms.data.snmp, &ureq->cmd, req_len);
3672 rc = qeth_send_ipa_snmp_cmd(card, iob, QETH_SETADP_BASE_LEN + req_len,
3673 qeth_snmp_command_cb, (void *)&qinfo);
3674 if (rc)
3675 QETH_DBF_MESSAGE(2, "SNMP command failed on %s: (0x%x)\n",
3676 QETH_CARD_IFNAME(card), rc);
3677 else {
3678 if (copy_to_user(udata, qinfo.udata, qinfo.udata_len))
3679 rc = -EFAULT;
3680 }
3681
3682 kfree(ureq);
3683 kfree(qinfo.udata);
3684 return rc;
3685 }
3686 EXPORT_SYMBOL_GPL(qeth_snmp_command);
3687
qeth_get_qdio_q_format(struct qeth_card * card)3688 static inline int qeth_get_qdio_q_format(struct qeth_card *card)
3689 {
3690 switch (card->info.type) {
3691 case QETH_CARD_TYPE_IQD:
3692 return 2;
3693 default:
3694 return 0;
3695 }
3696 }
3697
qeth_qdio_establish(struct qeth_card * card)3698 static int qeth_qdio_establish(struct qeth_card *card)
3699 {
3700 struct qdio_initialize init_data;
3701 char *qib_param_field;
3702 struct qdio_buffer **in_sbal_ptrs;
3703 struct qdio_buffer **out_sbal_ptrs;
3704 int i, j, k;
3705 int rc = 0;
3706
3707 QETH_DBF_TEXT(SETUP, 2, "qdioest");
3708
3709 qib_param_field = kzalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(char),
3710 GFP_KERNEL);
3711 if (!qib_param_field)
3712 return -ENOMEM;
3713
3714 qeth_create_qib_param_field(card, qib_param_field);
3715 qeth_create_qib_param_field_blkt(card, qib_param_field);
3716
3717 in_sbal_ptrs = kmalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(void *),
3718 GFP_KERNEL);
3719 if (!in_sbal_ptrs) {
3720 kfree(qib_param_field);
3721 return -ENOMEM;
3722 }
3723 for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
3724 in_sbal_ptrs[i] = (struct qdio_buffer *)
3725 virt_to_phys(card->qdio.in_q->bufs[i].buffer);
3726
3727 out_sbal_ptrs =
3728 kmalloc(card->qdio.no_out_queues * QDIO_MAX_BUFFERS_PER_Q *
3729 sizeof(void *), GFP_KERNEL);
3730 if (!out_sbal_ptrs) {
3731 kfree(in_sbal_ptrs);
3732 kfree(qib_param_field);
3733 return -ENOMEM;
3734 }
3735 for (i = 0, k = 0; i < card->qdio.no_out_queues; ++i)
3736 for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j, ++k) {
3737 out_sbal_ptrs[k] = (struct qdio_buffer *)virt_to_phys(
3738 card->qdio.out_qs[i]->bufs[j].buffer);
3739 }
3740
3741 memset(&init_data, 0, sizeof(struct qdio_initialize));
3742 init_data.cdev = CARD_DDEV(card);
3743 init_data.q_format = qeth_get_qdio_q_format(card);
3744 init_data.qib_param_field_format = 0;
3745 init_data.qib_param_field = qib_param_field;
3746 init_data.no_input_qs = 1;
3747 init_data.no_output_qs = card->qdio.no_out_queues;
3748 init_data.input_handler = card->discipline.input_handler;
3749 init_data.output_handler = card->discipline.output_handler;
3750 init_data.int_parm = (unsigned long) card;
3751 init_data.flags = QDIO_INBOUND_0COPY_SBALS |
3752 QDIO_OUTBOUND_0COPY_SBALS |
3753 QDIO_USE_OUTBOUND_PCIS;
3754 init_data.input_sbal_addr_array = (void **) in_sbal_ptrs;
3755 init_data.output_sbal_addr_array = (void **) out_sbal_ptrs;
3756
3757 if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ALLOCATED,
3758 QETH_QDIO_ESTABLISHED) == QETH_QDIO_ALLOCATED) {
3759 rc = qdio_initialize(&init_data);
3760 if (rc)
3761 atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
3762 }
3763 kfree(out_sbal_ptrs);
3764 kfree(in_sbal_ptrs);
3765 kfree(qib_param_field);
3766 return rc;
3767 }
3768
qeth_core_free_card(struct qeth_card * card)3769 static void qeth_core_free_card(struct qeth_card *card)
3770 {
3771
3772 QETH_DBF_TEXT(SETUP, 2, "freecrd");
3773 QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
3774 qeth_clean_channel(&card->read);
3775 qeth_clean_channel(&card->write);
3776 if (card->dev)
3777 free_netdev(card->dev);
3778 kfree(card->ip_tbd_list);
3779 qeth_free_qdio_buffers(card);
3780 unregister_service_level(&card->qeth_service_level);
3781 kfree(card);
3782 }
3783
3784 static struct ccw_device_id qeth_ids[] = {
3785 {CCW_DEVICE(0x1731, 0x01), .driver_info = QETH_CARD_TYPE_OSAE},
3786 {CCW_DEVICE(0x1731, 0x05), .driver_info = QETH_CARD_TYPE_IQD},
3787 {CCW_DEVICE(0x1731, 0x06), .driver_info = QETH_CARD_TYPE_OSN},
3788 {},
3789 };
3790 MODULE_DEVICE_TABLE(ccw, qeth_ids);
3791
3792 static struct ccw_driver qeth_ccw_driver = {
3793 .name = "qeth",
3794 .ids = qeth_ids,
3795 .probe = ccwgroup_probe_ccwdev,
3796 .remove = ccwgroup_remove_ccwdev,
3797 };
3798
qeth_core_driver_group(const char * buf,struct device * root_dev,unsigned long driver_id)3799 static int qeth_core_driver_group(const char *buf, struct device *root_dev,
3800 unsigned long driver_id)
3801 {
3802 return ccwgroup_create_from_string(root_dev, driver_id,
3803 &qeth_ccw_driver, 3, buf);
3804 }
3805
qeth_core_hardsetup_card(struct qeth_card * card)3806 int qeth_core_hardsetup_card(struct qeth_card *card)
3807 {
3808 struct qdio_ssqd_desc *ssqd;
3809 int retries = 3;
3810 int mpno = 0;
3811 int rc;
3812
3813 QETH_DBF_TEXT(SETUP, 2, "hrdsetup");
3814 atomic_set(&card->force_alloc_skb, 0);
3815 retry:
3816 if (retries < 3) {
3817 QETH_DBF_MESSAGE(2, "%s Retrying to do IDX activates.\n",
3818 dev_name(&card->gdev->dev));
3819 ccw_device_set_offline(CARD_DDEV(card));
3820 ccw_device_set_offline(CARD_WDEV(card));
3821 ccw_device_set_offline(CARD_RDEV(card));
3822 ccw_device_set_online(CARD_RDEV(card));
3823 ccw_device_set_online(CARD_WDEV(card));
3824 ccw_device_set_online(CARD_DDEV(card));
3825 }
3826 rc = qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
3827 if (rc == -ERESTARTSYS) {
3828 QETH_DBF_TEXT(SETUP, 2, "break1");
3829 return rc;
3830 } else if (rc) {
3831 QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
3832 if (--retries < 0)
3833 goto out;
3834 else
3835 goto retry;
3836 }
3837
3838 rc = qeth_get_unitaddr(card);
3839 if (rc) {
3840 QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
3841 return rc;
3842 }
3843
3844 ssqd = kmalloc(sizeof(struct qdio_ssqd_desc), GFP_KERNEL);
3845 if (!ssqd) {
3846 rc = -ENOMEM;
3847 goto out;
3848 }
3849 rc = qdio_get_ssqd_desc(CARD_DDEV(card), ssqd);
3850 if (rc == 0)
3851 mpno = ssqd->pcnt;
3852 kfree(ssqd);
3853
3854 if (mpno)
3855 mpno = min(mpno - 1, QETH_MAX_PORTNO);
3856 if (card->info.portno > mpno) {
3857 QETH_DBF_MESSAGE(2, "Device %s does not offer port number %d"
3858 "\n.", CARD_BUS_ID(card), card->info.portno);
3859 rc = -ENODEV;
3860 goto out;
3861 }
3862 qeth_init_tokens(card);
3863 qeth_init_func_level(card);
3864 rc = qeth_idx_activate_channel(&card->read, qeth_idx_read_cb);
3865 if (rc == -ERESTARTSYS) {
3866 QETH_DBF_TEXT(SETUP, 2, "break2");
3867 return rc;
3868 } else if (rc) {
3869 QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
3870 if (--retries < 0)
3871 goto out;
3872 else
3873 goto retry;
3874 }
3875 rc = qeth_idx_activate_channel(&card->write, qeth_idx_write_cb);
3876 if (rc == -ERESTARTSYS) {
3877 QETH_DBF_TEXT(SETUP, 2, "break3");
3878 return rc;
3879 } else if (rc) {
3880 QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
3881 if (--retries < 0)
3882 goto out;
3883 else
3884 goto retry;
3885 }
3886 rc = qeth_mpc_initialize(card);
3887 if (rc) {
3888 QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
3889 goto out;
3890 }
3891 return 0;
3892 out:
3893 dev_warn(&card->gdev->dev, "The qeth device driver failed to recover "
3894 "an error on the device\n");
3895 QETH_DBF_MESSAGE(2, "%s Initialization in hardsetup failed! rc=%d\n",
3896 dev_name(&card->gdev->dev), rc);
3897 return rc;
3898 }
3899 EXPORT_SYMBOL_GPL(qeth_core_hardsetup_card);
3900
qeth_create_skb_frag(struct qdio_buffer_element * element,struct sk_buff ** pskb,int offset,int * pfrag,int data_len)3901 static inline int qeth_create_skb_frag(struct qdio_buffer_element *element,
3902 struct sk_buff **pskb, int offset, int *pfrag, int data_len)
3903 {
3904 struct page *page = virt_to_page(element->addr);
3905 if (*pskb == NULL) {
3906 /* the upper protocol layers assume that there is data in the
3907 * skb itself. Copy a small amount (64 bytes) to make them
3908 * happy. */
3909 *pskb = dev_alloc_skb(64 + ETH_HLEN);
3910 if (!(*pskb))
3911 return -ENOMEM;
3912 skb_reserve(*pskb, ETH_HLEN);
3913 if (data_len <= 64) {
3914 memcpy(skb_put(*pskb, data_len), element->addr + offset,
3915 data_len);
3916 } else {
3917 get_page(page);
3918 memcpy(skb_put(*pskb, 64), element->addr + offset, 64);
3919 skb_fill_page_desc(*pskb, *pfrag, page, offset + 64,
3920 data_len - 64);
3921 (*pskb)->data_len += data_len - 64;
3922 (*pskb)->len += data_len - 64;
3923 (*pskb)->truesize += data_len - 64;
3924 (*pfrag)++;
3925 }
3926 } else {
3927 get_page(page);
3928 skb_fill_page_desc(*pskb, *pfrag, page, offset, data_len);
3929 (*pskb)->data_len += data_len;
3930 (*pskb)->len += data_len;
3931 (*pskb)->truesize += data_len;
3932 (*pfrag)++;
3933 }
3934 return 0;
3935 }
3936
qeth_core_get_next_skb(struct qeth_card * card,struct qdio_buffer * buffer,struct qdio_buffer_element ** __element,int * __offset,struct qeth_hdr ** hdr)3937 struct sk_buff *qeth_core_get_next_skb(struct qeth_card *card,
3938 struct qdio_buffer *buffer,
3939 struct qdio_buffer_element **__element, int *__offset,
3940 struct qeth_hdr **hdr)
3941 {
3942 struct qdio_buffer_element *element = *__element;
3943 int offset = *__offset;
3944 struct sk_buff *skb = NULL;
3945 int skb_len;
3946 void *data_ptr;
3947 int data_len;
3948 int headroom = 0;
3949 int use_rx_sg = 0;
3950 int frag = 0;
3951
3952 /* qeth_hdr must not cross element boundaries */
3953 if (element->length < offset + sizeof(struct qeth_hdr)) {
3954 if (qeth_is_last_sbale(element))
3955 return NULL;
3956 element++;
3957 offset = 0;
3958 if (element->length < sizeof(struct qeth_hdr))
3959 return NULL;
3960 }
3961 *hdr = element->addr + offset;
3962
3963 offset += sizeof(struct qeth_hdr);
3964 if (card->options.layer2) {
3965 if (card->info.type == QETH_CARD_TYPE_OSN) {
3966 skb_len = (*hdr)->hdr.osn.pdu_length;
3967 headroom = sizeof(struct qeth_hdr);
3968 } else {
3969 skb_len = (*hdr)->hdr.l2.pkt_length;
3970 }
3971 } else {
3972 skb_len = (*hdr)->hdr.l3.length;
3973 if ((card->info.link_type == QETH_LINK_TYPE_LANE_TR) ||
3974 (card->info.link_type == QETH_LINK_TYPE_HSTR))
3975 headroom = TR_HLEN;
3976 else
3977 headroom = ETH_HLEN;
3978 }
3979
3980 if (!skb_len)
3981 return NULL;
3982
3983 if ((skb_len >= card->options.rx_sg_cb) &&
3984 (!(card->info.type == QETH_CARD_TYPE_OSN)) &&
3985 (!atomic_read(&card->force_alloc_skb))) {
3986 use_rx_sg = 1;
3987 } else {
3988 skb = dev_alloc_skb(skb_len + headroom);
3989 if (!skb)
3990 goto no_mem;
3991 if (headroom)
3992 skb_reserve(skb, headroom);
3993 }
3994
3995 data_ptr = element->addr + offset;
3996 while (skb_len) {
3997 data_len = min(skb_len, (int)(element->length - offset));
3998 if (data_len) {
3999 if (use_rx_sg) {
4000 if (qeth_create_skb_frag(element, &skb, offset,
4001 &frag, data_len))
4002 goto no_mem;
4003 } else {
4004 memcpy(skb_put(skb, data_len), data_ptr,
4005 data_len);
4006 }
4007 }
4008 skb_len -= data_len;
4009 if (skb_len) {
4010 if (qeth_is_last_sbale(element)) {
4011 QETH_DBF_TEXT(TRACE, 4, "unexeob");
4012 QETH_DBF_TEXT_(TRACE, 4, "%s",
4013 CARD_BUS_ID(card));
4014 QETH_DBF_TEXT(QERR, 2, "unexeob");
4015 QETH_DBF_TEXT_(QERR, 2, "%s",
4016 CARD_BUS_ID(card));
4017 QETH_DBF_HEX(MISC, 4, buffer, sizeof(*buffer));
4018 dev_kfree_skb_any(skb);
4019 card->stats.rx_errors++;
4020 return NULL;
4021 }
4022 element++;
4023 offset = 0;
4024 data_ptr = element->addr;
4025 } else {
4026 offset += data_len;
4027 }
4028 }
4029 *__element = element;
4030 *__offset = offset;
4031 if (use_rx_sg && card->options.performance_stats) {
4032 card->perf_stats.sg_skbs_rx++;
4033 card->perf_stats.sg_frags_rx += skb_shinfo(skb)->nr_frags;
4034 }
4035 return skb;
4036 no_mem:
4037 if (net_ratelimit()) {
4038 QETH_DBF_TEXT(TRACE, 2, "noskbmem");
4039 QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
4040 }
4041 card->stats.rx_dropped++;
4042 return NULL;
4043 }
4044 EXPORT_SYMBOL_GPL(qeth_core_get_next_skb);
4045
qeth_unregister_dbf_views(void)4046 static void qeth_unregister_dbf_views(void)
4047 {
4048 int x;
4049 for (x = 0; x < QETH_DBF_INFOS; x++) {
4050 debug_unregister(qeth_dbf[x].id);
4051 qeth_dbf[x].id = NULL;
4052 }
4053 }
4054
qeth_dbf_longtext(enum qeth_dbf_names dbf_nix,int level,char * fmt,...)4055 void qeth_dbf_longtext(enum qeth_dbf_names dbf_nix, int level, char *fmt, ...)
4056 {
4057 char dbf_txt_buf[32];
4058 va_list args;
4059
4060 if (level > (qeth_dbf[dbf_nix].id)->level)
4061 return;
4062 va_start(args, fmt);
4063 vsnprintf(dbf_txt_buf, sizeof(dbf_txt_buf), fmt, args);
4064 va_end(args);
4065 debug_text_event(qeth_dbf[dbf_nix].id, level, dbf_txt_buf);
4066 }
4067 EXPORT_SYMBOL_GPL(qeth_dbf_longtext);
4068
qeth_register_dbf_views(void)4069 static int qeth_register_dbf_views(void)
4070 {
4071 int ret;
4072 int x;
4073
4074 for (x = 0; x < QETH_DBF_INFOS; x++) {
4075 /* register the areas */
4076 qeth_dbf[x].id = debug_register(qeth_dbf[x].name,
4077 qeth_dbf[x].pages,
4078 qeth_dbf[x].areas,
4079 qeth_dbf[x].len);
4080 if (qeth_dbf[x].id == NULL) {
4081 qeth_unregister_dbf_views();
4082 return -ENOMEM;
4083 }
4084
4085 /* register a view */
4086 ret = debug_register_view(qeth_dbf[x].id, qeth_dbf[x].view);
4087 if (ret) {
4088 qeth_unregister_dbf_views();
4089 return ret;
4090 }
4091
4092 /* set a passing level */
4093 debug_set_level(qeth_dbf[x].id, qeth_dbf[x].level);
4094 }
4095
4096 return 0;
4097 }
4098
qeth_core_load_discipline(struct qeth_card * card,enum qeth_discipline_id discipline)4099 int qeth_core_load_discipline(struct qeth_card *card,
4100 enum qeth_discipline_id discipline)
4101 {
4102 int rc = 0;
4103 switch (discipline) {
4104 case QETH_DISCIPLINE_LAYER3:
4105 card->discipline.ccwgdriver = try_then_request_module(
4106 symbol_get(qeth_l3_ccwgroup_driver),
4107 "qeth_l3");
4108 break;
4109 case QETH_DISCIPLINE_LAYER2:
4110 card->discipline.ccwgdriver = try_then_request_module(
4111 symbol_get(qeth_l2_ccwgroup_driver),
4112 "qeth_l2");
4113 break;
4114 }
4115 if (!card->discipline.ccwgdriver) {
4116 dev_err(&card->gdev->dev, "There is no kernel module to "
4117 "support discipline %d\n", discipline);
4118 rc = -EINVAL;
4119 }
4120 return rc;
4121 }
4122
qeth_core_free_discipline(struct qeth_card * card)4123 void qeth_core_free_discipline(struct qeth_card *card)
4124 {
4125 if (card->options.layer2)
4126 symbol_put(qeth_l2_ccwgroup_driver);
4127 else
4128 symbol_put(qeth_l3_ccwgroup_driver);
4129 card->discipline.ccwgdriver = NULL;
4130 }
4131
qeth_core_probe_device(struct ccwgroup_device * gdev)4132 static int qeth_core_probe_device(struct ccwgroup_device *gdev)
4133 {
4134 struct qeth_card *card;
4135 struct device *dev;
4136 int rc;
4137 unsigned long flags;
4138
4139 QETH_DBF_TEXT(SETUP, 2, "probedev");
4140
4141 dev = &gdev->dev;
4142 if (!get_device(dev))
4143 return -ENODEV;
4144
4145 QETH_DBF_TEXT_(SETUP, 2, "%s", dev_name(&gdev->dev));
4146
4147 card = qeth_alloc_card();
4148 if (!card) {
4149 QETH_DBF_TEXT_(SETUP, 2, "1err%d", -ENOMEM);
4150 rc = -ENOMEM;
4151 goto err_dev;
4152 }
4153 card->read.ccwdev = gdev->cdev[0];
4154 card->write.ccwdev = gdev->cdev[1];
4155 card->data.ccwdev = gdev->cdev[2];
4156 dev_set_drvdata(&gdev->dev, card);
4157 card->gdev = gdev;
4158 gdev->cdev[0]->handler = qeth_irq;
4159 gdev->cdev[1]->handler = qeth_irq;
4160 gdev->cdev[2]->handler = qeth_irq;
4161
4162 rc = qeth_determine_card_type(card);
4163 if (rc) {
4164 QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
4165 goto err_card;
4166 }
4167 rc = qeth_setup_card(card);
4168 if (rc) {
4169 QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
4170 goto err_card;
4171 }
4172
4173 if (card->info.type == QETH_CARD_TYPE_OSN) {
4174 rc = qeth_core_create_osn_attributes(dev);
4175 if (rc)
4176 goto err_card;
4177 rc = qeth_core_load_discipline(card, QETH_DISCIPLINE_LAYER2);
4178 if (rc) {
4179 qeth_core_remove_osn_attributes(dev);
4180 goto err_card;
4181 }
4182 rc = card->discipline.ccwgdriver->probe(card->gdev);
4183 if (rc) {
4184 qeth_core_free_discipline(card);
4185 qeth_core_remove_osn_attributes(dev);
4186 goto err_card;
4187 }
4188 } else {
4189 rc = qeth_core_create_device_attributes(dev);
4190 if (rc)
4191 goto err_card;
4192 }
4193
4194 write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
4195 list_add_tail(&card->list, &qeth_core_card_list.list);
4196 write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
4197 return 0;
4198
4199 err_card:
4200 qeth_core_free_card(card);
4201 err_dev:
4202 put_device(dev);
4203 return rc;
4204 }
4205
qeth_core_remove_device(struct ccwgroup_device * gdev)4206 static void qeth_core_remove_device(struct ccwgroup_device *gdev)
4207 {
4208 unsigned long flags;
4209 struct qeth_card *card = dev_get_drvdata(&gdev->dev);
4210
4211 QETH_DBF_TEXT(SETUP, 2, "removedv");
4212 if (card->discipline.ccwgdriver) {
4213 card->discipline.ccwgdriver->remove(gdev);
4214 qeth_core_free_discipline(card);
4215 }
4216
4217 if (card->info.type == QETH_CARD_TYPE_OSN) {
4218 qeth_core_remove_osn_attributes(&gdev->dev);
4219 } else {
4220 qeth_core_remove_device_attributes(&gdev->dev);
4221 }
4222 write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
4223 list_del(&card->list);
4224 write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
4225 qeth_core_free_card(card);
4226 dev_set_drvdata(&gdev->dev, NULL);
4227 put_device(&gdev->dev);
4228 return;
4229 }
4230
qeth_core_set_online(struct ccwgroup_device * gdev)4231 static int qeth_core_set_online(struct ccwgroup_device *gdev)
4232 {
4233 struct qeth_card *card = dev_get_drvdata(&gdev->dev);
4234 int rc = 0;
4235 int def_discipline;
4236
4237 if (!card->discipline.ccwgdriver) {
4238 if (card->info.type == QETH_CARD_TYPE_IQD)
4239 def_discipline = QETH_DISCIPLINE_LAYER3;
4240 else
4241 def_discipline = QETH_DISCIPLINE_LAYER2;
4242 rc = qeth_core_load_discipline(card, def_discipline);
4243 if (rc)
4244 goto err;
4245 rc = card->discipline.ccwgdriver->probe(card->gdev);
4246 if (rc)
4247 goto err;
4248 }
4249 rc = card->discipline.ccwgdriver->set_online(gdev);
4250 err:
4251 return rc;
4252 }
4253
qeth_core_set_offline(struct ccwgroup_device * gdev)4254 static int qeth_core_set_offline(struct ccwgroup_device *gdev)
4255 {
4256 struct qeth_card *card = dev_get_drvdata(&gdev->dev);
4257 return card->discipline.ccwgdriver->set_offline(gdev);
4258 }
4259
qeth_core_shutdown(struct ccwgroup_device * gdev)4260 static void qeth_core_shutdown(struct ccwgroup_device *gdev)
4261 {
4262 struct qeth_card *card = dev_get_drvdata(&gdev->dev);
4263 if (card->discipline.ccwgdriver &&
4264 card->discipline.ccwgdriver->shutdown)
4265 card->discipline.ccwgdriver->shutdown(gdev);
4266 }
4267
4268 static struct ccwgroup_driver qeth_core_ccwgroup_driver = {
4269 .owner = THIS_MODULE,
4270 .name = "qeth",
4271 .driver_id = 0xD8C5E3C8,
4272 .probe = qeth_core_probe_device,
4273 .remove = qeth_core_remove_device,
4274 .set_online = qeth_core_set_online,
4275 .set_offline = qeth_core_set_offline,
4276 .shutdown = qeth_core_shutdown,
4277 };
4278
4279 static ssize_t
qeth_core_driver_group_store(struct device_driver * ddrv,const char * buf,size_t count)4280 qeth_core_driver_group_store(struct device_driver *ddrv, const char *buf,
4281 size_t count)
4282 {
4283 int err;
4284 err = qeth_core_driver_group(buf, qeth_core_root_dev,
4285 qeth_core_ccwgroup_driver.driver_id);
4286 if (err)
4287 return err;
4288 else
4289 return count;
4290 }
4291
4292 static DRIVER_ATTR(group, 0200, NULL, qeth_core_driver_group_store);
4293
4294 static struct {
4295 const char str[ETH_GSTRING_LEN];
4296 } qeth_ethtool_stats_keys[] = {
4297 /* 0 */{"rx skbs"},
4298 {"rx buffers"},
4299 {"tx skbs"},
4300 {"tx buffers"},
4301 {"tx skbs no packing"},
4302 {"tx buffers no packing"},
4303 {"tx skbs packing"},
4304 {"tx buffers packing"},
4305 {"tx sg skbs"},
4306 {"tx sg frags"},
4307 /* 10 */{"rx sg skbs"},
4308 {"rx sg frags"},
4309 {"rx sg page allocs"},
4310 {"tx large kbytes"},
4311 {"tx large count"},
4312 {"tx pk state ch n->p"},
4313 {"tx pk state ch p->n"},
4314 {"tx pk watermark low"},
4315 {"tx pk watermark high"},
4316 {"queue 0 buffer usage"},
4317 /* 20 */{"queue 1 buffer usage"},
4318 {"queue 2 buffer usage"},
4319 {"queue 3 buffer usage"},
4320 {"rx handler time"},
4321 {"rx handler count"},
4322 {"rx do_QDIO time"},
4323 {"rx do_QDIO count"},
4324 {"tx handler time"},
4325 {"tx handler count"},
4326 {"tx time"},
4327 /* 30 */{"tx count"},
4328 {"tx do_QDIO time"},
4329 {"tx do_QDIO count"},
4330 };
4331
qeth_core_get_stats_count(struct net_device * dev)4332 int qeth_core_get_stats_count(struct net_device *dev)
4333 {
4334 return (sizeof(qeth_ethtool_stats_keys) / ETH_GSTRING_LEN);
4335 }
4336 EXPORT_SYMBOL_GPL(qeth_core_get_stats_count);
4337
qeth_core_get_ethtool_stats(struct net_device * dev,struct ethtool_stats * stats,u64 * data)4338 void qeth_core_get_ethtool_stats(struct net_device *dev,
4339 struct ethtool_stats *stats, u64 *data)
4340 {
4341 struct qeth_card *card = dev->ml_priv;
4342 data[0] = card->stats.rx_packets -
4343 card->perf_stats.initial_rx_packets;
4344 data[1] = card->perf_stats.bufs_rec;
4345 data[2] = card->stats.tx_packets -
4346 card->perf_stats.initial_tx_packets;
4347 data[3] = card->perf_stats.bufs_sent;
4348 data[4] = card->stats.tx_packets - card->perf_stats.initial_tx_packets
4349 - card->perf_stats.skbs_sent_pack;
4350 data[5] = card->perf_stats.bufs_sent - card->perf_stats.bufs_sent_pack;
4351 data[6] = card->perf_stats.skbs_sent_pack;
4352 data[7] = card->perf_stats.bufs_sent_pack;
4353 data[8] = card->perf_stats.sg_skbs_sent;
4354 data[9] = card->perf_stats.sg_frags_sent;
4355 data[10] = card->perf_stats.sg_skbs_rx;
4356 data[11] = card->perf_stats.sg_frags_rx;
4357 data[12] = card->perf_stats.sg_alloc_page_rx;
4358 data[13] = (card->perf_stats.large_send_bytes >> 10);
4359 data[14] = card->perf_stats.large_send_cnt;
4360 data[15] = card->perf_stats.sc_dp_p;
4361 data[16] = card->perf_stats.sc_p_dp;
4362 data[17] = QETH_LOW_WATERMARK_PACK;
4363 data[18] = QETH_HIGH_WATERMARK_PACK;
4364 data[19] = atomic_read(&card->qdio.out_qs[0]->used_buffers);
4365 data[20] = (card->qdio.no_out_queues > 1) ?
4366 atomic_read(&card->qdio.out_qs[1]->used_buffers) : 0;
4367 data[21] = (card->qdio.no_out_queues > 2) ?
4368 atomic_read(&card->qdio.out_qs[2]->used_buffers) : 0;
4369 data[22] = (card->qdio.no_out_queues > 3) ?
4370 atomic_read(&card->qdio.out_qs[3]->used_buffers) : 0;
4371 data[23] = card->perf_stats.inbound_time;
4372 data[24] = card->perf_stats.inbound_cnt;
4373 data[25] = card->perf_stats.inbound_do_qdio_time;
4374 data[26] = card->perf_stats.inbound_do_qdio_cnt;
4375 data[27] = card->perf_stats.outbound_handler_time;
4376 data[28] = card->perf_stats.outbound_handler_cnt;
4377 data[29] = card->perf_stats.outbound_time;
4378 data[30] = card->perf_stats.outbound_cnt;
4379 data[31] = card->perf_stats.outbound_do_qdio_time;
4380 data[32] = card->perf_stats.outbound_do_qdio_cnt;
4381 }
4382 EXPORT_SYMBOL_GPL(qeth_core_get_ethtool_stats);
4383
qeth_core_get_strings(struct net_device * dev,u32 stringset,u8 * data)4384 void qeth_core_get_strings(struct net_device *dev, u32 stringset, u8 *data)
4385 {
4386 switch (stringset) {
4387 case ETH_SS_STATS:
4388 memcpy(data, &qeth_ethtool_stats_keys,
4389 sizeof(qeth_ethtool_stats_keys));
4390 break;
4391 default:
4392 WARN_ON(1);
4393 break;
4394 }
4395 }
4396 EXPORT_SYMBOL_GPL(qeth_core_get_strings);
4397
qeth_core_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * info)4398 void qeth_core_get_drvinfo(struct net_device *dev,
4399 struct ethtool_drvinfo *info)
4400 {
4401 struct qeth_card *card = dev->ml_priv;
4402 if (card->options.layer2)
4403 strcpy(info->driver, "qeth_l2");
4404 else
4405 strcpy(info->driver, "qeth_l3");
4406
4407 strcpy(info->version, "1.0");
4408 strcpy(info->fw_version, card->info.mcl_level);
4409 sprintf(info->bus_info, "%s/%s/%s",
4410 CARD_RDEV_ID(card),
4411 CARD_WDEV_ID(card),
4412 CARD_DDEV_ID(card));
4413 }
4414 EXPORT_SYMBOL_GPL(qeth_core_get_drvinfo);
4415
qeth_core_ethtool_get_settings(struct net_device * netdev,struct ethtool_cmd * ecmd)4416 int qeth_core_ethtool_get_settings(struct net_device *netdev,
4417 struct ethtool_cmd *ecmd)
4418 {
4419 struct qeth_card *card = netdev->ml_priv;
4420 enum qeth_link_types link_type;
4421
4422 if ((card->info.type == QETH_CARD_TYPE_IQD) || (card->info.guestlan))
4423 link_type = QETH_LINK_TYPE_10GBIT_ETH;
4424 else
4425 link_type = card->info.link_type;
4426
4427 ecmd->transceiver = XCVR_INTERNAL;
4428 ecmd->supported = SUPPORTED_Autoneg;
4429 ecmd->advertising = ADVERTISED_Autoneg;
4430 ecmd->duplex = DUPLEX_FULL;
4431 ecmd->autoneg = AUTONEG_ENABLE;
4432
4433 switch (link_type) {
4434 case QETH_LINK_TYPE_FAST_ETH:
4435 case QETH_LINK_TYPE_LANE_ETH100:
4436 ecmd->supported |= SUPPORTED_10baseT_Half |
4437 SUPPORTED_10baseT_Full |
4438 SUPPORTED_100baseT_Half |
4439 SUPPORTED_100baseT_Full |
4440 SUPPORTED_TP;
4441 ecmd->advertising |= ADVERTISED_10baseT_Half |
4442 ADVERTISED_10baseT_Full |
4443 ADVERTISED_100baseT_Half |
4444 ADVERTISED_100baseT_Full |
4445 ADVERTISED_TP;
4446 ecmd->speed = SPEED_100;
4447 ecmd->port = PORT_TP;
4448 break;
4449
4450 case QETH_LINK_TYPE_GBIT_ETH:
4451 case QETH_LINK_TYPE_LANE_ETH1000:
4452 ecmd->supported |= SUPPORTED_10baseT_Half |
4453 SUPPORTED_10baseT_Full |
4454 SUPPORTED_100baseT_Half |
4455 SUPPORTED_100baseT_Full |
4456 SUPPORTED_1000baseT_Half |
4457 SUPPORTED_1000baseT_Full |
4458 SUPPORTED_FIBRE;
4459 ecmd->advertising |= ADVERTISED_10baseT_Half |
4460 ADVERTISED_10baseT_Full |
4461 ADVERTISED_100baseT_Half |
4462 ADVERTISED_100baseT_Full |
4463 ADVERTISED_1000baseT_Half |
4464 ADVERTISED_1000baseT_Full |
4465 ADVERTISED_FIBRE;
4466 ecmd->speed = SPEED_1000;
4467 ecmd->port = PORT_FIBRE;
4468 break;
4469
4470 case QETH_LINK_TYPE_10GBIT_ETH:
4471 ecmd->supported |= SUPPORTED_10baseT_Half |
4472 SUPPORTED_10baseT_Full |
4473 SUPPORTED_100baseT_Half |
4474 SUPPORTED_100baseT_Full |
4475 SUPPORTED_1000baseT_Half |
4476 SUPPORTED_1000baseT_Full |
4477 SUPPORTED_10000baseT_Full |
4478 SUPPORTED_FIBRE;
4479 ecmd->advertising |= ADVERTISED_10baseT_Half |
4480 ADVERTISED_10baseT_Full |
4481 ADVERTISED_100baseT_Half |
4482 ADVERTISED_100baseT_Full |
4483 ADVERTISED_1000baseT_Half |
4484 ADVERTISED_1000baseT_Full |
4485 ADVERTISED_10000baseT_Full |
4486 ADVERTISED_FIBRE;
4487 ecmd->speed = SPEED_10000;
4488 ecmd->port = PORT_FIBRE;
4489 break;
4490
4491 default:
4492 ecmd->supported |= SUPPORTED_10baseT_Half |
4493 SUPPORTED_10baseT_Full |
4494 SUPPORTED_TP;
4495 ecmd->advertising |= ADVERTISED_10baseT_Half |
4496 ADVERTISED_10baseT_Full |
4497 ADVERTISED_TP;
4498 ecmd->speed = SPEED_10;
4499 ecmd->port = PORT_TP;
4500 }
4501
4502 return 0;
4503 }
4504 EXPORT_SYMBOL_GPL(qeth_core_ethtool_get_settings);
4505
qeth_core_init(void)4506 static int __init qeth_core_init(void)
4507 {
4508 int rc;
4509
4510 pr_info("loading core functions\n");
4511 INIT_LIST_HEAD(&qeth_core_card_list.list);
4512 rwlock_init(&qeth_core_card_list.rwlock);
4513
4514 rc = qeth_register_dbf_views();
4515 if (rc)
4516 goto out_err;
4517 rc = ccw_driver_register(&qeth_ccw_driver);
4518 if (rc)
4519 goto ccw_err;
4520 rc = ccwgroup_driver_register(&qeth_core_ccwgroup_driver);
4521 if (rc)
4522 goto ccwgroup_err;
4523 rc = driver_create_file(&qeth_core_ccwgroup_driver.driver,
4524 &driver_attr_group);
4525 if (rc)
4526 goto driver_err;
4527 qeth_core_root_dev = root_device_register("qeth");
4528 rc = IS_ERR(qeth_core_root_dev) ? PTR_ERR(qeth_core_root_dev) : 0;
4529 if (rc)
4530 goto register_err;
4531
4532 qeth_core_header_cache = kmem_cache_create("qeth_hdr",
4533 sizeof(struct qeth_hdr) + ETH_HLEN, 64, 0, NULL);
4534 if (!qeth_core_header_cache) {
4535 rc = -ENOMEM;
4536 goto slab_err;
4537 }
4538
4539 return 0;
4540 slab_err:
4541 root_device_unregister(qeth_core_root_dev);
4542 register_err:
4543 driver_remove_file(&qeth_core_ccwgroup_driver.driver,
4544 &driver_attr_group);
4545 driver_err:
4546 ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
4547 ccwgroup_err:
4548 ccw_driver_unregister(&qeth_ccw_driver);
4549 ccw_err:
4550 QETH_DBF_MESSAGE(2, "Initialization failed with code %d\n", rc);
4551 qeth_unregister_dbf_views();
4552 out_err:
4553 pr_err("Initializing the qeth device driver failed\n");
4554 return rc;
4555 }
4556
qeth_core_exit(void)4557 static void __exit qeth_core_exit(void)
4558 {
4559 root_device_unregister(qeth_core_root_dev);
4560 driver_remove_file(&qeth_core_ccwgroup_driver.driver,
4561 &driver_attr_group);
4562 ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
4563 ccw_driver_unregister(&qeth_ccw_driver);
4564 kmem_cache_destroy(qeth_core_header_cache);
4565 qeth_unregister_dbf_views();
4566 pr_info("core functions removed\n");
4567 }
4568
4569 module_init(qeth_core_init);
4570 module_exit(qeth_core_exit);
4571 MODULE_AUTHOR("Frank Blaschka <frank.blaschka@de.ibm.com>");
4572 MODULE_DESCRIPTION("qeth core functions");
4573 MODULE_LICENSE("GPL");
4574