1 /* linux/arch/arm/plat-s3c24xx/include/plat/pll.h 2 * 3 * Copyright 2008 Simtec Electronics 4 * Ben Dooks <ben@simtec.co.uk> 5 * http://armlinux.simtec.co.uk/ 6 * 7 * S3C24xx - common pll registers and code 8 */ 9 10 #define S3C24XX_PLLCON_MDIVSHIFT 12 11 #define S3C24XX_PLLCON_PDIVSHIFT 4 12 #define S3C24XX_PLLCON_SDIVSHIFT 0 13 #define S3C24XX_PLLCON_MDIVMASK ((1<<(1+(19-12)))-1) 14 #define S3C24XX_PLLCON_PDIVMASK ((1<<5)-1) 15 #define S3C24XX_PLLCON_SDIVMASK 3 16 17 #include <asm/div64.h> 18 19 static inline unsigned int s3c24xx_get_pll(unsigned int pllval,unsigned int baseclk)20s3c24xx_get_pll(unsigned int pllval, unsigned int baseclk) 21 { 22 unsigned int mdiv, pdiv, sdiv; 23 uint64_t fvco; 24 25 mdiv = pllval >> S3C24XX_PLLCON_MDIVSHIFT; 26 pdiv = pllval >> S3C24XX_PLLCON_PDIVSHIFT; 27 sdiv = pllval >> S3C24XX_PLLCON_SDIVSHIFT; 28 29 mdiv &= S3C24XX_PLLCON_MDIVMASK; 30 pdiv &= S3C24XX_PLLCON_PDIVMASK; 31 sdiv &= S3C24XX_PLLCON_SDIVMASK; 32 33 fvco = (uint64_t)baseclk * (mdiv + 8); 34 do_div(fvco, (pdiv + 2) << sdiv); 35 36 return (unsigned int)fvco; 37 } 38