1 /*
2 * TX4938/4937 setup routines
3 * Based on linux/arch/mips/txx9/rbtx4938/setup.c,
4 * and RBTX49xx patch from CELF patch archive.
5 *
6 * 2003-2005 (c) MontaVista Software, Inc.
7 * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13 #include <linux/init.h>
14 #include <linux/ioport.h>
15 #include <linux/delay.h>
16 #include <linux/param.h>
17 #include <linux/ptrace.h>
18 #include <linux/mtd/physmap.h>
19 #include <linux/platform_device.h>
20 #include <asm/reboot.h>
21 #include <asm/traps.h>
22 #include <asm/txx9irq.h>
23 #include <asm/txx9tmr.h>
24 #include <asm/txx9pio.h>
25 #include <asm/txx9/generic.h>
26 #include <asm/txx9/tx4938.h>
27
tx4938_wdr_init(void)28 static void __init tx4938_wdr_init(void)
29 {
30 /* report watchdog reset status */
31 if (____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_WDRST)
32 pr_warning("Watchdog reset detected at 0x%lx\n",
33 read_c0_errorepc());
34 /* clear WatchDogReset (W1C) */
35 tx4938_ccfg_set(TX4938_CCFG_WDRST);
36 /* do reset on watchdog */
37 tx4938_ccfg_set(TX4938_CCFG_WR);
38 }
39
tx4938_wdt_init(void)40 void __init tx4938_wdt_init(void)
41 {
42 txx9_wdt_init(TX4938_TMR_REG(2) & 0xfffffffffULL);
43 }
44
tx4938_machine_restart(char * command)45 static void tx4938_machine_restart(char *command)
46 {
47 local_irq_disable();
48 pr_emerg("Rebooting (with %s watchdog reset)...\n",
49 (____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_WDREXEN) ?
50 "external" : "internal");
51 /* clear watchdog status */
52 tx4938_ccfg_set(TX4938_CCFG_WDRST); /* W1C */
53 txx9_wdt_now(TX4938_TMR_REG(2) & 0xfffffffffULL);
54 while (!(____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_WDRST))
55 ;
56 mdelay(10);
57 if (____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_WDREXEN) {
58 pr_emerg("Rebooting (with internal watchdog reset)...\n");
59 /* External WDRST failed. Do internal watchdog reset */
60 tx4938_ccfg_clear(TX4938_CCFG_WDREXEN);
61 }
62 /* fallback */
63 (*_machine_halt)();
64 }
65
66 void show_registers(struct pt_regs *regs);
tx4938_be_handler(struct pt_regs * regs,int is_fixup)67 static int tx4938_be_handler(struct pt_regs *regs, int is_fixup)
68 {
69 int data = regs->cp0_cause & 4;
70 console_verbose();
71 pr_err("%cBE exception at %#lx\n", data ? 'D' : 'I', regs->cp0_epc);
72 pr_err("ccfg:%llx, toea:%llx\n",
73 (unsigned long long)____raw_readq(&tx4938_ccfgptr->ccfg),
74 (unsigned long long)____raw_readq(&tx4938_ccfgptr->toea));
75 #ifdef CONFIG_PCI
76 tx4927_report_pcic_status();
77 #endif
78 show_registers(regs);
79 panic("BusError!");
80 }
tx4938_be_init(void)81 static void __init tx4938_be_init(void)
82 {
83 board_be_handler = tx4938_be_handler;
84 }
85
86 static struct resource tx4938_sdram_resource[4];
87 static struct resource tx4938_sram_resource;
88
89 #define TX4938_SRAM_SIZE 0x800
90
tx4938_setup(void)91 void __init tx4938_setup(void)
92 {
93 int i;
94 __u32 divmode;
95 int cpuclk = 0;
96 u64 ccfg;
97
98 txx9_reg_res_init(TX4938_REV_PCODE(), TX4938_REG_BASE,
99 TX4938_REG_SIZE);
100 set_c0_config(TX49_CONF_CWFON);
101
102 /* SDRAMC,EBUSC are configured by PROM */
103 for (i = 0; i < 8; i++) {
104 if (!(TX4938_EBUSC_CR(i) & 0x8))
105 continue; /* disabled */
106 txx9_ce_res[i].start = (unsigned long)TX4938_EBUSC_BA(i);
107 txx9_ce_res[i].end =
108 txx9_ce_res[i].start + TX4938_EBUSC_SIZE(i) - 1;
109 request_resource(&iomem_resource, &txx9_ce_res[i]);
110 }
111
112 /* clocks */
113 ccfg = ____raw_readq(&tx4938_ccfgptr->ccfg);
114 if (txx9_master_clock) {
115 /* calculate gbus_clock and cpu_clock from master_clock */
116 divmode = (__u32)ccfg & TX4938_CCFG_DIVMODE_MASK;
117 switch (divmode) {
118 case TX4938_CCFG_DIVMODE_8:
119 case TX4938_CCFG_DIVMODE_10:
120 case TX4938_CCFG_DIVMODE_12:
121 case TX4938_CCFG_DIVMODE_16:
122 case TX4938_CCFG_DIVMODE_18:
123 txx9_gbus_clock = txx9_master_clock * 4; break;
124 default:
125 txx9_gbus_clock = txx9_master_clock;
126 }
127 switch (divmode) {
128 case TX4938_CCFG_DIVMODE_2:
129 case TX4938_CCFG_DIVMODE_8:
130 cpuclk = txx9_gbus_clock * 2; break;
131 case TX4938_CCFG_DIVMODE_2_5:
132 case TX4938_CCFG_DIVMODE_10:
133 cpuclk = txx9_gbus_clock * 5 / 2; break;
134 case TX4938_CCFG_DIVMODE_3:
135 case TX4938_CCFG_DIVMODE_12:
136 cpuclk = txx9_gbus_clock * 3; break;
137 case TX4938_CCFG_DIVMODE_4:
138 case TX4938_CCFG_DIVMODE_16:
139 cpuclk = txx9_gbus_clock * 4; break;
140 case TX4938_CCFG_DIVMODE_4_5:
141 case TX4938_CCFG_DIVMODE_18:
142 cpuclk = txx9_gbus_clock * 9 / 2; break;
143 }
144 txx9_cpu_clock = cpuclk;
145 } else {
146 if (txx9_cpu_clock == 0)
147 txx9_cpu_clock = 300000000; /* 300MHz */
148 /* calculate gbus_clock and master_clock from cpu_clock */
149 cpuclk = txx9_cpu_clock;
150 divmode = (__u32)ccfg & TX4938_CCFG_DIVMODE_MASK;
151 switch (divmode) {
152 case TX4938_CCFG_DIVMODE_2:
153 case TX4938_CCFG_DIVMODE_8:
154 txx9_gbus_clock = cpuclk / 2; break;
155 case TX4938_CCFG_DIVMODE_2_5:
156 case TX4938_CCFG_DIVMODE_10:
157 txx9_gbus_clock = cpuclk * 2 / 5; break;
158 case TX4938_CCFG_DIVMODE_3:
159 case TX4938_CCFG_DIVMODE_12:
160 txx9_gbus_clock = cpuclk / 3; break;
161 case TX4938_CCFG_DIVMODE_4:
162 case TX4938_CCFG_DIVMODE_16:
163 txx9_gbus_clock = cpuclk / 4; break;
164 case TX4938_CCFG_DIVMODE_4_5:
165 case TX4938_CCFG_DIVMODE_18:
166 txx9_gbus_clock = cpuclk * 2 / 9; break;
167 }
168 switch (divmode) {
169 case TX4938_CCFG_DIVMODE_8:
170 case TX4938_CCFG_DIVMODE_10:
171 case TX4938_CCFG_DIVMODE_12:
172 case TX4938_CCFG_DIVMODE_16:
173 case TX4938_CCFG_DIVMODE_18:
174 txx9_master_clock = txx9_gbus_clock / 4; break;
175 default:
176 txx9_master_clock = txx9_gbus_clock;
177 }
178 }
179 /* change default value to udelay/mdelay take reasonable time */
180 loops_per_jiffy = txx9_cpu_clock / HZ / 2;
181
182 /* CCFG */
183 tx4938_wdr_init();
184 /* clear BusErrorOnWrite flag (W1C) */
185 tx4938_ccfg_set(TX4938_CCFG_BEOW);
186 /* enable Timeout BusError */
187 if (txx9_ccfg_toeon)
188 tx4938_ccfg_set(TX4938_CCFG_TOE);
189
190 /* DMA selection */
191 txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_DMASEL_ALL);
192
193 /* Use external clock for external arbiter */
194 if (!(____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB))
195 txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_PCICLKEN_ALL);
196
197 printk(KERN_INFO "%s -- %dMHz(M%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
198 txx9_pcode_str,
199 (cpuclk + 500000) / 1000000,
200 (txx9_master_clock + 500000) / 1000000,
201 (__u32)____raw_readq(&tx4938_ccfgptr->crir),
202 (unsigned long long)____raw_readq(&tx4938_ccfgptr->ccfg),
203 (unsigned long long)____raw_readq(&tx4938_ccfgptr->pcfg));
204
205 printk(KERN_INFO "%s SDRAMC --", txx9_pcode_str);
206 for (i = 0; i < 4; i++) {
207 __u64 cr = TX4938_SDRAMC_CR(i);
208 unsigned long base, size;
209 if (!((__u32)cr & 0x00000400))
210 continue; /* disabled */
211 base = (unsigned long)(cr >> 49) << 21;
212 size = (((unsigned long)(cr >> 33) & 0x7fff) + 1) << 21;
213 printk(" CR%d:%016llx", i, (unsigned long long)cr);
214 tx4938_sdram_resource[i].name = "SDRAM";
215 tx4938_sdram_resource[i].start = base;
216 tx4938_sdram_resource[i].end = base + size - 1;
217 tx4938_sdram_resource[i].flags = IORESOURCE_MEM;
218 request_resource(&iomem_resource, &tx4938_sdram_resource[i]);
219 }
220 printk(" TR:%09llx\n",
221 (unsigned long long)____raw_readq(&tx4938_sdramcptr->tr));
222
223 /* SRAM */
224 if (txx9_pcode == 0x4938 && ____raw_readq(&tx4938_sramcptr->cr) & 1) {
225 unsigned int size = TX4938_SRAM_SIZE;
226 tx4938_sram_resource.name = "SRAM";
227 tx4938_sram_resource.start =
228 (____raw_readq(&tx4938_sramcptr->cr) >> (39-11))
229 & ~(size - 1);
230 tx4938_sram_resource.end =
231 tx4938_sram_resource.start + TX4938_SRAM_SIZE - 1;
232 tx4938_sram_resource.flags = IORESOURCE_MEM;
233 request_resource(&iomem_resource, &tx4938_sram_resource);
234 }
235
236 /* TMR */
237 /* disable all timers */
238 for (i = 0; i < TX4938_NR_TMR; i++)
239 txx9_tmr_init(TX4938_TMR_REG(i) & 0xfffffffffULL);
240
241 /* DMA */
242 for (i = 0; i < 2; i++)
243 ____raw_writeq(TX4938_DMA_MCR_MSTEN,
244 (void __iomem *)(TX4938_DMA_REG(i) + 0x50));
245
246 /* PIO */
247 txx9_gpio_init(TX4938_PIO_REG & 0xfffffffffULL, 0, TX4938_NUM_PIO);
248 __raw_writel(0, &tx4938_pioptr->maskcpu);
249 __raw_writel(0, &tx4938_pioptr->maskext);
250
251 if (txx9_pcode == 0x4938) {
252 __u64 pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg);
253 /* set PCIC1 reset */
254 txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST);
255 if (pcfg & (TX4938_PCFG_ETH0_SEL | TX4938_PCFG_ETH1_SEL)) {
256 mdelay(1); /* at least 128 cpu clock */
257 /* clear PCIC1 reset */
258 txx9_clear64(&tx4938_ccfgptr->clkctr,
259 TX4938_CLKCTR_PCIC1RST);
260 } else {
261 printk(KERN_INFO "%s: stop PCIC1\n", txx9_pcode_str);
262 /* stop PCIC1 */
263 txx9_set64(&tx4938_ccfgptr->clkctr,
264 TX4938_CLKCTR_PCIC1CKD);
265 }
266 if (!(pcfg & TX4938_PCFG_ETH0_SEL)) {
267 printk(KERN_INFO "%s: stop ETH0\n", txx9_pcode_str);
268 txx9_set64(&tx4938_ccfgptr->clkctr,
269 TX4938_CLKCTR_ETH0RST);
270 txx9_set64(&tx4938_ccfgptr->clkctr,
271 TX4938_CLKCTR_ETH0CKD);
272 }
273 if (!(pcfg & TX4938_PCFG_ETH1_SEL)) {
274 printk(KERN_INFO "%s: stop ETH1\n", txx9_pcode_str);
275 txx9_set64(&tx4938_ccfgptr->clkctr,
276 TX4938_CLKCTR_ETH1RST);
277 txx9_set64(&tx4938_ccfgptr->clkctr,
278 TX4938_CLKCTR_ETH1CKD);
279 }
280 }
281
282 _machine_restart = tx4938_machine_restart;
283 board_be_init = tx4938_be_init;
284 }
285
tx4938_time_init(unsigned int tmrnr)286 void __init tx4938_time_init(unsigned int tmrnr)
287 {
288 if (____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_TINTDIS)
289 txx9_clockevent_init(TX4938_TMR_REG(tmrnr) & 0xfffffffffULL,
290 TXX9_IRQ_BASE + TX4938_IR_TMR(tmrnr),
291 TXX9_IMCLK);
292 }
293
tx4938_sio_init(unsigned int sclk,unsigned int cts_mask)294 void __init tx4938_sio_init(unsigned int sclk, unsigned int cts_mask)
295 {
296 int i;
297 unsigned int ch_mask = 0;
298
299 if (__raw_readq(&tx4938_ccfgptr->pcfg) & TX4938_PCFG_ETH0_SEL)
300 ch_mask |= 1 << 1; /* disable SIO1 by PCFG setting */
301 for (i = 0; i < 2; i++) {
302 if ((1 << i) & ch_mask)
303 continue;
304 txx9_sio_init(TX4938_SIO_REG(i) & 0xfffffffffULL,
305 TXX9_IRQ_BASE + TX4938_IR_SIO(i),
306 i, sclk, (1 << i) & cts_mask);
307 }
308 }
309
tx4938_spi_init(int busid)310 void __init tx4938_spi_init(int busid)
311 {
312 txx9_spi_init(busid, TX4938_SPI_REG & 0xfffffffffULL,
313 TXX9_IRQ_BASE + TX4938_IR_SPI);
314 }
315
tx4938_ethaddr_init(unsigned char * addr0,unsigned char * addr1)316 void __init tx4938_ethaddr_init(unsigned char *addr0, unsigned char *addr1)
317 {
318 u64 pcfg = __raw_readq(&tx4938_ccfgptr->pcfg);
319
320 if (addr0 && (pcfg & TX4938_PCFG_ETH0_SEL))
321 txx9_ethaddr_init(TXX9_IRQ_BASE + TX4938_IR_ETH0, addr0);
322 if (addr1 && (pcfg & TX4938_PCFG_ETH1_SEL))
323 txx9_ethaddr_init(TXX9_IRQ_BASE + TX4938_IR_ETH1, addr1);
324 }
325
tx4938_mtd_init(int ch)326 void __init tx4938_mtd_init(int ch)
327 {
328 struct physmap_flash_data pdata = {
329 .width = TX4938_EBUSC_WIDTH(ch) / 8,
330 };
331 unsigned long start = txx9_ce_res[ch].start;
332 unsigned long size = txx9_ce_res[ch].end - start + 1;
333
334 if (!(TX4938_EBUSC_CR(ch) & 0x8))
335 return; /* disabled */
336 txx9_physmap_flash_init(ch, start, size, &pdata);
337 }
338
tx4938_ata_init(unsigned int irq,unsigned int shift,int tune)339 void __init tx4938_ata_init(unsigned int irq, unsigned int shift, int tune)
340 {
341 struct platform_device *pdev;
342 struct resource res[] = {
343 {
344 /* .start and .end are filled in later */
345 .flags = IORESOURCE_MEM,
346 }, {
347 .start = irq,
348 .flags = IORESOURCE_IRQ,
349 },
350 };
351 struct tx4938ide_platform_info pdata = {
352 .ioport_shift = shift,
353 /*
354 * The IDE driver should not change bus timings if other ISA
355 * devices existed.
356 */
357 .gbus_clock = tune ? txx9_gbus_clock : 0,
358 };
359 u64 ebccr;
360 int i;
361
362 if ((__raw_readq(&tx4938_ccfgptr->pcfg) &
363 (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL))
364 != TX4938_PCFG_ATA_SEL)
365 return;
366 for (i = 0; i < 8; i++) {
367 /* check EBCCRn.ISA, EBCCRn.BSZ, EBCCRn.ME */
368 ebccr = __raw_readq(&tx4938_ebuscptr->cr[i]);
369 if ((ebccr & 0x00f00008) == 0x00e00008)
370 break;
371 }
372 if (i == 8)
373 return;
374 pdata.ebus_ch = i;
375 res[0].start = ((ebccr >> 48) << 20) + 0x10000;
376 res[0].end = res[0].start + 0x20000 - 1;
377 pdev = platform_device_alloc("tx4938ide", -1);
378 if (!pdev ||
379 platform_device_add_resources(pdev, res, ARRAY_SIZE(res)) ||
380 platform_device_add_data(pdev, &pdata, sizeof(pdata)) ||
381 platform_device_add(pdev))
382 platform_device_put(pdev);
383 }
384
tx4938_stop_unused_modules(void)385 static void __init tx4938_stop_unused_modules(void)
386 {
387 __u64 pcfg, rst = 0, ckd = 0;
388 char buf[128];
389
390 buf[0] = '\0';
391 local_irq_disable();
392 pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg);
393 switch (txx9_pcode) {
394 case 0x4937:
395 if (!(pcfg & TX4938_PCFG_SEL2)) {
396 rst |= TX4938_CLKCTR_ACLRST;
397 ckd |= TX4938_CLKCTR_ACLCKD;
398 strcat(buf, " ACLC");
399 }
400 break;
401 case 0x4938:
402 if (!(pcfg & TX4938_PCFG_SEL2) ||
403 (pcfg & TX4938_PCFG_ETH0_SEL)) {
404 rst |= TX4938_CLKCTR_ACLRST;
405 ckd |= TX4938_CLKCTR_ACLCKD;
406 strcat(buf, " ACLC");
407 }
408 if ((pcfg &
409 (TX4938_PCFG_ATA_SEL | TX4938_PCFG_ISA_SEL |
410 TX4938_PCFG_NDF_SEL))
411 != TX4938_PCFG_NDF_SEL) {
412 rst |= TX4938_CLKCTR_NDFRST;
413 ckd |= TX4938_CLKCTR_NDFCKD;
414 strcat(buf, " NDFMC");
415 }
416 if (!(pcfg & TX4938_PCFG_SPI_SEL)) {
417 rst |= TX4938_CLKCTR_SPIRST;
418 ckd |= TX4938_CLKCTR_SPICKD;
419 strcat(buf, " SPI");
420 }
421 break;
422 }
423 if (rst | ckd) {
424 txx9_set64(&tx4938_ccfgptr->clkctr, rst);
425 txx9_set64(&tx4938_ccfgptr->clkctr, ckd);
426 }
427 local_irq_enable();
428 if (buf[0])
429 pr_info("%s: stop%s\n", txx9_pcode_str, buf);
430 }
431
tx4938_late_init(void)432 static int __init tx4938_late_init(void)
433 {
434 if (txx9_pcode != 0x4937 && txx9_pcode != 0x4938)
435 return -ENODEV;
436 tx4938_stop_unused_modules();
437 return 0;
438 }
439 late_initcall(tx4938_late_init);
440