1 #ifndef __ASM_ARCH_PXA3XX_NAND_H 2 #define __ASM_ARCH_PXA3XX_NAND_H 3 4 #include <linux/mtd/mtd.h> 5 #include <linux/mtd/partitions.h> 6 7 struct pxa3xx_nand_timing { 8 unsigned int tCH; /* Enable signal hold time */ 9 unsigned int tCS; /* Enable signal setup time */ 10 unsigned int tWH; /* ND_nWE high duration */ 11 unsigned int tWP; /* ND_nWE pulse time */ 12 unsigned int tRH; /* ND_nRE high duration */ 13 unsigned int tRP; /* ND_nRE pulse width */ 14 unsigned int tR; /* ND_nWE high to ND_nRE low for read */ 15 unsigned int tWHR; /* ND_nWE high to ND_nRE low for status read */ 16 unsigned int tAR; /* ND_ALE low to ND_nRE low delay */ 17 }; 18 19 struct pxa3xx_nand_cmdset { 20 uint16_t read1; 21 uint16_t read2; 22 uint16_t program; 23 uint16_t read_status; 24 uint16_t read_id; 25 uint16_t erase; 26 uint16_t reset; 27 uint16_t lock; 28 uint16_t unlock; 29 uint16_t lock_status; 30 }; 31 32 struct pxa3xx_nand_flash { 33 const struct pxa3xx_nand_timing *timing; /* NAND Flash timing */ 34 const struct pxa3xx_nand_cmdset *cmdset; 35 36 uint32_t page_per_block;/* Pages per block (PG_PER_BLK) */ 37 uint32_t page_size; /* Page size in bytes (PAGE_SZ) */ 38 uint32_t flash_width; /* Width of Flash memory (DWIDTH_M) */ 39 uint32_t dfc_width; /* Width of flash controller(DWIDTH_C) */ 40 uint32_t num_blocks; /* Number of physical blocks in Flash */ 41 uint32_t chip_id; 42 }; 43 44 struct pxa3xx_nand_platform_data { 45 46 /* the data flash bus is shared between the Static Memory 47 * Controller and the Data Flash Controller, the arbiter 48 * controls the ownership of the bus 49 */ 50 int enable_arbiter; 51 52 const struct mtd_partition *parts; 53 unsigned int nr_parts; 54 55 const struct pxa3xx_nand_flash * flash; 56 size_t num_flash; 57 }; 58 59 extern void pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info); 60 #endif /* __ASM_ARCH_PXA3XX_NAND_H */ 61