1 /* -*- mode: c; c-basic-offset: 8 -*- */
2
3 /* Copyright (C) 1999,2001
4 *
5 * Author: J.E.J.Bottomley@HansenPartnership.com
6 *
7 * This file provides all the same external entries as smp.c but uses
8 * the voyager hal to provide the functionality
9 */
10 #include <linux/cpu.h>
11 #include <linux/module.h>
12 #include <linux/mm.h>
13 #include <linux/kernel_stat.h>
14 #include <linux/delay.h>
15 #include <linux/mc146818rtc.h>
16 #include <linux/cache.h>
17 #include <linux/interrupt.h>
18 #include <linux/init.h>
19 #include <linux/kernel.h>
20 #include <linux/bootmem.h>
21 #include <linux/completion.h>
22 #include <asm/desc.h>
23 #include <asm/voyager.h>
24 #include <asm/vic.h>
25 #include <asm/mtrr.h>
26 #include <asm/pgalloc.h>
27 #include <asm/tlbflush.h>
28 #include <asm/arch_hooks.h>
29 #include <asm/trampoline.h>
30
31 /* TLB state -- visible externally, indexed physically */
32 DEFINE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate) = { &init_mm, 0 };
33
34 /* CPU IRQ affinity -- set to all ones initially */
35 static unsigned long cpu_irq_affinity[NR_CPUS] __cacheline_aligned =
36 {[0 ... NR_CPUS-1] = ~0UL };
37
38 /* per CPU data structure (for /proc/cpuinfo et al), visible externally
39 * indexed physically */
40 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
41 EXPORT_PER_CPU_SYMBOL(cpu_info);
42
43 /* physical ID of the CPU used to boot the system */
44 unsigned char boot_cpu_id;
45
46 /* The memory line addresses for the Quad CPIs */
47 struct voyager_qic_cpi *voyager_quad_cpi_addr[NR_CPUS] __cacheline_aligned;
48
49 /* The masks for the Extended VIC processors, filled in by cat_init */
50 __u32 voyager_extended_vic_processors = 0;
51
52 /* Masks for the extended Quad processors which cannot be VIC booted */
53 __u32 voyager_allowed_boot_processors = 0;
54
55 /* The mask for the Quad Processors (both extended and non-extended) */
56 __u32 voyager_quad_processors = 0;
57
58 /* Total count of live CPUs, used in process.c to display
59 * the CPU information and in irq.c for the per CPU irq
60 * activity count. Finally exported by i386_ksyms.c */
61 static int voyager_extended_cpus = 1;
62
63 /* Used for the invalidate map that's also checked in the spinlock */
64 static volatile unsigned long smp_invalidate_needed;
65
66 /* Bitmask of CPUs present in the system - exported by i386_syms.c, used
67 * by scheduler but indexed physically */
68 static cpumask_t voyager_phys_cpu_present_map = CPU_MASK_NONE;
69
70 /* The internal functions */
71 static void send_CPI(__u32 cpuset, __u8 cpi);
72 static void ack_CPI(__u8 cpi);
73 static int ack_QIC_CPI(__u8 cpi);
74 static void ack_special_QIC_CPI(__u8 cpi);
75 static void ack_VIC_CPI(__u8 cpi);
76 static void send_CPI_allbutself(__u8 cpi);
77 static void mask_vic_irq(unsigned int irq);
78 static void unmask_vic_irq(unsigned int irq);
79 static unsigned int startup_vic_irq(unsigned int irq);
80 static void enable_local_vic_irq(unsigned int irq);
81 static void disable_local_vic_irq(unsigned int irq);
82 static void before_handle_vic_irq(unsigned int irq);
83 static void after_handle_vic_irq(unsigned int irq);
84 static void set_vic_irq_affinity(unsigned int irq, const struct cpumask *mask);
85 static void ack_vic_irq(unsigned int irq);
86 static void vic_enable_cpi(void);
87 static void do_boot_cpu(__u8 cpuid);
88 static void do_quad_bootstrap(void);
89 static void initialize_secondary(void);
90
91 int hard_smp_processor_id(void);
92 int safe_smp_processor_id(void);
93
94 /* Inline functions */
send_one_QIC_CPI(__u8 cpu,__u8 cpi)95 static inline void send_one_QIC_CPI(__u8 cpu, __u8 cpi)
96 {
97 voyager_quad_cpi_addr[cpu]->qic_cpi[cpi].cpi =
98 (smp_processor_id() << 16) + cpi;
99 }
100
send_QIC_CPI(__u32 cpuset,__u8 cpi)101 static inline void send_QIC_CPI(__u32 cpuset, __u8 cpi)
102 {
103 int cpu;
104
105 for_each_online_cpu(cpu) {
106 if (cpuset & (1 << cpu)) {
107 #ifdef VOYAGER_DEBUG
108 if (!cpu_online(cpu))
109 VDEBUG(("CPU%d sending cpi %d to CPU%d not in "
110 "cpu_online_map\n",
111 hard_smp_processor_id(), cpi, cpu));
112 #endif
113 send_one_QIC_CPI(cpu, cpi - QIC_CPI_OFFSET);
114 }
115 }
116 }
117
wrapper_smp_local_timer_interrupt(void)118 static inline void wrapper_smp_local_timer_interrupt(void)
119 {
120 irq_enter();
121 smp_local_timer_interrupt();
122 irq_exit();
123 }
124
send_one_CPI(__u8 cpu,__u8 cpi)125 static inline void send_one_CPI(__u8 cpu, __u8 cpi)
126 {
127 if (voyager_quad_processors & (1 << cpu))
128 send_one_QIC_CPI(cpu, cpi - QIC_CPI_OFFSET);
129 else
130 send_CPI(1 << cpu, cpi);
131 }
132
send_CPI_allbutself(__u8 cpi)133 static inline void send_CPI_allbutself(__u8 cpi)
134 {
135 __u8 cpu = smp_processor_id();
136 __u32 mask = cpus_addr(cpu_online_map)[0] & ~(1 << cpu);
137 send_CPI(mask, cpi);
138 }
139
is_cpu_quad(void)140 static inline int is_cpu_quad(void)
141 {
142 __u8 cpumask = inb(VIC_PROC_WHO_AM_I);
143 return ((cpumask & QUAD_IDENTIFIER) == QUAD_IDENTIFIER);
144 }
145
is_cpu_extended(void)146 static inline int is_cpu_extended(void)
147 {
148 __u8 cpu = hard_smp_processor_id();
149
150 return (voyager_extended_vic_processors & (1 << cpu));
151 }
152
is_cpu_vic_boot(void)153 static inline int is_cpu_vic_boot(void)
154 {
155 __u8 cpu = hard_smp_processor_id();
156
157 return (voyager_extended_vic_processors
158 & voyager_allowed_boot_processors & (1 << cpu));
159 }
160
ack_CPI(__u8 cpi)161 static inline void ack_CPI(__u8 cpi)
162 {
163 switch (cpi) {
164 case VIC_CPU_BOOT_CPI:
165 if (is_cpu_quad() && !is_cpu_vic_boot())
166 ack_QIC_CPI(cpi);
167 else
168 ack_VIC_CPI(cpi);
169 break;
170 case VIC_SYS_INT:
171 case VIC_CMN_INT:
172 /* These are slightly strange. Even on the Quad card,
173 * They are vectored as VIC CPIs */
174 if (is_cpu_quad())
175 ack_special_QIC_CPI(cpi);
176 else
177 ack_VIC_CPI(cpi);
178 break;
179 default:
180 printk("VOYAGER ERROR: CPI%d is in common CPI code\n", cpi);
181 break;
182 }
183 }
184
185 /* local variables */
186
187 /* The VIC IRQ descriptors -- these look almost identical to the
188 * 8259 IRQs except that masks and things must be kept per processor
189 */
190 static struct irq_chip vic_chip = {
191 .name = "VIC",
192 .startup = startup_vic_irq,
193 .mask = mask_vic_irq,
194 .unmask = unmask_vic_irq,
195 .set_affinity = set_vic_irq_affinity,
196 };
197
198 /* used to count up as CPUs are brought on line (starts at 0) */
199 static int cpucount = 0;
200
201 /* The per cpu profile stuff - used in smp_local_timer_interrupt */
202 static DEFINE_PER_CPU(int, prof_multiplier) = 1;
203 static DEFINE_PER_CPU(int, prof_old_multiplier) = 1;
204 static DEFINE_PER_CPU(int, prof_counter) = 1;
205
206 /* the map used to check if a CPU has booted */
207 static __u32 cpu_booted_map;
208
209 /* the synchronize flag used to hold all secondary CPUs spinning in
210 * a tight loop until the boot sequence is ready for them */
211 static cpumask_t smp_commenced_mask = CPU_MASK_NONE;
212
213 /* This is for the new dynamic CPU boot code */
214
215 /* The per processor IRQ masks (these are usually kept in sync) */
216 static __u16 vic_irq_mask[NR_CPUS] __cacheline_aligned;
217
218 /* the list of IRQs to be enabled by the VIC_ENABLE_IRQ_CPI */
219 static __u16 vic_irq_enable_mask[NR_CPUS] __cacheline_aligned = { 0 };
220
221 /* Lock for enable/disable of VIC interrupts */
222 static __cacheline_aligned DEFINE_SPINLOCK(vic_irq_lock);
223
224 /* The boot processor is correctly set up in PC mode when it
225 * comes up, but the secondaries need their master/slave 8259
226 * pairs initializing correctly */
227
228 /* Interrupt counters (per cpu) and total - used to try to
229 * even up the interrupt handling routines */
230 static long vic_intr_total = 0;
231 static long vic_intr_count[NR_CPUS] __cacheline_aligned = { 0 };
232 static unsigned long vic_tick[NR_CPUS] __cacheline_aligned = { 0 };
233
234 /* Since we can only use CPI0, we fake all the other CPIs */
235 static unsigned long vic_cpi_mailbox[NR_CPUS] __cacheline_aligned;
236
237 /* debugging routine to read the isr of the cpu's pic */
vic_read_isr(void)238 static inline __u16 vic_read_isr(void)
239 {
240 __u16 isr;
241
242 outb(0x0b, 0xa0);
243 isr = inb(0xa0) << 8;
244 outb(0x0b, 0x20);
245 isr |= inb(0x20);
246
247 return isr;
248 }
249
qic_setup(void)250 static __init void qic_setup(void)
251 {
252 if (!is_cpu_quad()) {
253 /* not a quad, no setup */
254 return;
255 }
256 outb(QIC_DEFAULT_MASK0, QIC_MASK_REGISTER0);
257 outb(QIC_CPI_ENABLE, QIC_MASK_REGISTER1);
258
259 if (is_cpu_extended()) {
260 /* the QIC duplicate of the VIC base register */
261 outb(VIC_DEFAULT_CPI_BASE, QIC_VIC_CPI_BASE_REGISTER);
262 outb(QIC_DEFAULT_CPI_BASE, QIC_CPI_BASE_REGISTER);
263
264 /* FIXME: should set up the QIC timer and memory parity
265 * error vectors here */
266 }
267 }
268
vic_setup_pic(void)269 static __init void vic_setup_pic(void)
270 {
271 outb(1, VIC_REDIRECT_REGISTER_1);
272 /* clear the claim registers for dynamic routing */
273 outb(0, VIC_CLAIM_REGISTER_0);
274 outb(0, VIC_CLAIM_REGISTER_1);
275
276 outb(0, VIC_PRIORITY_REGISTER);
277 /* Set the Primary and Secondary Microchannel vector
278 * bases to be the same as the ordinary interrupts
279 *
280 * FIXME: This would be more efficient using separate
281 * vectors. */
282 outb(FIRST_EXTERNAL_VECTOR, VIC_PRIMARY_MC_BASE);
283 outb(FIRST_EXTERNAL_VECTOR, VIC_SECONDARY_MC_BASE);
284 /* Now initiallise the master PIC belonging to this CPU by
285 * sending the four ICWs */
286
287 /* ICW1: level triggered, ICW4 needed */
288 outb(0x19, 0x20);
289
290 /* ICW2: vector base */
291 outb(FIRST_EXTERNAL_VECTOR, 0x21);
292
293 /* ICW3: slave at line 2 */
294 outb(0x04, 0x21);
295
296 /* ICW4: 8086 mode */
297 outb(0x01, 0x21);
298
299 /* now the same for the slave PIC */
300
301 /* ICW1: level trigger, ICW4 needed */
302 outb(0x19, 0xA0);
303
304 /* ICW2: slave vector base */
305 outb(FIRST_EXTERNAL_VECTOR + 8, 0xA1);
306
307 /* ICW3: slave ID */
308 outb(0x02, 0xA1);
309
310 /* ICW4: 8086 mode */
311 outb(0x01, 0xA1);
312 }
313
do_quad_bootstrap(void)314 static void do_quad_bootstrap(void)
315 {
316 if (is_cpu_quad() && is_cpu_vic_boot()) {
317 int i;
318 unsigned long flags;
319 __u8 cpuid = hard_smp_processor_id();
320
321 local_irq_save(flags);
322
323 for (i = 0; i < 4; i++) {
324 /* FIXME: this would be >>3 &0x7 on the 32 way */
325 if (((cpuid >> 2) & 0x03) == i)
326 /* don't lower our own mask! */
327 continue;
328
329 /* masquerade as local Quad CPU */
330 outb(QIC_CPUID_ENABLE | i, QIC_PROCESSOR_ID);
331 /* enable the startup CPI */
332 outb(QIC_BOOT_CPI_MASK, QIC_MASK_REGISTER1);
333 /* restore cpu id */
334 outb(0, QIC_PROCESSOR_ID);
335 }
336 local_irq_restore(flags);
337 }
338 }
339
prefill_possible_map(void)340 void prefill_possible_map(void)
341 {
342 /* This is empty on voyager because we need a much
343 * earlier detection which is done in find_smp_config */
344 }
345
346 /* Set up all the basic stuff: read the SMP config and make all the
347 * SMP information reflect only the boot cpu. All others will be
348 * brought on-line later. */
find_smp_config(void)349 void __init find_smp_config(void)
350 {
351 int i;
352
353 boot_cpu_id = hard_smp_processor_id();
354
355 printk("VOYAGER SMP: Boot cpu is %d\n", boot_cpu_id);
356
357 /* initialize the CPU structures (moved from smp_boot_cpus) */
358 for (i = 0; i < nr_cpu_ids; i++)
359 cpu_irq_affinity[i] = ~0;
360 cpu_online_map = cpumask_of_cpu(boot_cpu_id);
361
362 /* The boot CPU must be extended */
363 voyager_extended_vic_processors = 1 << boot_cpu_id;
364 /* initially, all of the first 8 CPUs can boot */
365 voyager_allowed_boot_processors = 0xff;
366 /* set up everything for just this CPU, we can alter
367 * this as we start the other CPUs later */
368 /* now get the CPU disposition from the extended CMOS */
369 cpus_addr(voyager_phys_cpu_present_map)[0] =
370 voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK);
371 cpus_addr(voyager_phys_cpu_present_map)[0] |=
372 voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK + 1) << 8;
373 cpus_addr(voyager_phys_cpu_present_map)[0] |=
374 voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK +
375 2) << 16;
376 cpus_addr(voyager_phys_cpu_present_map)[0] |=
377 voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK +
378 3) << 24;
379 init_cpu_possible(&voyager_phys_cpu_present_map);
380 printk("VOYAGER SMP: voyager_phys_cpu_present_map = 0x%lx\n",
381 cpus_addr(voyager_phys_cpu_present_map)[0]);
382 /* Here we set up the VIC to enable SMP */
383 /* enable the CPIs by writing the base vector to their register */
384 outb(VIC_DEFAULT_CPI_BASE, VIC_CPI_BASE_REGISTER);
385 outb(1, VIC_REDIRECT_REGISTER_1);
386 /* set the claim registers for static routing --- Boot CPU gets
387 * all interrupts untill all other CPUs started */
388 outb(0xff, VIC_CLAIM_REGISTER_0);
389 outb(0xff, VIC_CLAIM_REGISTER_1);
390 /* Set the Primary and Secondary Microchannel vector
391 * bases to be the same as the ordinary interrupts
392 *
393 * FIXME: This would be more efficient using separate
394 * vectors. */
395 outb(FIRST_EXTERNAL_VECTOR, VIC_PRIMARY_MC_BASE);
396 outb(FIRST_EXTERNAL_VECTOR, VIC_SECONDARY_MC_BASE);
397
398 /* Finally tell the firmware that we're driving */
399 outb(inb(VOYAGER_SUS_IN_CONTROL_PORT) | VOYAGER_IN_CONTROL_FLAG,
400 VOYAGER_SUS_IN_CONTROL_PORT);
401
402 current_thread_info()->cpu = boot_cpu_id;
403 x86_write_percpu(cpu_number, boot_cpu_id);
404 }
405
406 /*
407 * The bootstrap kernel entry code has set these up. Save them
408 * for a given CPU, id is physical */
smp_store_cpu_info(int id)409 void __init smp_store_cpu_info(int id)
410 {
411 struct cpuinfo_x86 *c = &cpu_data(id);
412
413 *c = boot_cpu_data;
414 c->cpu_index = id;
415
416 identify_secondary_cpu(c);
417 }
418
419 /* Routine initially called when a non-boot CPU is brought online */
start_secondary(void * unused)420 static void __init start_secondary(void *unused)
421 {
422 __u8 cpuid = hard_smp_processor_id();
423
424 cpu_init();
425
426 /* OK, we're in the routine */
427 ack_CPI(VIC_CPU_BOOT_CPI);
428
429 /* setup the 8259 master slave pair belonging to this CPU ---
430 * we won't actually receive any until the boot CPU
431 * relinquishes it's static routing mask */
432 vic_setup_pic();
433
434 qic_setup();
435
436 if (is_cpu_quad() && !is_cpu_vic_boot()) {
437 /* clear the boot CPI */
438 __u8 dummy;
439
440 dummy =
441 voyager_quad_cpi_addr[cpuid]->qic_cpi[VIC_CPU_BOOT_CPI].cpi;
442 printk("read dummy %d\n", dummy);
443 }
444
445 /* lower the mask to receive CPIs */
446 vic_enable_cpi();
447
448 VDEBUG(("VOYAGER SMP: CPU%d, stack at about %p\n", cpuid, &cpuid));
449
450 notify_cpu_starting(cpuid);
451
452 /* enable interrupts */
453 local_irq_enable();
454
455 /* get our bogomips */
456 calibrate_delay();
457
458 /* save our processor parameters */
459 smp_store_cpu_info(cpuid);
460
461 /* if we're a quad, we may need to bootstrap other CPUs */
462 do_quad_bootstrap();
463
464 /* FIXME: this is rather a poor hack to prevent the CPU
465 * activating softirqs while it's supposed to be waiting for
466 * permission to proceed. Without this, the new per CPU stuff
467 * in the softirqs will fail */
468 local_irq_disable();
469 cpu_set(cpuid, cpu_callin_map);
470
471 /* signal that we're done */
472 cpu_booted_map = 1;
473
474 while (!cpu_isset(cpuid, smp_commenced_mask))
475 rep_nop();
476 local_irq_enable();
477
478 local_flush_tlb();
479
480 cpu_set(cpuid, cpu_online_map);
481 wmb();
482 cpu_idle();
483 }
484
485 /* Routine to kick start the given CPU and wait for it to report ready
486 * (or timeout in startup). When this routine returns, the requested
487 * CPU is either fully running and configured or known to be dead.
488 *
489 * We call this routine sequentially 1 CPU at a time, so no need for
490 * locking */
491
do_boot_cpu(__u8 cpu)492 static void __init do_boot_cpu(__u8 cpu)
493 {
494 struct task_struct *idle;
495 int timeout;
496 unsigned long flags;
497 int quad_boot = (1 << cpu) & voyager_quad_processors
498 & ~(voyager_extended_vic_processors
499 & voyager_allowed_boot_processors);
500
501 /* This is the format of the CPI IDT gate (in real mode) which
502 * we're hijacking to boot the CPU */
503 union IDTFormat {
504 struct seg {
505 __u16 Offset;
506 __u16 Segment;
507 } idt;
508 __u32 val;
509 } hijack_source;
510
511 __u32 *hijack_vector;
512 __u32 start_phys_address = setup_trampoline();
513
514 /* There's a clever trick to this: The linux trampoline is
515 * compiled to begin at absolute location zero, so make the
516 * address zero but have the data segment selector compensate
517 * for the actual address */
518 hijack_source.idt.Offset = start_phys_address & 0x000F;
519 hijack_source.idt.Segment = (start_phys_address >> 4) & 0xFFFF;
520
521 cpucount++;
522 alternatives_smp_switch(1);
523
524 idle = fork_idle(cpu);
525 if (IS_ERR(idle))
526 panic("failed fork for CPU%d", cpu);
527 idle->thread.ip = (unsigned long)start_secondary;
528 /* init_tasks (in sched.c) is indexed logically */
529 stack_start.sp = (void *)idle->thread.sp;
530
531 init_gdt(cpu);
532 per_cpu(current_task, cpu) = idle;
533 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
534 irq_ctx_init(cpu);
535
536 /* Note: Don't modify initial ss override */
537 VDEBUG(("VOYAGER SMP: Booting CPU%d at 0x%lx[%x:%x], stack %p\n", cpu,
538 (unsigned long)hijack_source.val, hijack_source.idt.Segment,
539 hijack_source.idt.Offset, stack_start.sp));
540
541 /* init lowmem identity mapping */
542 clone_pgd_range(swapper_pg_dir, swapper_pg_dir + KERNEL_PGD_BOUNDARY,
543 min_t(unsigned long, KERNEL_PGD_PTRS, KERNEL_PGD_BOUNDARY));
544 flush_tlb_all();
545
546 if (quad_boot) {
547 printk("CPU %d: non extended Quad boot\n", cpu);
548 hijack_vector =
549 (__u32 *)
550 phys_to_virt((VIC_CPU_BOOT_CPI + QIC_DEFAULT_CPI_BASE) * 4);
551 *hijack_vector = hijack_source.val;
552 } else {
553 printk("CPU%d: extended VIC boot\n", cpu);
554 hijack_vector =
555 (__u32 *)
556 phys_to_virt((VIC_CPU_BOOT_CPI + VIC_DEFAULT_CPI_BASE) * 4);
557 *hijack_vector = hijack_source.val;
558 /* VIC errata, may also receive interrupt at this address */
559 hijack_vector =
560 (__u32 *)
561 phys_to_virt((VIC_CPU_BOOT_ERRATA_CPI +
562 VIC_DEFAULT_CPI_BASE) * 4);
563 *hijack_vector = hijack_source.val;
564 }
565 /* All non-boot CPUs start with interrupts fully masked. Need
566 * to lower the mask of the CPI we're about to send. We do
567 * this in the VIC by masquerading as the processor we're
568 * about to boot and lowering its interrupt mask */
569 local_irq_save(flags);
570 if (quad_boot) {
571 send_one_QIC_CPI(cpu, VIC_CPU_BOOT_CPI);
572 } else {
573 outb(VIC_CPU_MASQUERADE_ENABLE | cpu, VIC_PROCESSOR_ID);
574 /* here we're altering registers belonging to `cpu' */
575
576 outb(VIC_BOOT_INTERRUPT_MASK, 0x21);
577 /* now go back to our original identity */
578 outb(boot_cpu_id, VIC_PROCESSOR_ID);
579
580 /* and boot the CPU */
581
582 send_CPI((1 << cpu), VIC_CPU_BOOT_CPI);
583 }
584 cpu_booted_map = 0;
585 local_irq_restore(flags);
586
587 /* now wait for it to become ready (or timeout) */
588 for (timeout = 0; timeout < 50000; timeout++) {
589 if (cpu_booted_map)
590 break;
591 udelay(100);
592 }
593 /* reset the page table */
594 zap_low_mappings();
595
596 if (cpu_booted_map) {
597 VDEBUG(("CPU%d: Booted successfully, back in CPU %d\n",
598 cpu, smp_processor_id()));
599
600 printk("CPU%d: ", cpu);
601 print_cpu_info(&cpu_data(cpu));
602 wmb();
603 cpu_set(cpu, cpu_callout_map);
604 cpu_set(cpu, cpu_present_map);
605 } else {
606 printk("CPU%d FAILED TO BOOT: ", cpu);
607 if (*
608 ((volatile unsigned char *)phys_to_virt(start_phys_address))
609 == 0xA5)
610 printk("Stuck.\n");
611 else
612 printk("Not responding.\n");
613
614 cpucount--;
615 }
616 }
617
smp_boot_cpus(void)618 void __init smp_boot_cpus(void)
619 {
620 int i;
621
622 /* CAT BUS initialisation must be done after the memory */
623 /* FIXME: The L4 has a catbus too, it just needs to be
624 * accessed in a totally different way */
625 if (voyager_level == 5) {
626 voyager_cat_init();
627
628 /* now that the cat has probed the Voyager System Bus, sanity
629 * check the cpu map */
630 if (((voyager_quad_processors | voyager_extended_vic_processors)
631 & cpus_addr(voyager_phys_cpu_present_map)[0]) !=
632 cpus_addr(voyager_phys_cpu_present_map)[0]) {
633 /* should panic */
634 printk("\n\n***WARNING*** "
635 "Sanity check of CPU present map FAILED\n");
636 }
637 } else if (voyager_level == 4)
638 voyager_extended_vic_processors =
639 cpus_addr(voyager_phys_cpu_present_map)[0];
640
641 /* this sets up the idle task to run on the current cpu */
642 voyager_extended_cpus = 1;
643 /* Remove the global_irq_holder setting, it triggers a BUG() on
644 * schedule at the moment */
645 //global_irq_holder = boot_cpu_id;
646
647 /* FIXME: Need to do something about this but currently only works
648 * on CPUs with a tsc which none of mine have.
649 smp_tune_scheduling();
650 */
651 smp_store_cpu_info(boot_cpu_id);
652 /* setup the jump vector */
653 initial_code = (unsigned long)initialize_secondary;
654 printk("CPU%d: ", boot_cpu_id);
655 print_cpu_info(&cpu_data(boot_cpu_id));
656
657 if (is_cpu_quad()) {
658 /* booting on a Quad CPU */
659 printk("VOYAGER SMP: Boot CPU is Quad\n");
660 qic_setup();
661 do_quad_bootstrap();
662 }
663
664 /* enable our own CPIs */
665 vic_enable_cpi();
666
667 cpu_set(boot_cpu_id, cpu_online_map);
668 cpu_set(boot_cpu_id, cpu_callout_map);
669
670 /* loop over all the extended VIC CPUs and boot them. The
671 * Quad CPUs must be bootstrapped by their extended VIC cpu */
672 for (i = 0; i < nr_cpu_ids; i++) {
673 if (i == boot_cpu_id || !cpu_isset(i, voyager_phys_cpu_present_map))
674 continue;
675 do_boot_cpu(i);
676 /* This udelay seems to be needed for the Quad boots
677 * don't remove unless you know what you're doing */
678 udelay(1000);
679 }
680 /* we could compute the total bogomips here, but why bother?,
681 * Code added from smpboot.c */
682 {
683 unsigned long bogosum = 0;
684
685 for_each_online_cpu(i)
686 bogosum += cpu_data(i).loops_per_jiffy;
687 printk(KERN_INFO "Total of %d processors activated "
688 "(%lu.%02lu BogoMIPS).\n",
689 cpucount + 1, bogosum / (500000 / HZ),
690 (bogosum / (5000 / HZ)) % 100);
691 }
692 voyager_extended_cpus = hweight32(voyager_extended_vic_processors);
693 printk("VOYAGER: Extended (interrupt handling CPUs): "
694 "%d, non-extended: %d\n", voyager_extended_cpus,
695 num_booting_cpus() - voyager_extended_cpus);
696 /* that's it, switch to symmetric mode */
697 outb(0, VIC_PRIORITY_REGISTER);
698 outb(0, VIC_CLAIM_REGISTER_0);
699 outb(0, VIC_CLAIM_REGISTER_1);
700
701 VDEBUG(("VOYAGER SMP: Booted with %d CPUs\n", num_booting_cpus()));
702 }
703
704 /* Reload the secondary CPUs task structure (this function does not
705 * return ) */
initialize_secondary(void)706 static void __init initialize_secondary(void)
707 {
708 #if 0
709 // AC kernels only
710 set_current(hard_get_current());
711 #endif
712
713 /*
714 * We don't actually need to load the full TSS,
715 * basically just the stack pointer and the eip.
716 */
717
718 asm volatile ("movl %0,%%esp\n\t"
719 "jmp *%1"::"r" (current->thread.sp),
720 "r"(current->thread.ip));
721 }
722
723 /* handle a Voyager SYS_INT -- If we don't, the base board will
724 * panic the system.
725 *
726 * System interrupts occur because some problem was detected on the
727 * various busses. To find out what you have to probe all the
728 * hardware via the CAT bus. FIXME: At the moment we do nothing. */
smp_vic_sys_interrupt(struct pt_regs * regs)729 void smp_vic_sys_interrupt(struct pt_regs *regs)
730 {
731 ack_CPI(VIC_SYS_INT);
732 printk("Voyager SYSTEM INTERRUPT\n");
733 }
734
735 /* Handle a voyager CMN_INT; These interrupts occur either because of
736 * a system status change or because a single bit memory error
737 * occurred. FIXME: At the moment, ignore all this. */
smp_vic_cmn_interrupt(struct pt_regs * regs)738 void smp_vic_cmn_interrupt(struct pt_regs *regs)
739 {
740 static __u8 in_cmn_int = 0;
741 static DEFINE_SPINLOCK(cmn_int_lock);
742
743 /* common ints are broadcast, so make sure we only do this once */
744 _raw_spin_lock(&cmn_int_lock);
745 if (in_cmn_int)
746 goto unlock_end;
747
748 in_cmn_int++;
749 _raw_spin_unlock(&cmn_int_lock);
750
751 VDEBUG(("Voyager COMMON INTERRUPT\n"));
752
753 if (voyager_level == 5)
754 voyager_cat_do_common_interrupt();
755
756 _raw_spin_lock(&cmn_int_lock);
757 in_cmn_int = 0;
758 unlock_end:
759 _raw_spin_unlock(&cmn_int_lock);
760 ack_CPI(VIC_CMN_INT);
761 }
762
763 /*
764 * Reschedule call back. Nothing to do, all the work is done
765 * automatically when we return from the interrupt. */
smp_reschedule_interrupt(void)766 static void smp_reschedule_interrupt(void)
767 {
768 /* do nothing */
769 }
770
771 static struct mm_struct *flush_mm;
772 static unsigned long flush_va;
773 static DEFINE_SPINLOCK(tlbstate_lock);
774
775 /*
776 * We cannot call mmdrop() because we are in interrupt context,
777 * instead update mm->cpu_vm_mask.
778 *
779 * We need to reload %cr3 since the page tables may be going
780 * away from under us..
781 */
voyager_leave_mm(unsigned long cpu)782 static inline void voyager_leave_mm(unsigned long cpu)
783 {
784 if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_OK)
785 BUG();
786 cpu_clear(cpu, per_cpu(cpu_tlbstate, cpu).active_mm->cpu_vm_mask);
787 load_cr3(swapper_pg_dir);
788 }
789
790 /*
791 * Invalidate call-back
792 */
smp_invalidate_interrupt(void)793 static void smp_invalidate_interrupt(void)
794 {
795 __u8 cpu = smp_processor_id();
796
797 if (!test_bit(cpu, &smp_invalidate_needed))
798 return;
799 /* This will flood messages. Don't uncomment unless you see
800 * Problems with cross cpu invalidation
801 VDEBUG(("VOYAGER SMP: CPU%d received INVALIDATE_CPI\n",
802 smp_processor_id()));
803 */
804
805 if (flush_mm == per_cpu(cpu_tlbstate, cpu).active_mm) {
806 if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_OK) {
807 if (flush_va == TLB_FLUSH_ALL)
808 local_flush_tlb();
809 else
810 __flush_tlb_one(flush_va);
811 } else
812 voyager_leave_mm(cpu);
813 }
814 smp_mb__before_clear_bit();
815 clear_bit(cpu, &smp_invalidate_needed);
816 smp_mb__after_clear_bit();
817 }
818
819 /* All the new flush operations for 2.4 */
820
821 /* This routine is called with a physical cpu mask */
822 static void
voyager_flush_tlb_others(unsigned long cpumask,struct mm_struct * mm,unsigned long va)823 voyager_flush_tlb_others(unsigned long cpumask, struct mm_struct *mm,
824 unsigned long va)
825 {
826 int stuck = 50000;
827
828 if (!cpumask)
829 BUG();
830 if ((cpumask & cpus_addr(cpu_online_map)[0]) != cpumask)
831 BUG();
832 if (cpumask & (1 << smp_processor_id()))
833 BUG();
834 if (!mm)
835 BUG();
836
837 spin_lock(&tlbstate_lock);
838
839 flush_mm = mm;
840 flush_va = va;
841 atomic_set_mask(cpumask, &smp_invalidate_needed);
842 /*
843 * We have to send the CPI only to
844 * CPUs affected.
845 */
846 send_CPI(cpumask, VIC_INVALIDATE_CPI);
847
848 while (smp_invalidate_needed) {
849 mb();
850 if (--stuck == 0) {
851 printk("***WARNING*** Stuck doing invalidate CPI "
852 "(CPU%d)\n", smp_processor_id());
853 break;
854 }
855 }
856
857 /* Uncomment only to debug invalidation problems
858 VDEBUG(("VOYAGER SMP: Completed invalidate CPI (CPU%d)\n", cpu));
859 */
860
861 flush_mm = NULL;
862 flush_va = 0;
863 spin_unlock(&tlbstate_lock);
864 }
865
flush_tlb_current_task(void)866 void flush_tlb_current_task(void)
867 {
868 struct mm_struct *mm = current->mm;
869 unsigned long cpu_mask;
870
871 preempt_disable();
872
873 cpu_mask = cpus_addr(mm->cpu_vm_mask)[0] & ~(1 << smp_processor_id());
874 local_flush_tlb();
875 if (cpu_mask)
876 voyager_flush_tlb_others(cpu_mask, mm, TLB_FLUSH_ALL);
877
878 preempt_enable();
879 }
880
flush_tlb_mm(struct mm_struct * mm)881 void flush_tlb_mm(struct mm_struct *mm)
882 {
883 unsigned long cpu_mask;
884
885 preempt_disable();
886
887 cpu_mask = cpus_addr(mm->cpu_vm_mask)[0] & ~(1 << smp_processor_id());
888
889 if (current->active_mm == mm) {
890 if (current->mm)
891 local_flush_tlb();
892 else
893 voyager_leave_mm(smp_processor_id());
894 }
895 if (cpu_mask)
896 voyager_flush_tlb_others(cpu_mask, mm, TLB_FLUSH_ALL);
897
898 preempt_enable();
899 }
900
flush_tlb_page(struct vm_area_struct * vma,unsigned long va)901 void flush_tlb_page(struct vm_area_struct *vma, unsigned long va)
902 {
903 struct mm_struct *mm = vma->vm_mm;
904 unsigned long cpu_mask;
905
906 preempt_disable();
907
908 cpu_mask = cpus_addr(mm->cpu_vm_mask)[0] & ~(1 << smp_processor_id());
909 if (current->active_mm == mm) {
910 if (current->mm)
911 __flush_tlb_one(va);
912 else
913 voyager_leave_mm(smp_processor_id());
914 }
915
916 if (cpu_mask)
917 voyager_flush_tlb_others(cpu_mask, mm, va);
918
919 preempt_enable();
920 }
921
922 EXPORT_SYMBOL(flush_tlb_page);
923
924 /* enable the requested IRQs */
smp_enable_irq_interrupt(void)925 static void smp_enable_irq_interrupt(void)
926 {
927 __u8 irq;
928 __u8 cpu = get_cpu();
929
930 VDEBUG(("VOYAGER SMP: CPU%d enabling irq mask 0x%x\n", cpu,
931 vic_irq_enable_mask[cpu]));
932
933 spin_lock(&vic_irq_lock);
934 for (irq = 0; irq < 16; irq++) {
935 if (vic_irq_enable_mask[cpu] & (1 << irq))
936 enable_local_vic_irq(irq);
937 }
938 vic_irq_enable_mask[cpu] = 0;
939 spin_unlock(&vic_irq_lock);
940
941 put_cpu_no_resched();
942 }
943
944 /*
945 * CPU halt call-back
946 */
smp_stop_cpu_function(void * dummy)947 static void smp_stop_cpu_function(void *dummy)
948 {
949 VDEBUG(("VOYAGER SMP: CPU%d is STOPPING\n", smp_processor_id()));
950 cpu_clear(smp_processor_id(), cpu_online_map);
951 local_irq_disable();
952 for (;;)
953 halt();
954 }
955
956 /* execute a thread on a new CPU. The function to be called must be
957 * previously set up. This is used to schedule a function for
958 * execution on all CPUs - set up the function then broadcast a
959 * function_interrupt CPI to come here on each CPU */
smp_call_function_interrupt(void)960 static void smp_call_function_interrupt(void)
961 {
962 irq_enter();
963 generic_smp_call_function_interrupt();
964 __get_cpu_var(irq_stat).irq_call_count++;
965 irq_exit();
966 }
967
smp_call_function_single_interrupt(void)968 static void smp_call_function_single_interrupt(void)
969 {
970 irq_enter();
971 generic_smp_call_function_single_interrupt();
972 __get_cpu_var(irq_stat).irq_call_count++;
973 irq_exit();
974 }
975
976 /* Sorry about the name. In an APIC based system, the APICs
977 * themselves are programmed to send a timer interrupt. This is used
978 * by linux to reschedule the processor. Voyager doesn't have this,
979 * so we use the system clock to interrupt one processor, which in
980 * turn, broadcasts a timer CPI to all the others --- we receive that
981 * CPI here. We don't use this actually for counting so losing
982 * ticks doesn't matter
983 *
984 * FIXME: For those CPUs which actually have a local APIC, we could
985 * try to use it to trigger this interrupt instead of having to
986 * broadcast the timer tick. Unfortunately, all my pentium DYADs have
987 * no local APIC, so I can't do this
988 *
989 * This function is currently a placeholder and is unused in the code */
smp_apic_timer_interrupt(struct pt_regs * regs)990 void smp_apic_timer_interrupt(struct pt_regs *regs)
991 {
992 struct pt_regs *old_regs = set_irq_regs(regs);
993 wrapper_smp_local_timer_interrupt();
994 set_irq_regs(old_regs);
995 }
996
997 /* All of the QUAD interrupt GATES */
smp_qic_timer_interrupt(struct pt_regs * regs)998 void smp_qic_timer_interrupt(struct pt_regs *regs)
999 {
1000 struct pt_regs *old_regs = set_irq_regs(regs);
1001 ack_QIC_CPI(QIC_TIMER_CPI);
1002 wrapper_smp_local_timer_interrupt();
1003 set_irq_regs(old_regs);
1004 }
1005
smp_qic_invalidate_interrupt(struct pt_regs * regs)1006 void smp_qic_invalidate_interrupt(struct pt_regs *regs)
1007 {
1008 ack_QIC_CPI(QIC_INVALIDATE_CPI);
1009 smp_invalidate_interrupt();
1010 }
1011
smp_qic_reschedule_interrupt(struct pt_regs * regs)1012 void smp_qic_reschedule_interrupt(struct pt_regs *regs)
1013 {
1014 ack_QIC_CPI(QIC_RESCHEDULE_CPI);
1015 smp_reschedule_interrupt();
1016 }
1017
smp_qic_enable_irq_interrupt(struct pt_regs * regs)1018 void smp_qic_enable_irq_interrupt(struct pt_regs *regs)
1019 {
1020 ack_QIC_CPI(QIC_ENABLE_IRQ_CPI);
1021 smp_enable_irq_interrupt();
1022 }
1023
smp_qic_call_function_interrupt(struct pt_regs * regs)1024 void smp_qic_call_function_interrupt(struct pt_regs *regs)
1025 {
1026 ack_QIC_CPI(QIC_CALL_FUNCTION_CPI);
1027 smp_call_function_interrupt();
1028 }
1029
smp_qic_call_function_single_interrupt(struct pt_regs * regs)1030 void smp_qic_call_function_single_interrupt(struct pt_regs *regs)
1031 {
1032 ack_QIC_CPI(QIC_CALL_FUNCTION_SINGLE_CPI);
1033 smp_call_function_single_interrupt();
1034 }
1035
smp_vic_cpi_interrupt(struct pt_regs * regs)1036 void smp_vic_cpi_interrupt(struct pt_regs *regs)
1037 {
1038 struct pt_regs *old_regs = set_irq_regs(regs);
1039 __u8 cpu = smp_processor_id();
1040
1041 if (is_cpu_quad())
1042 ack_QIC_CPI(VIC_CPI_LEVEL0);
1043 else
1044 ack_VIC_CPI(VIC_CPI_LEVEL0);
1045
1046 if (test_and_clear_bit(VIC_TIMER_CPI, &vic_cpi_mailbox[cpu]))
1047 wrapper_smp_local_timer_interrupt();
1048 if (test_and_clear_bit(VIC_INVALIDATE_CPI, &vic_cpi_mailbox[cpu]))
1049 smp_invalidate_interrupt();
1050 if (test_and_clear_bit(VIC_RESCHEDULE_CPI, &vic_cpi_mailbox[cpu]))
1051 smp_reschedule_interrupt();
1052 if (test_and_clear_bit(VIC_ENABLE_IRQ_CPI, &vic_cpi_mailbox[cpu]))
1053 smp_enable_irq_interrupt();
1054 if (test_and_clear_bit(VIC_CALL_FUNCTION_CPI, &vic_cpi_mailbox[cpu]))
1055 smp_call_function_interrupt();
1056 if (test_and_clear_bit(VIC_CALL_FUNCTION_SINGLE_CPI, &vic_cpi_mailbox[cpu]))
1057 smp_call_function_single_interrupt();
1058 set_irq_regs(old_regs);
1059 }
1060
do_flush_tlb_all(void * info)1061 static void do_flush_tlb_all(void *info)
1062 {
1063 unsigned long cpu = smp_processor_id();
1064
1065 __flush_tlb_all();
1066 if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_LAZY)
1067 voyager_leave_mm(cpu);
1068 }
1069
1070 /* flush the TLB of every active CPU in the system */
flush_tlb_all(void)1071 void flush_tlb_all(void)
1072 {
1073 on_each_cpu(do_flush_tlb_all, 0, 1);
1074 }
1075
1076 /* send a reschedule CPI to one CPU by physical CPU number*/
voyager_smp_send_reschedule(int cpu)1077 static void voyager_smp_send_reschedule(int cpu)
1078 {
1079 send_one_CPI(cpu, VIC_RESCHEDULE_CPI);
1080 }
1081
hard_smp_processor_id(void)1082 int hard_smp_processor_id(void)
1083 {
1084 __u8 i;
1085 __u8 cpumask = inb(VIC_PROC_WHO_AM_I);
1086 if ((cpumask & QUAD_IDENTIFIER) == QUAD_IDENTIFIER)
1087 return cpumask & 0x1F;
1088
1089 for (i = 0; i < 8; i++) {
1090 if (cpumask & (1 << i))
1091 return i;
1092 }
1093 printk("** WARNING ** Illegal cpuid returned by VIC: %d", cpumask);
1094 return 0;
1095 }
1096
safe_smp_processor_id(void)1097 int safe_smp_processor_id(void)
1098 {
1099 return hard_smp_processor_id();
1100 }
1101
1102 /* broadcast a halt to all other CPUs */
voyager_smp_send_stop(void)1103 static void voyager_smp_send_stop(void)
1104 {
1105 smp_call_function(smp_stop_cpu_function, NULL, 1);
1106 }
1107
1108 /* this function is triggered in time.c when a clock tick fires
1109 * we need to re-broadcast the tick to all CPUs */
smp_vic_timer_interrupt(void)1110 void smp_vic_timer_interrupt(void)
1111 {
1112 send_CPI_allbutself(VIC_TIMER_CPI);
1113 smp_local_timer_interrupt();
1114 }
1115
1116 /* local (per CPU) timer interrupt. It does both profiling and
1117 * process statistics/rescheduling.
1118 *
1119 * We do profiling in every local tick, statistics/rescheduling
1120 * happen only every 'profiling multiplier' ticks. The default
1121 * multiplier is 1 and it can be changed by writing the new multiplier
1122 * value into /proc/profile.
1123 */
smp_local_timer_interrupt(void)1124 void smp_local_timer_interrupt(void)
1125 {
1126 int cpu = smp_processor_id();
1127 long weight;
1128
1129 profile_tick(CPU_PROFILING);
1130 if (--per_cpu(prof_counter, cpu) <= 0) {
1131 /*
1132 * The multiplier may have changed since the last time we got
1133 * to this point as a result of the user writing to
1134 * /proc/profile. In this case we need to adjust the APIC
1135 * timer accordingly.
1136 *
1137 * Interrupts are already masked off at this point.
1138 */
1139 per_cpu(prof_counter, cpu) = per_cpu(prof_multiplier, cpu);
1140 if (per_cpu(prof_counter, cpu) !=
1141 per_cpu(prof_old_multiplier, cpu)) {
1142 /* FIXME: need to update the vic timer tick here */
1143 per_cpu(prof_old_multiplier, cpu) =
1144 per_cpu(prof_counter, cpu);
1145 }
1146
1147 update_process_times(user_mode_vm(get_irq_regs()));
1148 }
1149
1150 if (((1 << cpu) & voyager_extended_vic_processors) == 0)
1151 /* only extended VIC processors participate in
1152 * interrupt distribution */
1153 return;
1154
1155 /*
1156 * We take the 'long' return path, and there every subsystem
1157 * grabs the appropriate locks (kernel lock/ irq lock).
1158 *
1159 * we might want to decouple profiling from the 'long path',
1160 * and do the profiling totally in assembly.
1161 *
1162 * Currently this isn't too much of an issue (performance wise),
1163 * we can take more than 100K local irqs per second on a 100 MHz P5.
1164 */
1165
1166 if ((++vic_tick[cpu] & 0x7) != 0)
1167 return;
1168 /* get here every 16 ticks (about every 1/6 of a second) */
1169
1170 /* Change our priority to give someone else a chance at getting
1171 * the IRQ. The algorithm goes like this:
1172 *
1173 * In the VIC, the dynamically routed interrupt is always
1174 * handled by the lowest priority eligible (i.e. receiving
1175 * interrupts) CPU. If >1 eligible CPUs are equal lowest, the
1176 * lowest processor number gets it.
1177 *
1178 * The priority of a CPU is controlled by a special per-CPU
1179 * VIC priority register which is 3 bits wide 0 being lowest
1180 * and 7 highest priority..
1181 *
1182 * Therefore we subtract the average number of interrupts from
1183 * the number we've fielded. If this number is negative, we
1184 * lower the activity count and if it is positive, we raise
1185 * it.
1186 *
1187 * I'm afraid this still leads to odd looking interrupt counts:
1188 * the totals are all roughly equal, but the individual ones
1189 * look rather skewed.
1190 *
1191 * FIXME: This algorithm is total crap when mixed with SMP
1192 * affinity code since we now try to even up the interrupt
1193 * counts when an affinity binding is keeping them on a
1194 * particular CPU*/
1195 weight = (vic_intr_count[cpu] * voyager_extended_cpus
1196 - vic_intr_total) >> 4;
1197 weight += 4;
1198 if (weight > 7)
1199 weight = 7;
1200 if (weight < 0)
1201 weight = 0;
1202
1203 outb((__u8) weight, VIC_PRIORITY_REGISTER);
1204
1205 #ifdef VOYAGER_DEBUG
1206 if ((vic_tick[cpu] & 0xFFF) == 0) {
1207 /* print this message roughly every 25 secs */
1208 printk("VOYAGER SMP: vic_tick[%d] = %lu, weight = %ld\n",
1209 cpu, vic_tick[cpu], weight);
1210 }
1211 #endif
1212 }
1213
1214 /* setup the profiling timer */
setup_profiling_timer(unsigned int multiplier)1215 int setup_profiling_timer(unsigned int multiplier)
1216 {
1217 int i;
1218
1219 if ((!multiplier))
1220 return -EINVAL;
1221
1222 /*
1223 * Set the new multiplier for each CPU. CPUs don't start using the
1224 * new values until the next timer interrupt in which they do process
1225 * accounting.
1226 */
1227 for (i = 0; i < nr_cpu_ids; ++i)
1228 per_cpu(prof_multiplier, i) = multiplier;
1229
1230 return 0;
1231 }
1232
1233 /* This is a bit of a mess, but forced on us by the genirq changes
1234 * there's no genirq handler that really does what voyager wants
1235 * so hack it up with the simple IRQ handler */
handle_vic_irq(unsigned int irq,struct irq_desc * desc)1236 static void handle_vic_irq(unsigned int irq, struct irq_desc *desc)
1237 {
1238 before_handle_vic_irq(irq);
1239 handle_simple_irq(irq, desc);
1240 after_handle_vic_irq(irq);
1241 }
1242
1243 /* The CPIs are handled in the per cpu 8259s, so they must be
1244 * enabled to be received: FIX: enabling the CPIs in the early
1245 * boot sequence interferes with bug checking; enable them later
1246 * on in smp_init */
1247 #define VIC_SET_GATE(cpi, vector) \
1248 set_intr_gate((cpi) + VIC_DEFAULT_CPI_BASE, (vector))
1249 #define QIC_SET_GATE(cpi, vector) \
1250 set_intr_gate((cpi) + QIC_DEFAULT_CPI_BASE, (vector))
1251
voyager_smp_intr_init(void)1252 void __init voyager_smp_intr_init(void)
1253 {
1254 int i;
1255
1256 /* initialize the per cpu irq mask to all disabled */
1257 for (i = 0; i < nr_cpu_ids; i++)
1258 vic_irq_mask[i] = 0xFFFF;
1259
1260 VIC_SET_GATE(VIC_CPI_LEVEL0, vic_cpi_interrupt);
1261
1262 VIC_SET_GATE(VIC_SYS_INT, vic_sys_interrupt);
1263 VIC_SET_GATE(VIC_CMN_INT, vic_cmn_interrupt);
1264
1265 QIC_SET_GATE(QIC_TIMER_CPI, qic_timer_interrupt);
1266 QIC_SET_GATE(QIC_INVALIDATE_CPI, qic_invalidate_interrupt);
1267 QIC_SET_GATE(QIC_RESCHEDULE_CPI, qic_reschedule_interrupt);
1268 QIC_SET_GATE(QIC_ENABLE_IRQ_CPI, qic_enable_irq_interrupt);
1269 QIC_SET_GATE(QIC_CALL_FUNCTION_CPI, qic_call_function_interrupt);
1270
1271 /* now put the VIC descriptor into the first 48 IRQs
1272 *
1273 * This is for later: first 16 correspond to PC IRQs; next 16
1274 * are Primary MC IRQs and final 16 are Secondary MC IRQs */
1275 for (i = 0; i < 48; i++)
1276 set_irq_chip_and_handler(i, &vic_chip, handle_vic_irq);
1277 }
1278
1279 /* send a CPI at level cpi to a set of cpus in cpuset (set 1 bit per
1280 * processor to receive CPI */
send_CPI(__u32 cpuset,__u8 cpi)1281 static void send_CPI(__u32 cpuset, __u8 cpi)
1282 {
1283 int cpu;
1284 __u32 quad_cpuset = (cpuset & voyager_quad_processors);
1285
1286 if (cpi < VIC_START_FAKE_CPI) {
1287 /* fake CPI are only used for booting, so send to the
1288 * extended quads as well---Quads must be VIC booted */
1289 outb((__u8) (cpuset), VIC_CPI_Registers[cpi]);
1290 return;
1291 }
1292 if (quad_cpuset)
1293 send_QIC_CPI(quad_cpuset, cpi);
1294 cpuset &= ~quad_cpuset;
1295 cpuset &= 0xff; /* only first 8 CPUs vaild for VIC CPI */
1296 if (cpuset == 0)
1297 return;
1298 for_each_online_cpu(cpu) {
1299 if (cpuset & (1 << cpu))
1300 set_bit(cpi, &vic_cpi_mailbox[cpu]);
1301 }
1302 if (cpuset)
1303 outb((__u8) cpuset, VIC_CPI_Registers[VIC_CPI_LEVEL0]);
1304 }
1305
1306 /* Acknowledge receipt of CPI in the QIC, clear in QIC hardware and
1307 * set the cache line to shared by reading it.
1308 *
1309 * DON'T make this inline otherwise the cache line read will be
1310 * optimised away
1311 * */
ack_QIC_CPI(__u8 cpi)1312 static int ack_QIC_CPI(__u8 cpi)
1313 {
1314 __u8 cpu = hard_smp_processor_id();
1315
1316 cpi &= 7;
1317
1318 outb(1 << cpi, QIC_INTERRUPT_CLEAR1);
1319 return voyager_quad_cpi_addr[cpu]->qic_cpi[cpi].cpi;
1320 }
1321
ack_special_QIC_CPI(__u8 cpi)1322 static void ack_special_QIC_CPI(__u8 cpi)
1323 {
1324 switch (cpi) {
1325 case VIC_CMN_INT:
1326 outb(QIC_CMN_INT, QIC_INTERRUPT_CLEAR0);
1327 break;
1328 case VIC_SYS_INT:
1329 outb(QIC_SYS_INT, QIC_INTERRUPT_CLEAR0);
1330 break;
1331 }
1332 /* also clear at the VIC, just in case (nop for non-extended proc) */
1333 ack_VIC_CPI(cpi);
1334 }
1335
1336 /* Acknowledge receipt of CPI in the VIC (essentially an EOI) */
ack_VIC_CPI(__u8 cpi)1337 static void ack_VIC_CPI(__u8 cpi)
1338 {
1339 #ifdef VOYAGER_DEBUG
1340 unsigned long flags;
1341 __u16 isr;
1342 __u8 cpu = smp_processor_id();
1343
1344 local_irq_save(flags);
1345 isr = vic_read_isr();
1346 if ((isr & (1 << (cpi & 7))) == 0) {
1347 printk("VOYAGER SMP: CPU%d lost CPI%d\n", cpu, cpi);
1348 }
1349 #endif
1350 /* send specific EOI; the two system interrupts have
1351 * bit 4 set for a separate vector but behave as the
1352 * corresponding 3 bit intr */
1353 outb_p(0x60 | (cpi & 7), 0x20);
1354
1355 #ifdef VOYAGER_DEBUG
1356 if ((vic_read_isr() & (1 << (cpi & 7))) != 0) {
1357 printk("VOYAGER SMP: CPU%d still asserting CPI%d\n", cpu, cpi);
1358 }
1359 local_irq_restore(flags);
1360 #endif
1361 }
1362
1363 /* cribbed with thanks from irq.c */
1364 #define __byte(x,y) (((unsigned char *)&(y))[x])
1365 #define cached_21(cpu) (__byte(0,vic_irq_mask[cpu]))
1366 #define cached_A1(cpu) (__byte(1,vic_irq_mask[cpu]))
1367
startup_vic_irq(unsigned int irq)1368 static unsigned int startup_vic_irq(unsigned int irq)
1369 {
1370 unmask_vic_irq(irq);
1371
1372 return 0;
1373 }
1374
1375 /* The enable and disable routines. This is where we run into
1376 * conflicting architectural philosophy. Fundamentally, the voyager
1377 * architecture does not expect to have to disable interrupts globally
1378 * (the IRQ controllers belong to each CPU). The processor masquerade
1379 * which is used to start the system shouldn't be used in a running OS
1380 * since it will cause great confusion if two separate CPUs drive to
1381 * the same IRQ controller (I know, I've tried it).
1382 *
1383 * The solution is a variant on the NCR lazy SPL design:
1384 *
1385 * 1) To disable an interrupt, do nothing (other than set the
1386 * IRQ_DISABLED flag). This dares the interrupt actually to arrive.
1387 *
1388 * 2) If the interrupt dares to come in, raise the local mask against
1389 * it (this will result in all the CPU masks being raised
1390 * eventually).
1391 *
1392 * 3) To enable the interrupt, lower the mask on the local CPU and
1393 * broadcast an Interrupt enable CPI which causes all other CPUs to
1394 * adjust their masks accordingly. */
1395
unmask_vic_irq(unsigned int irq)1396 static void unmask_vic_irq(unsigned int irq)
1397 {
1398 /* linux doesn't to processor-irq affinity, so enable on
1399 * all CPUs we know about */
1400 int cpu = smp_processor_id(), real_cpu;
1401 __u16 mask = (1 << irq);
1402 __u32 processorList = 0;
1403 unsigned long flags;
1404
1405 VDEBUG(("VOYAGER: unmask_vic_irq(%d) CPU%d affinity 0x%lx\n",
1406 irq, cpu, cpu_irq_affinity[cpu]));
1407 spin_lock_irqsave(&vic_irq_lock, flags);
1408 for_each_online_cpu(real_cpu) {
1409 if (!(voyager_extended_vic_processors & (1 << real_cpu)))
1410 continue;
1411 if (!(cpu_irq_affinity[real_cpu] & mask)) {
1412 /* irq has no affinity for this CPU, ignore */
1413 continue;
1414 }
1415 if (real_cpu == cpu) {
1416 enable_local_vic_irq(irq);
1417 } else if (vic_irq_mask[real_cpu] & mask) {
1418 vic_irq_enable_mask[real_cpu] |= mask;
1419 processorList |= (1 << real_cpu);
1420 }
1421 }
1422 spin_unlock_irqrestore(&vic_irq_lock, flags);
1423 if (processorList)
1424 send_CPI(processorList, VIC_ENABLE_IRQ_CPI);
1425 }
1426
mask_vic_irq(unsigned int irq)1427 static void mask_vic_irq(unsigned int irq)
1428 {
1429 /* lazy disable, do nothing */
1430 }
1431
enable_local_vic_irq(unsigned int irq)1432 static void enable_local_vic_irq(unsigned int irq)
1433 {
1434 __u8 cpu = smp_processor_id();
1435 __u16 mask = ~(1 << irq);
1436 __u16 old_mask = vic_irq_mask[cpu];
1437
1438 vic_irq_mask[cpu] &= mask;
1439 if (vic_irq_mask[cpu] == old_mask)
1440 return;
1441
1442 VDEBUG(("VOYAGER DEBUG: Enabling irq %d in hardware on CPU %d\n",
1443 irq, cpu));
1444
1445 if (irq & 8) {
1446 outb_p(cached_A1(cpu), 0xA1);
1447 (void)inb_p(0xA1);
1448 } else {
1449 outb_p(cached_21(cpu), 0x21);
1450 (void)inb_p(0x21);
1451 }
1452 }
1453
disable_local_vic_irq(unsigned int irq)1454 static void disable_local_vic_irq(unsigned int irq)
1455 {
1456 __u8 cpu = smp_processor_id();
1457 __u16 mask = (1 << irq);
1458 __u16 old_mask = vic_irq_mask[cpu];
1459
1460 if (irq == 7)
1461 return;
1462
1463 vic_irq_mask[cpu] |= mask;
1464 if (old_mask == vic_irq_mask[cpu])
1465 return;
1466
1467 VDEBUG(("VOYAGER DEBUG: Disabling irq %d in hardware on CPU %d\n",
1468 irq, cpu));
1469
1470 if (irq & 8) {
1471 outb_p(cached_A1(cpu), 0xA1);
1472 (void)inb_p(0xA1);
1473 } else {
1474 outb_p(cached_21(cpu), 0x21);
1475 (void)inb_p(0x21);
1476 }
1477 }
1478
1479 /* The VIC is level triggered, so the ack can only be issued after the
1480 * interrupt completes. However, we do Voyager lazy interrupt
1481 * handling here: It is an extremely expensive operation to mask an
1482 * interrupt in the vic, so we merely set a flag (IRQ_DISABLED). If
1483 * this interrupt actually comes in, then we mask and ack here to push
1484 * the interrupt off to another CPU */
before_handle_vic_irq(unsigned int irq)1485 static void before_handle_vic_irq(unsigned int irq)
1486 {
1487 irq_desc_t *desc = irq_to_desc(irq);
1488 __u8 cpu = smp_processor_id();
1489
1490 _raw_spin_lock(&vic_irq_lock);
1491 vic_intr_total++;
1492 vic_intr_count[cpu]++;
1493
1494 if (!(cpu_irq_affinity[cpu] & (1 << irq))) {
1495 /* The irq is not in our affinity mask, push it off
1496 * onto another CPU */
1497 VDEBUG(("VOYAGER DEBUG: affinity triggered disable of irq %d "
1498 "on cpu %d\n", irq, cpu));
1499 disable_local_vic_irq(irq);
1500 /* set IRQ_INPROGRESS to prevent the handler in irq.c from
1501 * actually calling the interrupt routine */
1502 desc->status |= IRQ_REPLAY | IRQ_INPROGRESS;
1503 } else if (desc->status & IRQ_DISABLED) {
1504 /* Damn, the interrupt actually arrived, do the lazy
1505 * disable thing. The interrupt routine in irq.c will
1506 * not handle a IRQ_DISABLED interrupt, so nothing more
1507 * need be done here */
1508 VDEBUG(("VOYAGER DEBUG: lazy disable of irq %d on CPU %d\n",
1509 irq, cpu));
1510 disable_local_vic_irq(irq);
1511 desc->status |= IRQ_REPLAY;
1512 } else {
1513 desc->status &= ~IRQ_REPLAY;
1514 }
1515
1516 _raw_spin_unlock(&vic_irq_lock);
1517 }
1518
1519 /* Finish the VIC interrupt: basically mask */
after_handle_vic_irq(unsigned int irq)1520 static void after_handle_vic_irq(unsigned int irq)
1521 {
1522 irq_desc_t *desc = irq_to_desc(irq);
1523
1524 _raw_spin_lock(&vic_irq_lock);
1525 {
1526 unsigned int status = desc->status & ~IRQ_INPROGRESS;
1527 #ifdef VOYAGER_DEBUG
1528 __u16 isr;
1529 #endif
1530
1531 desc->status = status;
1532 if ((status & IRQ_DISABLED))
1533 disable_local_vic_irq(irq);
1534 #ifdef VOYAGER_DEBUG
1535 /* DEBUG: before we ack, check what's in progress */
1536 isr = vic_read_isr();
1537 if ((isr & (1 << irq) && !(status & IRQ_REPLAY)) == 0) {
1538 int i;
1539 __u8 cpu = smp_processor_id();
1540 __u8 real_cpu;
1541 int mask; /* Um... initialize me??? --RR */
1542
1543 printk("VOYAGER SMP: CPU%d lost interrupt %d\n",
1544 cpu, irq);
1545 for_each_possible_cpu(real_cpu, mask) {
1546
1547 outb(VIC_CPU_MASQUERADE_ENABLE | real_cpu,
1548 VIC_PROCESSOR_ID);
1549 isr = vic_read_isr();
1550 if (isr & (1 << irq)) {
1551 printk
1552 ("VOYAGER SMP: CPU%d ack irq %d\n",
1553 real_cpu, irq);
1554 ack_vic_irq(irq);
1555 }
1556 outb(cpu, VIC_PROCESSOR_ID);
1557 }
1558 }
1559 #endif /* VOYAGER_DEBUG */
1560 /* as soon as we ack, the interrupt is eligible for
1561 * receipt by another CPU so everything must be in
1562 * order here */
1563 ack_vic_irq(irq);
1564 if (status & IRQ_REPLAY) {
1565 /* replay is set if we disable the interrupt
1566 * in the before_handle_vic_irq() routine, so
1567 * clear the in progress bit here to allow the
1568 * next CPU to handle this correctly */
1569 desc->status &= ~(IRQ_REPLAY | IRQ_INPROGRESS);
1570 }
1571 #ifdef VOYAGER_DEBUG
1572 isr = vic_read_isr();
1573 if ((isr & (1 << irq)) != 0)
1574 printk("VOYAGER SMP: after_handle_vic_irq() after "
1575 "ack irq=%d, isr=0x%x\n", irq, isr);
1576 #endif /* VOYAGER_DEBUG */
1577 }
1578 _raw_spin_unlock(&vic_irq_lock);
1579
1580 /* All code after this point is out of the main path - the IRQ
1581 * may be intercepted by another CPU if reasserted */
1582 }
1583
1584 /* Linux processor - interrupt affinity manipulations.
1585 *
1586 * For each processor, we maintain a 32 bit irq affinity mask.
1587 * Initially it is set to all 1's so every processor accepts every
1588 * interrupt. In this call, we change the processor's affinity mask:
1589 *
1590 * Change from enable to disable:
1591 *
1592 * If the interrupt ever comes in to the processor, we will disable it
1593 * and ack it to push it off to another CPU, so just accept the mask here.
1594 *
1595 * Change from disable to enable:
1596 *
1597 * change the mask and then do an interrupt enable CPI to re-enable on
1598 * the selected processors */
1599
set_vic_irq_affinity(unsigned int irq,const struct cpumask * mask)1600 void set_vic_irq_affinity(unsigned int irq, const struct cpumask *mask)
1601 {
1602 /* Only extended processors handle interrupts */
1603 unsigned long real_mask;
1604 unsigned long irq_mask = 1 << irq;
1605 int cpu;
1606
1607 real_mask = cpus_addr(*mask)[0] & voyager_extended_vic_processors;
1608
1609 if (cpus_addr(*mask)[0] == 0)
1610 /* can't have no CPUs to accept the interrupt -- extremely
1611 * bad things will happen */
1612 return;
1613
1614 if (irq == 0)
1615 /* can't change the affinity of the timer IRQ. This
1616 * is due to the constraint in the voyager
1617 * architecture that the CPI also comes in on and IRQ
1618 * line and we have chosen IRQ0 for this. If you
1619 * raise the mask on this interrupt, the processor
1620 * will no-longer be able to accept VIC CPIs */
1621 return;
1622
1623 if (irq >= 32)
1624 /* You can only have 32 interrupts in a voyager system
1625 * (and 32 only if you have a secondary microchannel
1626 * bus) */
1627 return;
1628
1629 for_each_online_cpu(cpu) {
1630 unsigned long cpu_mask = 1 << cpu;
1631
1632 if (cpu_mask & real_mask) {
1633 /* enable the interrupt for this cpu */
1634 cpu_irq_affinity[cpu] |= irq_mask;
1635 } else {
1636 /* disable the interrupt for this cpu */
1637 cpu_irq_affinity[cpu] &= ~irq_mask;
1638 }
1639 }
1640 /* this is magic, we now have the correct affinity maps, so
1641 * enable the interrupt. This will send an enable CPI to
1642 * those CPUs who need to enable it in their local masks,
1643 * causing them to correct for the new affinity . If the
1644 * interrupt is currently globally disabled, it will simply be
1645 * disabled again as it comes in (voyager lazy disable). If
1646 * the affinity map is tightened to disable the interrupt on a
1647 * cpu, it will be pushed off when it comes in */
1648 unmask_vic_irq(irq);
1649 }
1650
ack_vic_irq(unsigned int irq)1651 static void ack_vic_irq(unsigned int irq)
1652 {
1653 if (irq & 8) {
1654 outb(0x62, 0x20); /* Specific EOI to cascade */
1655 outb(0x60 | (irq & 7), 0xA0);
1656 } else {
1657 outb(0x60 | (irq & 7), 0x20);
1658 }
1659 }
1660
1661 /* enable the CPIs. In the VIC, the CPIs are delivered by the 8259
1662 * but are not vectored by it. This means that the 8259 mask must be
1663 * lowered to receive them */
vic_enable_cpi(void)1664 static __init void vic_enable_cpi(void)
1665 {
1666 __u8 cpu = smp_processor_id();
1667
1668 /* just take a copy of the current mask (nop for boot cpu) */
1669 vic_irq_mask[cpu] = vic_irq_mask[boot_cpu_id];
1670
1671 enable_local_vic_irq(VIC_CPI_LEVEL0);
1672 enable_local_vic_irq(VIC_CPI_LEVEL1);
1673 /* for sys int and cmn int */
1674 enable_local_vic_irq(7);
1675
1676 if (is_cpu_quad()) {
1677 outb(QIC_DEFAULT_MASK0, QIC_MASK_REGISTER0);
1678 outb(QIC_CPI_ENABLE, QIC_MASK_REGISTER1);
1679 VDEBUG(("VOYAGER SMP: QIC ENABLE CPI: CPU%d: MASK 0x%x\n",
1680 cpu, QIC_CPI_ENABLE));
1681 }
1682
1683 VDEBUG(("VOYAGER SMP: ENABLE CPI: CPU%d: MASK 0x%x\n",
1684 cpu, vic_irq_mask[cpu]));
1685 }
1686
voyager_smp_dump()1687 void voyager_smp_dump()
1688 {
1689 int old_cpu = smp_processor_id(), cpu;
1690
1691 /* dump the interrupt masks of each processor */
1692 for_each_online_cpu(cpu) {
1693 __u16 imr, isr, irr;
1694 unsigned long flags;
1695
1696 local_irq_save(flags);
1697 outb(VIC_CPU_MASQUERADE_ENABLE | cpu, VIC_PROCESSOR_ID);
1698 imr = (inb(0xa1) << 8) | inb(0x21);
1699 outb(0x0a, 0xa0);
1700 irr = inb(0xa0) << 8;
1701 outb(0x0a, 0x20);
1702 irr |= inb(0x20);
1703 outb(0x0b, 0xa0);
1704 isr = inb(0xa0) << 8;
1705 outb(0x0b, 0x20);
1706 isr |= inb(0x20);
1707 outb(old_cpu, VIC_PROCESSOR_ID);
1708 local_irq_restore(flags);
1709 printk("\tCPU%d: mask=0x%x, IMR=0x%x, IRR=0x%x, ISR=0x%x\n",
1710 cpu, vic_irq_mask[cpu], imr, irr, isr);
1711 #if 0
1712 /* These lines are put in to try to unstick an un ack'd irq */
1713 if (isr != 0) {
1714 int irq;
1715 for (irq = 0; irq < 16; irq++) {
1716 if (isr & (1 << irq)) {
1717 printk("\tCPU%d: ack irq %d\n",
1718 cpu, irq);
1719 local_irq_save(flags);
1720 outb(VIC_CPU_MASQUERADE_ENABLE | cpu,
1721 VIC_PROCESSOR_ID);
1722 ack_vic_irq(irq);
1723 outb(old_cpu, VIC_PROCESSOR_ID);
1724 local_irq_restore(flags);
1725 }
1726 }
1727 }
1728 #endif
1729 }
1730 }
1731
smp_voyager_power_off(void * dummy)1732 void smp_voyager_power_off(void *dummy)
1733 {
1734 if (smp_processor_id() == boot_cpu_id)
1735 voyager_power_off();
1736 else
1737 smp_stop_cpu_function(NULL);
1738 }
1739
voyager_smp_prepare_cpus(unsigned int max_cpus)1740 static void __init voyager_smp_prepare_cpus(unsigned int max_cpus)
1741 {
1742 /* FIXME: ignore max_cpus for now */
1743 smp_boot_cpus();
1744 }
1745
voyager_smp_prepare_boot_cpu(void)1746 static void __cpuinit voyager_smp_prepare_boot_cpu(void)
1747 {
1748 init_gdt(smp_processor_id());
1749 switch_to_new_gdt();
1750
1751 cpu_online_map = cpumask_of_cpu(smp_processor_id());
1752 cpu_callout_map = cpumask_of_cpu(smp_processor_id());
1753 cpu_callin_map = CPU_MASK_NONE;
1754 cpu_present_map = cpumask_of_cpu(smp_processor_id());
1755
1756 }
1757
voyager_cpu_up(unsigned int cpu)1758 static int __cpuinit voyager_cpu_up(unsigned int cpu)
1759 {
1760 /* This only works at boot for x86. See "rewrite" above. */
1761 if (cpu_isset(cpu, smp_commenced_mask))
1762 return -ENOSYS;
1763
1764 /* In case one didn't come up */
1765 if (!cpu_isset(cpu, cpu_callin_map))
1766 return -EIO;
1767 /* Unleash the CPU! */
1768 cpu_set(cpu, smp_commenced_mask);
1769 while (!cpu_online(cpu))
1770 mb();
1771 return 0;
1772 }
1773
voyager_smp_cpus_done(unsigned int max_cpus)1774 static void __init voyager_smp_cpus_done(unsigned int max_cpus)
1775 {
1776 zap_low_mappings();
1777 }
1778
smp_setup_processor_id(void)1779 void __init smp_setup_processor_id(void)
1780 {
1781 current_thread_info()->cpu = hard_smp_processor_id();
1782 x86_write_percpu(cpu_number, hard_smp_processor_id());
1783 }
1784
voyager_send_call_func(const struct cpumask * callmask)1785 static void voyager_send_call_func(const struct cpumask *callmask)
1786 {
1787 __u32 mask = cpus_addr(*callmask)[0] & ~(1 << smp_processor_id());
1788 send_CPI(mask, VIC_CALL_FUNCTION_CPI);
1789 }
1790
voyager_send_call_func_single(int cpu)1791 static void voyager_send_call_func_single(int cpu)
1792 {
1793 send_CPI(1 << cpu, VIC_CALL_FUNCTION_SINGLE_CPI);
1794 }
1795
1796 struct smp_ops smp_ops = {
1797 .smp_prepare_boot_cpu = voyager_smp_prepare_boot_cpu,
1798 .smp_prepare_cpus = voyager_smp_prepare_cpus,
1799 .cpu_up = voyager_cpu_up,
1800 .smp_cpus_done = voyager_smp_cpus_done,
1801
1802 .smp_send_stop = voyager_smp_send_stop,
1803 .smp_send_reschedule = voyager_smp_send_reschedule,
1804
1805 .send_call_func_ipi = voyager_send_call_func,
1806 .send_call_func_single_ipi = voyager_send_call_func_single,
1807 };
1808