1 /*
2 * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
7 * any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59
16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called COPYING.
20 */
21 #ifndef IOATDMA_H
22 #define IOATDMA_H
23
24 #include <linux/dmaengine.h>
25 #include "ioatdma_hw.h"
26 #include <linux/init.h>
27 #include <linux/dmapool.h>
28 #include <linux/cache.h>
29 #include <linux/pci_ids.h>
30 #include <net/tcp.h>
31
32 #define IOAT_DMA_VERSION "3.64"
33
34 enum ioat_interrupt {
35 none = 0,
36 msix_multi_vector = 1,
37 msix_single_vector = 2,
38 msi = 3,
39 intx = 4,
40 };
41
42 #define IOAT_LOW_COMPLETION_MASK 0xffffffc0
43 #define IOAT_DMA_DCA_ANY_CPU ~0
44 #define IOAT_WATCHDOG_PERIOD (2 * HZ)
45
46
47 /**
48 * struct ioatdma_device - internal representation of a IOAT device
49 * @pdev: PCI-Express device
50 * @reg_base: MMIO register space base address
51 * @dma_pool: for allocating DMA descriptors
52 * @common: embedded struct dma_device
53 * @version: version of ioatdma device
54 * @irq_mode: which style irq to use
55 * @msix_entries: irq handlers
56 * @idx: per channel data
57 */
58
59 struct ioatdma_device {
60 struct pci_dev *pdev;
61 void __iomem *reg_base;
62 struct pci_pool *dma_pool;
63 struct pci_pool *completion_pool;
64 struct dma_device common;
65 u8 version;
66 enum ioat_interrupt irq_mode;
67 struct delayed_work work;
68 struct msix_entry msix_entries[4];
69 struct ioat_dma_chan *idx[4];
70 };
71
72 /**
73 * struct ioat_dma_chan - internal representation of a DMA channel
74 */
75 struct ioat_dma_chan {
76
77 void __iomem *reg_base;
78
79 dma_cookie_t completed_cookie;
80 unsigned long last_completion;
81 unsigned long last_completion_time;
82
83 size_t xfercap; /* XFERCAP register value expanded out */
84
85 spinlock_t cleanup_lock;
86 spinlock_t desc_lock;
87 struct list_head free_desc;
88 struct list_head used_desc;
89 unsigned long watchdog_completion;
90 int watchdog_tcp_cookie;
91 u32 watchdog_last_tcp_cookie;
92 struct delayed_work work;
93
94 int pending;
95 int dmacount;
96 int desccount;
97
98 struct ioatdma_device *device;
99 struct dma_chan common;
100
101 dma_addr_t completion_addr;
102 union {
103 u64 full; /* HW completion writeback */
104 struct {
105 u32 low;
106 u32 high;
107 };
108 } *completion_virt;
109 unsigned long last_compl_desc_addr_hw;
110 struct tasklet_struct cleanup_task;
111 };
112
113 /* wrapper around hardware descriptor format + additional software fields */
114
115 /**
116 * struct ioat_desc_sw - wrapper around hardware descriptor
117 * @hw: hardware DMA descriptor
118 * @node: this descriptor will either be on the free list,
119 * or attached to a transaction list (async_tx.tx_list)
120 * @tx_cnt: number of descriptors required to complete the transaction
121 * @async_tx: the generic software descriptor for all engines
122 */
123 struct ioat_desc_sw {
124 struct ioat_dma_descriptor *hw;
125 struct list_head node;
126 int tx_cnt;
127 size_t len;
128 dma_addr_t src;
129 dma_addr_t dst;
130 struct dma_async_tx_descriptor async_tx;
131 };
132
ioat_set_tcp_copy_break(struct ioatdma_device * dev)133 static inline void ioat_set_tcp_copy_break(struct ioatdma_device *dev)
134 {
135 #ifdef CONFIG_NET_DMA
136 switch (dev->version) {
137 case IOAT_VER_1_2:
138 sysctl_tcp_dma_copybreak = 4096;
139 break;
140 case IOAT_VER_2_0:
141 sysctl_tcp_dma_copybreak = 2048;
142 break;
143 case IOAT_VER_3_0:
144 sysctl_tcp_dma_copybreak = 262144;
145 break;
146 }
147 #endif
148 }
149
150 #if defined(CONFIG_INTEL_IOATDMA) || defined(CONFIG_INTEL_IOATDMA_MODULE)
151 struct ioatdma_device *ioat_dma_probe(struct pci_dev *pdev,
152 void __iomem *iobase);
153 void ioat_dma_remove(struct ioatdma_device *device);
154 struct dca_provider *ioat_dca_init(struct pci_dev *pdev, void __iomem *iobase);
155 struct dca_provider *ioat2_dca_init(struct pci_dev *pdev, void __iomem *iobase);
156 struct dca_provider *ioat3_dca_init(struct pci_dev *pdev, void __iomem *iobase);
157 #else
158 #define ioat_dma_probe(pdev, iobase) NULL
159 #define ioat_dma_remove(device) do { } while (0)
160 #define ioat_dca_init(pdev, iobase) NULL
161 #define ioat2_dca_init(pdev, iobase) NULL
162 #define ioat3_dca_init(pdev, iobase) NULL
163 #endif
164
165 #endif /* IOATDMA_H */
166