1 /***************************************************************************/
2
3 /*
4 * pit.c -- Freescale ColdFire PIT timer. Currently this type of
5 * hardware timer only exists in the Freescale ColdFire
6 * 5270/5271, 5282 and 5208 CPUs. No doubt newer ColdFire
7 * family members will probably use it too.
8 *
9 * Copyright (C) 1999-2008, Greg Ungerer (gerg@snapgear.com)
10 * Copyright (C) 2001-2004, SnapGear Inc. (www.snapgear.com)
11 */
12
13 /***************************************************************************/
14
15 #include <linux/kernel.h>
16 #include <linux/sched.h>
17 #include <linux/param.h>
18 #include <linux/init.h>
19 #include <linux/interrupt.h>
20 #include <linux/irq.h>
21 #include <linux/clockchips.h>
22 #include <asm/machdep.h>
23 #include <asm/io.h>
24 #include <asm/coldfire.h>
25 #include <asm/mcfpit.h>
26 #include <asm/mcfsim.h>
27
28 /***************************************************************************/
29
30 /*
31 * By default use timer1 as the system clock timer.
32 */
33 #define FREQ ((MCF_CLK / 2) / 64)
34 #define TA(a) (MCF_IPSBAR + MCFPIT_BASE1 + (a))
35 #define INTC0 (MCF_IPSBAR + MCFICM_INTC0)
36 #define PIT_CYCLES_PER_JIFFY (FREQ / HZ)
37
38 static u32 pit_cnt;
39
40 /*
41 * Initialize the PIT timer.
42 *
43 * This is also called after resume to bring the PIT into operation again.
44 */
45
init_cf_pit_timer(enum clock_event_mode mode,struct clock_event_device * evt)46 static void init_cf_pit_timer(enum clock_event_mode mode,
47 struct clock_event_device *evt)
48 {
49 switch (mode) {
50 case CLOCK_EVT_MODE_PERIODIC:
51
52 __raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR));
53 __raw_writew(PIT_CYCLES_PER_JIFFY, TA(MCFPIT_PMR));
54 __raw_writew(MCFPIT_PCSR_EN | MCFPIT_PCSR_PIE | \
55 MCFPIT_PCSR_OVW | MCFPIT_PCSR_RLD | \
56 MCFPIT_PCSR_CLK64, TA(MCFPIT_PCSR));
57 break;
58
59 case CLOCK_EVT_MODE_SHUTDOWN:
60 case CLOCK_EVT_MODE_UNUSED:
61
62 __raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR));
63 break;
64
65 case CLOCK_EVT_MODE_ONESHOT:
66
67 __raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR));
68 __raw_writew(MCFPIT_PCSR_EN | MCFPIT_PCSR_PIE | \
69 MCFPIT_PCSR_OVW | MCFPIT_PCSR_CLK64, \
70 TA(MCFPIT_PCSR));
71 break;
72
73 case CLOCK_EVT_MODE_RESUME:
74 /* Nothing to do here */
75 break;
76 }
77 }
78
79 /*
80 * Program the next event in oneshot mode
81 *
82 * Delta is given in PIT ticks
83 */
cf_pit_next_event(unsigned long delta,struct clock_event_device * evt)84 static int cf_pit_next_event(unsigned long delta,
85 struct clock_event_device *evt)
86 {
87 __raw_writew(delta, TA(MCFPIT_PMR));
88 return 0;
89 }
90
91 struct clock_event_device cf_pit_clockevent = {
92 .name = "pit",
93 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
94 .set_mode = init_cf_pit_timer,
95 .set_next_event = cf_pit_next_event,
96 .shift = 32,
97 .irq = MCFINT_VECBASE + MCFINT_PIT1,
98 };
99
100
101
102 /***************************************************************************/
103
pit_tick(int irq,void * dummy)104 static irqreturn_t pit_tick(int irq, void *dummy)
105 {
106 struct clock_event_device *evt = &cf_pit_clockevent;
107 u16 pcsr;
108
109 /* Reset the ColdFire timer */
110 pcsr = __raw_readw(TA(MCFPIT_PCSR));
111 __raw_writew(pcsr | MCFPIT_PCSR_PIF, TA(MCFPIT_PCSR));
112
113 pit_cnt += PIT_CYCLES_PER_JIFFY;
114 evt->event_handler(evt);
115 return IRQ_HANDLED;
116 }
117
118 /***************************************************************************/
119
120 static struct irqaction pit_irq = {
121 .name = "timer",
122 .flags = IRQF_DISABLED | IRQF_TIMER,
123 .handler = pit_tick,
124 };
125
126 /***************************************************************************/
127
pit_read_clk(void)128 static cycle_t pit_read_clk(void)
129 {
130 unsigned long flags;
131 u32 cycles;
132 u16 pcntr;
133
134 local_irq_save(flags);
135 pcntr = __raw_readw(TA(MCFPIT_PCNTR));
136 cycles = pit_cnt;
137 local_irq_restore(flags);
138
139 return cycles + PIT_CYCLES_PER_JIFFY - pcntr;
140 }
141
142 /***************************************************************************/
143
144 static struct clocksource pit_clk = {
145 .name = "pit",
146 .rating = 100,
147 .read = pit_read_clk,
148 .shift = 20,
149 .mask = CLOCKSOURCE_MASK(32),
150 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
151 };
152
153 /***************************************************************************/
154
hw_timer_init(void)155 void hw_timer_init(void)
156 {
157 u32 imr;
158
159 cf_pit_clockevent.cpumask = cpumask_of(smp_processor_id());
160 cf_pit_clockevent.mult = div_sc(FREQ, NSEC_PER_SEC, 32);
161 cf_pit_clockevent.max_delta_ns =
162 clockevent_delta2ns(0xFFFF, &cf_pit_clockevent);
163 cf_pit_clockevent.min_delta_ns =
164 clockevent_delta2ns(0x3f, &cf_pit_clockevent);
165 clockevents_register_device(&cf_pit_clockevent);
166
167 setup_irq(MCFINT_VECBASE + MCFINT_PIT1, &pit_irq);
168
169 __raw_writeb(ICR_INTRCONF, INTC0 + MCFINTC_ICR0 + MCFINT_PIT1);
170 imr = __raw_readl(INTC0 + MCFPIT_IMR);
171 imr &= ~MCFPIT_IMR_IBIT;
172 __raw_writel(imr, INTC0 + MCFPIT_IMR);
173
174 pit_clk.mult = clocksource_hz2mult(FREQ, pit_clk.shift);
175 clocksource_register(&pit_clk);
176 }
177
178 /***************************************************************************/
179