1 /* 2 * arch/arm/mach-pxa/include/mach/pxafb.h 3 * 4 * Support for the xscale frame buffer. 5 * 6 * Author: Jean-Frederic Clere 7 * Created: Sep 22, 2003 8 * Copyright: jfclere@sinix.net 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 15 #include <linux/fb.h> 16 #include <mach/regs-lcd.h> 17 18 /* 19 * Supported LCD connections 20 * 21 * bits 0 - 3: for LCD panel type: 22 * 23 * STN - for passive matrix 24 * DSTN - for dual scan passive matrix 25 * TFT - for active matrix 26 * 27 * bits 4 - 9 : for bus width 28 * bits 10-17 : for AC Bias Pin Frequency 29 * bit 18 : for output enable polarity 30 * bit 19 : for pixel clock edge 31 * bit 20 : for output pixel format when base is RGBT16 32 */ 33 #define LCD_CONN_TYPE(_x) ((_x) & 0x0f) 34 #define LCD_CONN_WIDTH(_x) (((_x) >> 4) & 0x1f) 35 36 #define LCD_TYPE_MASK 0xf 37 #define LCD_TYPE_UNKNOWN 0 38 #define LCD_TYPE_MONO_STN 1 39 #define LCD_TYPE_MONO_DSTN 2 40 #define LCD_TYPE_COLOR_STN 3 41 #define LCD_TYPE_COLOR_DSTN 4 42 #define LCD_TYPE_COLOR_TFT 5 43 #define LCD_TYPE_SMART_PANEL 6 44 #define LCD_TYPE_MAX 7 45 46 #define LCD_MONO_STN_4BPP ((4 << 4) | LCD_TYPE_MONO_STN) 47 #define LCD_MONO_STN_8BPP ((8 << 4) | LCD_TYPE_MONO_STN) 48 #define LCD_MONO_DSTN_8BPP ((8 << 4) | LCD_TYPE_MONO_DSTN) 49 #define LCD_COLOR_STN_8BPP ((8 << 4) | LCD_TYPE_COLOR_STN) 50 #define LCD_COLOR_DSTN_16BPP ((16 << 4) | LCD_TYPE_COLOR_DSTN) 51 #define LCD_COLOR_TFT_8BPP ((8 << 4) | LCD_TYPE_COLOR_TFT) 52 #define LCD_COLOR_TFT_16BPP ((16 << 4) | LCD_TYPE_COLOR_TFT) 53 #define LCD_COLOR_TFT_18BPP ((18 << 4) | LCD_TYPE_COLOR_TFT) 54 #define LCD_SMART_PANEL_8BPP ((8 << 4) | LCD_TYPE_SMART_PANEL) 55 #define LCD_SMART_PANEL_16BPP ((16 << 4) | LCD_TYPE_SMART_PANEL) 56 #define LCD_SMART_PANEL_18BPP ((18 << 4) | LCD_TYPE_SMART_PANEL) 57 58 #define LCD_AC_BIAS_FREQ(x) (((x) & 0xff) << 10) 59 #define LCD_BIAS_ACTIVE_HIGH (0 << 18) 60 #define LCD_BIAS_ACTIVE_LOW (1 << 18) 61 #define LCD_PCLK_EDGE_RISE (0 << 19) 62 #define LCD_PCLK_EDGE_FALL (1 << 19) 63 #define LCD_ALTERNATE_MAPPING (1 << 20) 64 65 /* 66 * This structure describes the machine which we are running on. 67 * It is set in linux/arch/arm/mach-pxa/machine_name.c and used in the probe routine 68 * of linux/drivers/video/pxafb.c 69 */ 70 struct pxafb_mode_info { 71 u_long pixclock; 72 73 u_short xres; 74 u_short yres; 75 76 u_char bpp; 77 u_int cmap_greyscale:1, 78 depth:8, 79 unused:23; 80 81 /* Parallel Mode Timing */ 82 u_char hsync_len; 83 u_char left_margin; 84 u_char right_margin; 85 86 u_char vsync_len; 87 u_char upper_margin; 88 u_char lower_margin; 89 u_char sync; 90 91 /* Smart Panel Mode Timing - see PXA27x DM 7.4.15.0.3 for details 92 * Note: 93 * 1. all parameters in nanosecond (ns) 94 * 2. a0cs{rd,wr}_set_hld are controlled by the same register bits 95 * in pxa27x and pxa3xx, initialize them to the same value or 96 * the larger one will be used 97 * 3. same to {rd,wr}_pulse_width 98 * 99 * 4. LCD_PCLK_EDGE_{RISE,FALL} controls the L_PCLK_WR polarity 100 * 5. sync & FB_SYNC_HOR_HIGH_ACT controls the L_LCLK_A0 101 * 6. sync & FB_SYNC_VERT_HIGH_ACT controls the L_LCLK_RD 102 */ 103 unsigned a0csrd_set_hld; /* A0 and CS Setup/Hold Time before/after L_FCLK_RD */ 104 unsigned a0cswr_set_hld; /* A0 and CS Setup/Hold Time before/after L_PCLK_WR */ 105 unsigned wr_pulse_width; /* L_PCLK_WR pulse width */ 106 unsigned rd_pulse_width; /* L_FCLK_RD pulse width */ 107 unsigned cmd_inh_time; /* Command Inhibit time between two writes */ 108 unsigned op_hold_time; /* Output Hold time from L_FCLK_RD negation */ 109 }; 110 111 struct pxafb_mach_info { 112 struct pxafb_mode_info *modes; 113 unsigned int num_modes; 114 115 unsigned int lcd_conn; 116 unsigned long video_mem_size; 117 118 u_int fixed_modes:1, 119 cmap_inverse:1, 120 cmap_static:1, 121 unused:29; 122 123 /* The following should be defined in LCCR0 124 * LCCR0_Act or LCCR0_Pas Active or Passive 125 * LCCR0_Sngl or LCCR0_Dual Single/Dual panel 126 * LCCR0_Mono or LCCR0_Color Mono/Color 127 * LCCR0_4PixMono or LCCR0_8PixMono (in mono single mode) 128 * LCCR0_DMADel(Tcpu) (optional) DMA request delay 129 * 130 * The following should not be defined in LCCR0: 131 * LCCR0_OUM, LCCR0_BM, LCCR0_QDM, LCCR0_DIS, LCCR0_EFM 132 * LCCR0_IUM, LCCR0_SFM, LCCR0_LDM, LCCR0_ENB 133 */ 134 u_int lccr0; 135 /* The following should be defined in LCCR3 136 * LCCR3_OutEnH or LCCR3_OutEnL Output enable polarity 137 * LCCR3_PixRsEdg or LCCR3_PixFlEdg Pixel clock edge type 138 * LCCR3_Acb(X) AB Bias pin frequency 139 * LCCR3_DPC (optional) Double Pixel Clock mode (untested) 140 * 141 * The following should not be defined in LCCR3 142 * LCCR3_HSP, LCCR3_VSP, LCCR0_Pcd(x), LCCR3_Bpp 143 */ 144 u_int lccr3; 145 /* The following should be defined in LCCR4 146 * LCCR4_PAL_FOR_0 or LCCR4_PAL_FOR_1 or LCCR4_PAL_FOR_2 147 * 148 * All other bits in LCCR4 should be left alone. 149 */ 150 u_int lccr4; 151 void (*pxafb_backlight_power)(int); 152 void (*pxafb_lcd_power)(int, struct fb_var_screeninfo *); 153 void (*smart_update)(struct fb_info *); 154 }; 155 void set_pxa_fb_info(struct pxafb_mach_info *hard_pxa_fb_info); 156 void set_pxa_fb_parent(struct device *parent_dev); 157 unsigned long pxafb_get_hsync_time(struct device *dev); 158 159 extern int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int); 160 extern int pxafb_smart_flush(struct fb_info *info); 161