1 /*
2 * File: arch/blackfin/mach-bf533/boards/cm_bf533.c
3 * Based on: arch/blackfin/mach-bf533/boards/ezkit.c
4 * Author: Aidan Williams <aidan@nicta.com.au> Copyright 2005
5 *
6 * Created: 2005
7 * Description: Board description file
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30 #include <linux/device.h>
31 #include <linux/platform_device.h>
32 #include <linux/mtd/mtd.h>
33 #include <linux/mtd/partitions.h>
34 #include <linux/spi/spi.h>
35 #include <linux/spi/flash.h>
36 #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
37 #include <linux/usb/isp1362.h>
38 #endif
39 #include <linux/irq.h>
40 #include <asm/dma.h>
41 #include <asm/bfin5xx_spi.h>
42 #include <asm/portmux.h>
43 #include <asm/dpmc.h>
44
45 /*
46 * Name the Board for the /proc/cpuinfo
47 */
48 const char bfin_board_name[] = "Bluetechnix CM BF533";
49
50 #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
51 /* all SPI peripherals info goes here */
52 #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
53 static struct mtd_partition bfin_spi_flash_partitions[] = {
54 {
55 .name = "bootloader(spi)",
56 .size = 0x00020000,
57 .offset = 0,
58 .mask_flags = MTD_CAP_ROM
59 }, {
60 .name = "linux kernel(spi)",
61 .size = 0xe0000,
62 .offset = 0x20000
63 }, {
64 .name = "file system(spi)",
65 .size = 0x700000,
66 .offset = 0x00100000,
67 }
68 };
69
70 static struct flash_platform_data bfin_spi_flash_data = {
71 .name = "m25p80",
72 .parts = bfin_spi_flash_partitions,
73 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
74 .type = "m25p64",
75 };
76
77 /* SPI flash chip (m25p64) */
78 static struct bfin5xx_spi_chip spi_flash_chip_info = {
79 .enable_dma = 0, /* use dma transfer with this chip*/
80 .bits_per_word = 8,
81 };
82 #endif
83
84 /* SPI ADC chip */
85 #if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE)
86 static struct bfin5xx_spi_chip spi_adc_chip_info = {
87 .enable_dma = 1, /* use dma transfer with this chip*/
88 .bits_per_word = 16,
89 };
90 #endif
91
92 #if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
93 static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
94 .enable_dma = 0,
95 .bits_per_word = 16,
96 };
97 #endif
98
99 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
100 static struct bfin5xx_spi_chip mmc_spi_chip_info = {
101 .enable_dma = 0,
102 .bits_per_word = 8,
103 };
104 #endif
105
106 static struct spi_board_info bfin_spi_board_info[] __initdata = {
107 #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
108 {
109 /* the modalias must be the same as spi device driver name */
110 .modalias = "m25p80", /* Name of spi_driver for this device */
111 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
112 .bus_num = 0, /* Framework bus number */
113 .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
114 .platform_data = &bfin_spi_flash_data,
115 .controller_data = &spi_flash_chip_info,
116 .mode = SPI_MODE_3,
117 },
118 #endif
119
120 #if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE)
121 {
122 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
123 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
124 .bus_num = 0, /* Framework bus number */
125 .chip_select = 2, /* Framework chip select. */
126 .platform_data = NULL, /* No spi_driver specific config */
127 .controller_data = &spi_adc_chip_info,
128 },
129 #endif
130
131 #if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
132 {
133 .modalias = "ad1836-spi",
134 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
135 .bus_num = 0,
136 .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
137 .controller_data = &ad1836_spi_chip_info,
138 },
139 #endif
140
141 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
142 {
143 .modalias = "mmc_spi",
144 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
145 .bus_num = 0,
146 .chip_select = 5,
147 .controller_data = &mmc_spi_chip_info,
148 .mode = SPI_MODE_3,
149 },
150 #endif
151 };
152
153 /* SPI (0) */
154 static struct resource bfin_spi0_resource[] = {
155 [0] = {
156 .start = SPI0_REGBASE,
157 .end = SPI0_REGBASE + 0xFF,
158 .flags = IORESOURCE_MEM,
159 },
160 [1] = {
161 .start = CH_SPI,
162 .end = CH_SPI,
163 .flags = IORESOURCE_IRQ,
164 }
165 };
166
167 /* SPI controller data */
168 static struct bfin5xx_spi_master bfin_spi0_info = {
169 .num_chipselect = 8,
170 .enable_dma = 1, /* master has the ability to do dma transfer */
171 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
172 };
173
174 static struct platform_device bfin_spi0_device = {
175 .name = "bfin-spi",
176 .id = 0, /* Bus number */
177 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
178 .resource = bfin_spi0_resource,
179 .dev = {
180 .platform_data = &bfin_spi0_info, /* Passed to driver */
181 },
182 };
183 #endif /* spi master and devices */
184
185 #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
186 static struct platform_device rtc_device = {
187 .name = "rtc-bfin",
188 .id = -1,
189 };
190 #endif
191
192 #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
193 static struct resource smc91x_resources[] = {
194 {
195 .start = 0x20200300,
196 .end = 0x20200300 + 16,
197 .flags = IORESOURCE_MEM,
198 }, {
199 .start = IRQ_PF0,
200 .end = IRQ_PF0,
201 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
202 },
203 };
204 static struct platform_device smc91x_device = {
205 .name = "smc91x",
206 .id = 0,
207 .num_resources = ARRAY_SIZE(smc91x_resources),
208 .resource = smc91x_resources,
209 };
210 #endif
211
212 static struct resource bfin_gpios_resources = {
213 .start = 0,
214 .end = MAX_BLACKFIN_GPIOS - 1,
215 .flags = IORESOURCE_IRQ,
216 };
217
218 static struct platform_device bfin_gpios_device = {
219 .name = "simple-gpio",
220 .id = -1,
221 .num_resources = 1,
222 .resource = &bfin_gpios_resources,
223 };
224
225 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
226 static struct resource bfin_uart_resources[] = {
227 {
228 .start = 0xFFC00400,
229 .end = 0xFFC004FF,
230 .flags = IORESOURCE_MEM,
231 },
232 };
233
234 static struct platform_device bfin_uart_device = {
235 .name = "bfin-uart",
236 .id = 1,
237 .num_resources = ARRAY_SIZE(bfin_uart_resources),
238 .resource = bfin_uart_resources,
239 };
240 #endif
241
242 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
243 #ifdef CONFIG_BFIN_SIR0
244 static struct resource bfin_sir0_resources[] = {
245 {
246 .start = 0xFFC00400,
247 .end = 0xFFC004FF,
248 .flags = IORESOURCE_MEM,
249 },
250 {
251 .start = IRQ_UART0_RX,
252 .end = IRQ_UART0_RX+1,
253 .flags = IORESOURCE_IRQ,
254 },
255 {
256 .start = CH_UART0_RX,
257 .end = CH_UART0_RX+1,
258 .flags = IORESOURCE_DMA,
259 },
260 };
261
262 static struct platform_device bfin_sir0_device = {
263 .name = "bfin_sir",
264 .id = 0,
265 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
266 .resource = bfin_sir0_resources,
267 };
268 #endif
269 #endif
270
271 #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
272 static struct platform_device bfin_sport0_uart_device = {
273 .name = "bfin-sport-uart",
274 .id = 0,
275 };
276
277 static struct platform_device bfin_sport1_uart_device = {
278 .name = "bfin-sport-uart",
279 .id = 1,
280 };
281 #endif
282
283 #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
284 static struct resource isp1362_hcd_resources[] = {
285 {
286 .start = 0x20308000,
287 .end = 0x20308000,
288 .flags = IORESOURCE_MEM,
289 }, {
290 .start = 0x20308004,
291 .end = 0x20308004,
292 .flags = IORESOURCE_MEM,
293 }, {
294 .start = IRQ_PF4,
295 .end = IRQ_PF4,
296 .flags = IORESOURCE_IRQ,
297 },
298 };
299
300 static struct isp1362_platform_data isp1362_priv = {
301 .sel15Kres = 1,
302 .clknotstop = 0,
303 .oc_enable = 0,
304 .int_act_high = 0,
305 .int_edge_triggered = 0,
306 .remote_wakeup_connected = 0,
307 .no_power_switching = 1,
308 .power_switching_mode = 0,
309 };
310
311 static struct platform_device isp1362_hcd_device = {
312 .name = "isp1362-hcd",
313 .id = 0,
314 .dev = {
315 .platform_data = &isp1362_priv,
316 },
317 .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
318 .resource = isp1362_hcd_resources,
319 };
320 #endif
321
322 static const unsigned int cclk_vlev_datasheet[] =
323 {
324 VRPAIR(VLEV_085, 250000000),
325 VRPAIR(VLEV_090, 376000000),
326 VRPAIR(VLEV_095, 426000000),
327 VRPAIR(VLEV_100, 426000000),
328 VRPAIR(VLEV_105, 476000000),
329 VRPAIR(VLEV_110, 476000000),
330 VRPAIR(VLEV_115, 476000000),
331 VRPAIR(VLEV_120, 600000000),
332 VRPAIR(VLEV_125, 600000000),
333 VRPAIR(VLEV_130, 600000000),
334 };
335
336 static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
337 .tuple_tab = cclk_vlev_datasheet,
338 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
339 .vr_settling_time = 25 /* us */,
340 };
341
342 static struct platform_device bfin_dpmc = {
343 .name = "bfin dpmc",
344 .dev = {
345 .platform_data = &bfin_dmpc_vreg_data,
346 },
347 };
348
349 static struct platform_device *cm_bf533_devices[] __initdata = {
350
351 &bfin_dpmc,
352
353 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
354 &bfin_uart_device,
355 #endif
356
357 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
358 #ifdef CONFIG_BFIN_SIR0
359 &bfin_sir0_device,
360 #endif
361 #endif
362
363 #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
364 &bfin_sport0_uart_device,
365 &bfin_sport1_uart_device,
366 #endif
367
368 #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
369 &rtc_device,
370 #endif
371
372 #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
373 &isp1362_hcd_device,
374 #endif
375
376 #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
377 &smc91x_device,
378 #endif
379
380 #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
381 &bfin_spi0_device,
382 #endif
383
384 &bfin_gpios_device,
385 };
386
cm_bf533_init(void)387 static int __init cm_bf533_init(void)
388 {
389 printk(KERN_INFO "%s(): registering device resources\n", __func__);
390 platform_add_devices(cm_bf533_devices, ARRAY_SIZE(cm_bf533_devices));
391 #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
392 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
393 #endif
394 return 0;
395 }
396
397 arch_initcall(cm_bf533_init);
398