1 /*
2 * Low-Level PCI Support for the SH7751
3 *
4 * Dustin McIntire (dustin@sensoria.com)
5 * Derived from arch/i386/kernel/pci-*.c which bore the message:
6 * (c) 1999--2000 Martin Mares <mj@ucw.cz>
7 *
8 * Ported to the new API by Paul Mundt <lethal@linux-sh.org>
9 * With cleanup by Paul van Gool <pvangool@mimotech.com>
10 *
11 * May be copied or modified under the terms of the GNU General Public
12 * License. See linux/COPYING for more information.
13 *
14 */
15 #undef DEBUG
16
17 #include <linux/init.h>
18 #include <linux/pci.h>
19 #include <linux/types.h>
20 #include <linux/errno.h>
21 #include <linux/delay.h>
22 #include "pci-sh4.h"
23 #include <asm/addrspace.h>
24 #include <asm/io.h>
25
26 /*
27 * Initialization. Try all known PCI access methods. Note that we support
28 * using both PCI BIOS and direct access: in such cases, we use I/O ports
29 * to access config space.
30 *
31 * Note that the platform specific initialization (BSC registers, and memory
32 * space mapping) will be called via the platform defined function
33 * pcibios_init_platform().
34 */
sh7751_pci_init(void)35 static int __init sh7751_pci_init(void)
36 {
37 unsigned int id;
38 int ret;
39
40 pr_debug("PCI: Starting intialization.\n");
41
42 /* check for SH7751/SH7751R hardware */
43 id = pci_read_reg(SH7751_PCICONF0);
44 if (id != ((SH7751_DEVICE_ID << 16) | SH7751_VENDOR_ID) &&
45 id != ((SH7751R_DEVICE_ID << 16) | SH7751_VENDOR_ID)) {
46 pr_debug("PCI: This is not an SH7751(R) (%x)\n", id);
47 return -ENODEV;
48 }
49
50 if ((ret = sh4_pci_check_direct()) != 0)
51 return ret;
52
53 return pcibios_init_platform();
54 }
55 subsys_initcall(sh7751_pci_init);
56
__area_sdram_check(unsigned int area)57 static int __init __area_sdram_check(unsigned int area)
58 {
59 u32 word;
60
61 word = ctrl_inl(SH7751_BCR1);
62 /* check BCR for SDRAM in area */
63 if (((word >> area) & 1) == 0) {
64 printk("PCI: Area %d is not configured for SDRAM. BCR1=0x%x\n",
65 area, word);
66 return 0;
67 }
68 pci_write_reg(word, SH4_PCIBCR1);
69
70 word = (u16)ctrl_inw(SH7751_BCR2);
71 /* check BCR2 for 32bit SDRAM interface*/
72 if (((word >> (area << 1)) & 0x3) != 0x3) {
73 printk("PCI: Area %d is not 32 bit SDRAM. BCR2=0x%x\n",
74 area, word);
75 return 0;
76 }
77 pci_write_reg(word, SH4_PCIBCR2);
78
79 return 1;
80 }
81
sh7751_pcic_init(struct sh4_pci_address_map * map)82 int __init sh7751_pcic_init(struct sh4_pci_address_map *map)
83 {
84 u32 reg;
85 u32 word;
86
87 /* Set the BCR's to enable PCI access */
88 reg = ctrl_inl(SH7751_BCR1);
89 reg |= 0x80000;
90 ctrl_outl(reg, SH7751_BCR1);
91
92 /* Turn the clocks back on (not done in reset)*/
93 pci_write_reg(0, SH4_PCICLKR);
94 /* Clear Powerdown IRQ's (not done in reset) */
95 word = SH4_PCIPINT_D3 | SH4_PCIPINT_D0;
96 pci_write_reg(word, SH4_PCIPINT);
97
98 /*
99 * This code is unused for some boards as it is done in the
100 * bootloader and doing it here means the MAC addresses loaded
101 * by the bootloader get lost.
102 */
103 if (!(map->flags & SH4_PCIC_NO_RESET)) {
104 /* toggle PCI reset pin */
105 word = SH4_PCICR_PREFIX | SH4_PCICR_PRST;
106 pci_write_reg(word, SH4_PCICR);
107 /* Wait for a long time... not 1 sec. but long enough */
108 mdelay(100);
109 word = SH4_PCICR_PREFIX;
110 pci_write_reg(word, SH4_PCICR);
111 }
112
113 /* set the command/status bits to:
114 * Wait Cycle Control + Parity Enable + Bus Master +
115 * Mem space enable
116 */
117 word = SH7751_PCICONF1_WCC | SH7751_PCICONF1_PER |
118 SH7751_PCICONF1_BUM | SH7751_PCICONF1_MES;
119 pci_write_reg(word, SH7751_PCICONF1);
120
121 /* define this host as the host bridge */
122 word = PCI_BASE_CLASS_BRIDGE << 24;
123 pci_write_reg(word, SH7751_PCICONF2);
124
125 /* Set IO and Mem windows to local address
126 * Make PCI and local address the same for easy 1 to 1 mapping
127 * Window0 = map->window0.size @ non-cached area base = SDRAM
128 * Window1 = map->window1.size @ cached area base = SDRAM
129 */
130 word = map->window0.size - 1;
131 pci_write_reg(word, SH4_PCILSR0);
132 word = map->window1.size - 1;
133 pci_write_reg(word, SH4_PCILSR1);
134 /* Set the values on window 0 PCI config registers */
135 word = P2SEGADDR(map->window0.base);
136 pci_write_reg(word, SH4_PCILAR0);
137 pci_write_reg(word, SH7751_PCICONF5);
138 /* Set the values on window 1 PCI config registers */
139 word = PHYSADDR(map->window1.base);
140 pci_write_reg(word, SH4_PCILAR1);
141 pci_write_reg(word, SH7751_PCICONF6);
142
143 /* Set the local 16MB PCI memory space window to
144 * the lowest PCI mapped address
145 */
146 word = PCIBIOS_MIN_MEM & SH4_PCIMBR_MASK;
147 pr_debug("PCI: Setting upper bits of Memory window to 0x%x\n", word);
148 pci_write_reg(word , SH4_PCIMBR);
149
150 /* Map IO space into PCI IO window
151 * The IO window is 64K-PCIBIOS_MIN_IO in size
152 * IO addresses will be translated to the
153 * PCI IO window base address
154 */
155 pr_debug("PCI: Mapping IO address 0x%x - 0x%x to base 0x%x\n",
156 PCIBIOS_MIN_IO, (64 << 10),
157 SH7751_PCI_IO_BASE + PCIBIOS_MIN_IO);
158
159 /* Make sure the MSB's of IO window are set to access PCI space
160 * correctly */
161 word = PCIBIOS_MIN_IO & SH4_PCIIOBR_MASK;
162 pr_debug("PCI: Setting upper bits of IO window to 0x%x\n", word);
163 pci_write_reg(word, SH4_PCIIOBR);
164
165 /* Set PCI WCRx, BCRx's, copy from BSC locations */
166
167 /* check BCR for SDRAM in specified area */
168 switch (map->window0.base) {
169 case SH7751_CS0_BASE_ADDR: word = __area_sdram_check(0); break;
170 case SH7751_CS1_BASE_ADDR: word = __area_sdram_check(1); break;
171 case SH7751_CS2_BASE_ADDR: word = __area_sdram_check(2); break;
172 case SH7751_CS3_BASE_ADDR: word = __area_sdram_check(3); break;
173 case SH7751_CS4_BASE_ADDR: word = __area_sdram_check(4); break;
174 case SH7751_CS5_BASE_ADDR: word = __area_sdram_check(5); break;
175 case SH7751_CS6_BASE_ADDR: word = __area_sdram_check(6); break;
176 }
177
178 if (!word)
179 return 0;
180
181 /* configure the wait control registers */
182 word = ctrl_inl(SH7751_WCR1);
183 pci_write_reg(word, SH4_PCIWCR1);
184 word = ctrl_inl(SH7751_WCR2);
185 pci_write_reg(word, SH4_PCIWCR2);
186 word = ctrl_inl(SH7751_WCR3);
187 pci_write_reg(word, SH4_PCIWCR3);
188 word = ctrl_inl(SH7751_MCR);
189 pci_write_reg(word, SH4_PCIMCR);
190
191 /* NOTE: I'm ignoring the PCI error IRQs for now..
192 * TODO: add support for the internal error interrupts and
193 * DMA interrupts...
194 */
195
196 pci_fixup_pcic();
197
198 /* SH7751 init done, set central function init complete */
199 /* use round robin mode to stop a device starving/overruning */
200 word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_ARBM;
201 pci_write_reg(word, SH4_PCICR);
202
203 return 1;
204 }
205